EP0923014B1 - Reference DC voltage generating apparatus - Google Patents
Reference DC voltage generating apparatus Download PDFInfo
- Publication number
- EP0923014B1 EP0923014B1 EP98403068A EP98403068A EP0923014B1 EP 0923014 B1 EP0923014 B1 EP 0923014B1 EP 98403068 A EP98403068 A EP 98403068A EP 98403068 A EP98403068 A EP 98403068A EP 0923014 B1 EP0923014 B1 EP 0923014B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- transistor
- drain
- source
- voltage
- type mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
- G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
Definitions
- the present invention relates to a device for generation of a reference DC voltage. More specifically, the invention relates to a device used to obtain a reference voltage at output substantially equal to half of a DC voltage supplied to this device.
- circuits for generating a reference voltage include generally passive elements and / or transistors bipolar.
- a passive element such as an ohmic resistance, for example, often has large variations in its value, of the order of magnitude of ⁇ 20%.
- some of these components are relatively expensive: for example, a bipolar transistor, longer to manufacture than a transistor MOS is more expensive and more difficult to to integrate.
- the object of the present invention is to overcome the disadvantages mentioned above by proposing a device for generation of a reference DC voltage achieved exclusively from MOS transistors.
- the use of such transistors has the advantage of allowing, compared to aforementioned components, at low cost, more integration easy, gain in integration density, low static consumption and obtaining a voltage of reference with an accuracy of ⁇ 1%.
- the operating principle of the proposed device is based on compensation for voltage variations in depending on ambient temperature and / or operating of the device, variations in the temperature of functioning being linked to the quality of the manufacturing of the device.
- the invention also proposes the use of a device of the above type in an integrated circuit.
- the reference direct voltage generation of the invention consists of three main parts: an entrance floor 10, an intermediate stage 11 and an output stage 12.
- the arrows designate the connection to a direct supply voltage, for example 5 V, or of 3 V.
- the triangles designate the connection to ground.
- Input stage 10 forms a voltage divider, which provides a first direct current NBGP output substantially equal to half of the supply voltage.
- the input stage 10 has two branches 101 and 102.
- the first branch 101 is connected to the power supply and the second branch 102 is connected to ground.
- the elements components of each branch are chosen so that when the ambient and / or operating temperature varies, each branch reacts differently.
- the two branches 101, 102 are made from P-type and N-type MOS transistors.
- the transistors whose reference sign begins by "TP” are P-type MOS transistors, and the transistors whose reference sign begins with "TN” are N type MOS transistors.
- the first branch 101 comprises a first transistor TP0 and a second transistor TN0.
- the second grid transistor TN0 and the drain of the first transistor TP0 are connected to food.
- the source of the first transistor TP0 is connected to the drain of the second transistor TN0, that is to say that the first and second transistors TP0 and TN0 are mounted in series.
- the second branch 102 includes a third transistor TP1 and a fourth transistor TN2 mounted in series: the gate of the third transistor TP1 and the source of the fourth transistor TN2 are connected to ground, and the source of the third transistor TP1 is connected to the drain of the fourth transistor TN2.
- the two branches 101, 102 are interconnected as follows: the grids of the first and fourth TP0 and TN2 transistors are connected to each other at a point AT ; the source of the second transistor TN0 is connected to the drain of the third transistor TP1 at a point B, and at the gates first and fourth transistors TP0 and TN2, by connection of points A and B.
- the logic inverter function of such a circuit is short-circuited due to the connection between these points A and B.
- branches 101 and 102 do not have the same behavior.
- I ds W 2L - ⁇ - C ox - (V GS - V T ) 2
- I ds denotes the drain-source current
- W denotes the width of the channel
- L denotes the length of the channel
- ⁇ denotes electrical mobility
- C ox denotes the capacity per unit area of the gate oxide
- V GS denotes the voltage between the gate and the source
- V T denotes the threshold voltage of the transistor considered.
- the input stage 10 is equivalent to a potentiometric divider with two resistances, the first of which, R TP0, TN0 , is the equivalent of the first and second transistors TP0, TN0 , and the second, R TP1, TN2 , is the equivalent of the third and fourth transistors TP1, TN2.
- Figure 3 shows the variations of the first continuous voltage MBGP as a function of the temperature in a particular example, where the DC supply voltage is equal to 5 v, and where we vary the temperature ambient between -40 ° C and + 125 ° C. There is a decrease substantially linear to NBGP as the temperature rises.
- the third DC voltage NREF obtained in output of the DC voltage generation device. We sees that the voltage NREF is substantially constant and equal at 2.5 V, half the DC voltage Power.
- the point B of the input stage 10 is connected to the entrance to the intermediate floor 11.
- the role of the floor intermediary 11 is to provide protection against switching noise, such as conducted noise or noise radiated, generated by the various elements of the circuit surrounding.
- the first direct voltage NBGP supplied by the input stage 11 has a static component and a dynamic component.
- the intermediate stage 11 performs a resistive and capacitive type filtering analog NBGP to remove the dynamic component.
- the floor intermediate 11 includes a framed resistive cell 112 of two capacitive cells 111 and 113.
- the first capacitive cell 111 comprises a fifth transistor TP2 and a sixth transistor TN1.
- the TP2 and TN1 grids are connected to each other as well as to point B of the input stage 10.
- the source and the drain of TP2 are connected to the power supply, and the source and drain of TN1 are connected to ground.
- the first capacitive cell 111 is equivalent to a pair of capacitors, the first of which, C TP2 , is formed by the fifth transistor TP2, and the second, C TN1 , is formed by the sixth transistor TN1.
- the resistive cell 112 has a seventh TN3 transistor and an eighth TP3 transistor.
- the grid of TN3 is connected to the power supply.
- TP3 grid is connected to ground.
- the source of TN3 and the drain of TP3 are connected between them and on the grids of the fifth and sixth TP2 and TN1 transistors of the first capacitive cell 111, and have a potential equal to the first direct voltage NBGP.
- the resistive cell 112 is equivalent to a resistor R TN3, TP3 shown in the equivalent diagram in FIG. 2.
- the second capacitive cell 113 includes a ninth transistor TP4 and a tenth transistor TN5.
- the source and drain of TP4 are connected to the power supply.
- the source and drain of TN5 are connected to ground.
- the gates of TP4 and TN5 are connected together as well as to the drain of the seventh transistor TN3 and to the source of the eighth transistor TP3 of the resistive cell, and constitute the output of the intermediate stage.
- the second capacitive cell 113 of structure analogous to the first capacitive cell 111, also has an equivalent analogous diagram, comprising a pair of capacitors shown in FIG. 2, the first of which, C TP4 , is formed by the ninth transistor TP4, and the second, C TN5 , is formed by the tenth transistor TN5.
- the drain of the seventh transistor TN3 and the source of the eighth transistor TP3 are interconnected and have a potential equal to a second NARF direct voltage.
- the variations in the NARF voltage as a function of the temperature are illustrated by the graph in Figure 4, in a particular example, where, as well as for curves of Figure 3, the DC supply voltage is equal to 5 V, and the ambient temperature is varied between -40 ° C and + 125 ° C. We also represented the tension NREF, for comparison.
- the variations of the second NARF direct voltage are substantially identical to those of the first direct voltage NBGP: we observe a decrease quasi-linear of NARF when the temperature increases.
- the output stage 12 has a structure similar to that of input stage 10, except for points C and D which, unlike points A and B, are not not interconnected, which gives the output stage 12, in addition to its potentiometric divider function, that of a logic inverter.
- the output stage 12 includes a first branch 121, which includes an eleventh TP5 transistor and a twelfth transistor TN6, the gate of TN6 and the drain of TP5 being connected to the power supply, the source of TP5 being connected to the TN6 drain.
- the output stage 12 also includes a second branch 122, which includes a thirteenth transistor TP7 and a fourteenth transistor TN8, the gate of TP7 and the source of TN8 being connected to ground, the source of TP7 being connected to the TN8 drain, the TP5 and TN8 grids being connected between them at point C, as well as at the exit of the floor intermediate 11.
- a second branch 122 which includes a thirteenth transistor TP7 and a fourteenth transistor TN8, the gate of TP7 and the source of TN8 being connected to ground, the source of TP7 being connected to the TN8 drain, the TP5 and TN8 grids being connected between them at point C, as well as at the exit of the floor intermediate 11.
- the source of TN6 is connected to the drain of TP7 at the point D, which constitutes the output of the output stage 12, and the whole system.
- Point D is at NREF potential.
- the output stage 12 also acts as a inverter against voltage variations induced by temperature variations.
- NARF voltage result of voltage filtering NBGP which tends to decrease, also tends to decrease.
- NREF tension would also tend to decrease due to the increase in temperature; however, due to the logic inversion carried out by the output stage 12, the tendency to decrease NARF voltage is transformed into an increasing trend in NREF tension result, which thus compensates for the NREF voltage issued.
- NREF undergoes slight variations, illustrated in a particular case by FIG. 5, where the DC supply voltage is 5 V, and where the value of NREF has been noted for ambient temperatures varying from - 40 ° C to + 125 ° C.
- the output stage 12 is equivalent to a series circuit comprising, in cascade, on the one hand, a potentiometric divider with two resistances, and on the other hand, a logic inverter INV.
- the first resistor of the divider, R TP5, TN6 is the equivalent of the eleventh and twelfth transistors TP5, TN6, and the second resistor of the divider, R TP7, TN8 , is the equivalent of the thirteenth and fourteenth transistors TP7, TN8.
- the lengths and the widths of the channels of the different transistors are chosen so that they verify the following relationships: L (TN2) ⁇ 4 x L (TN0) L (TN8) ⁇ 2 x L (TN6) L (TN6) ⁇ 2 x L (TN0) L (TP7) ⁇ 2 x L (TP1) W (TP3) ⁇ 2 x W (TN3) where L and W respectively designate the length and the width of the transistors whose reference numbers are indicated in brackets.
- the invention therefore allows to generate a half reference voltage Power. Tests have shown that accuracy obtained is around ⁇ 1% for a 5 V supply ⁇ 10%.
- the invention can be used in many types of integrated circuits, for example for generation logic signals from a low amplitude signal having as its resting point the reference voltage produced by the invention.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Logic Circuits (AREA)
- Control Of Electrical Variables (AREA)
Description
La présente invention concerne un dispositif de génération d'une tension continue de référence. Plus précisément, l'invention se rapporte à un dispositif permettant d'obtenir en sortie une tension de référence sensiblement égale à la moitié d'une tension continue d'alimentation fournie à ce dispositif.The present invention relates to a device for generation of a reference DC voltage. More specifically, the invention relates to a device used to obtain a reference voltage at output substantially equal to half of a DC voltage supplied to this device.
On connaít de nombreux circuits de génération d'une tension de référence. Cependant ces circuits comprennent généralement des éléments passifs et/ou des transistors bipolaires. Lorsqu'on tente de réaliser l'intégration de tels composants dans une matrice en silicium, de type logique, on se heurte à plusieurs inconvénients. D'une part, un élément passif tel qu'une résistance ohmique, par exemple, présente souvent de fortes variations de sa valeur, de l'ordre de grandeur de ± 20%. D'autre part, certains de ces composants sont relativement coûteux : par exemple, un transistor bipolaire, plus long à fabriquer qu'un transistor MOS, est plus cher, et est en outre plus difficile à intégrer.We know many circuits for generating a reference voltage. However these circuits include generally passive elements and / or transistors bipolar. When we try to achieve the integration of such components in a silicon matrix, of the type logical, there are several disadvantages. Firstly, a passive element such as an ohmic resistance, for example, often has large variations in its value, of the order of magnitude of ± 20%. On the other hand, some of these components are relatively expensive: for example, a bipolar transistor, longer to manufacture than a transistor MOS is more expensive and more difficult to to integrate.
La présente invention a pour but de s'affranchir des inconvénients précités en proposant un dispositif de génération d'une tension continue de référence réalisé exclusivement à partir de transistors MOS. L'utilisation de tels transistors a l'avantage de permettre, par rapport aux composants précités, à faible coût, une intégration plus facile, un gain en densité d'intégration, une faible consommation statique et l'obtention d'une tension de référence avec une précision de l'ordre de ± 1%. The object of the present invention is to overcome the disadvantages mentioned above by proposing a device for generation of a reference DC voltage achieved exclusively from MOS transistors. The use of such transistors has the advantage of allowing, compared to aforementioned components, at low cost, more integration easy, gain in integration density, low static consumption and obtaining a voltage of reference with an accuracy of ± 1%.
Le principe de fonctionnement du dispositif proposé repose sur la compensation des variations de tension en fonction de la température ambiante et/ou de fonctionnement du dispositif, les variations de la température de fonctionnement étant liées à la qualité du procédé de fabrication du dispositif.The operating principle of the proposed device is based on compensation for voltage variations in depending on ambient temperature and / or operating of the device, variations in the temperature of functioning being linked to the quality of the manufacturing of the device.
Afin d'atteindre le but précité, la présente invention
propose un dispositif de génération d'une tension continue
de référence sensiblement égale à la moitié d'une tension
continue d'alimentation fournie à ce dispositif, remarquable
en ce qu'il comprend :
Dans un mode particulier de réalisation, la première
branche de l'étage d'entrée comprend un premier transistor
MOS de type P et un deuxième transistor MOS de type N, la
grille du deuxième transistor et le drain du premier
transistor étant reliés à l'alimentation, la source du
premier transistor étant reliée au drain du deuxième
transistor,
Dans un mode particulier de réalisation, l'étage
intermédiaire comprend une première cellule capacitive,
comportant un cinquième transistor MOS de type P et un
sixième transistor MOS de type N, les grilles des cinquième
et sixième transistors étant reliées entre elles ainsi qu'à
la sortie de l'étage d'entrée, la source et le drain du
cinquième transistor étant reliés à l'alimentation, la
source et le drain du sixième transistor étant reliés à la
masse,
Dans un mode particulier de réalisation, la première
branche de l'étage de sortie comprend un onzième transistor
MOS de type P et un douzième transistor MOS de type N, la
grille du douzième transistor et le drain du onzième
transistor étant reliés à l'alimentation, la source du
onzième transistor étant reliée au drain du douzième
transistor,
L'invention propose également l'utilisation d'un dispositif du type ci-dessus dans un circuit intégré.The invention also proposes the use of a device of the above type in an integrated circuit.
D'autres aspects et avantages de la présente invention apparaítront à la lecture de la description détaillée qui suit de modes particuliers de réalisation, donnés à titre d'exemples non limitatifs.Other aspects and advantages of the present invention will appear on reading the detailed description which follows particular embodiments, given as non-limiting examples.
La présente invention se réfère aux dessins qui l'accompagnent, dans lesquels :
- la figure 1 est un schéma électrique d'un circuit à base de transistors MOS réalisant le dispositif de l'invention, dans un mode particulier de réalisation ;
- la figure 2 est un schéma électrique équivalent du circuit de la figure 1, illustrant les fonctions résistive, capacitive et d'inversion thermique remplies par les divers transistors ;
- la figure 3 est un graphique représentant la troisième tension continue NREF et l'évolution de la première tension continue NBGP en fonction de la température ambiante, pour une tension continue d'alimentation de 5 volts et pour une gamme de températures ambiantes de -40°C à +125°C ;
- la figure 4 est un graphique représentant la troisième tension continue NREF et l'évolution de la deuxième tension continue NARF en fonction de la température, pour une tension continue d'alimentation de 5 volts et pour une gamme de températures ambiantes de -40°C à +125°C ; et
- la figure 5 est un graphique représentant le détail de l'évolution de la troisième tension continue NREF dans l'intervalle [2,4995 V ; 2,4998 V], illustrant ses très faibles variations, pour une gamme de températures ambiantes de -40°C à +125°C.
- FIG. 1 is an electrical diagram of a circuit based on MOS transistors implementing the device of the invention, in a particular embodiment;
- FIG. 2 is an equivalent electrical diagram of the circuit of FIG. 1, illustrating the resistive, capacitive and thermal inversion functions fulfilled by the various transistors;
- FIG. 3 is a graph representing the third DC voltage NREF and the evolution of the first DC voltage NBGP as a function of the ambient temperature, for a DC supply voltage of 5 volts and for a range of ambient temperatures of -40 °. C at + 125 ° C;
- FIG. 4 is a graph showing the third DC voltage NREF and the evolution of the second DC voltage NARF as a function of temperature, for a DC supply voltage of 5 volts and for a range of ambient temperatures of -40 ° C. at + 125 ° C; and
- FIG. 5 is a graph showing the detail of the evolution of the third DC voltage NREF in the interval [2.4995 V; 2.4998 V], illustrating its very slight variations, for a range of ambient temperatures from -40 ° C to + 125 ° C.
Comme le montre la figure 1, le dispositif de
génération de tension continue de référence de l'invention
se compose de trois parties principales : un étage d'entrée
10, un étage intermédiaire 11 et un étage de sortie 12.As shown in Figure 1, the
reference direct voltage generation of the invention
consists of three main parts: an
Sur la figure 1, les flèches désignent la connexion à une tension continue d'alimentation, par exemple de 5 V, ou de 3 V. Les triangles désignent la connexion à la masse.In Figure 1, the arrows designate the connection to a direct supply voltage, for example 5 V, or of 3 V. The triangles designate the connection to ground.
L'étage d'entrée 10 forme un diviseur de tension, qui
fournit en sortie une première tension continue NBGP
sensiblement égale à la moitié de la tension d'alimentation.
L'étage d'entrée 10 comporte deux branches 101 et 102. La
première branche 101 est reliée à l'alimentation et la
deuxième branche 102 est reliée à la masse. Les éléments
constitutifs de chaque branche sont choisis de façon que
lorsque la température ambiante et/ou de fonctionnement
varie, chaque branche réagit différemment.
Dans le mode particulier de réalisation illustré par la
figure 1, les deux branches 101, 102 sont réalisées à partir
de transistors MOS de type P et de type N. Dans toute la
suite, les transistors dont le signe de référence commence
par "TP" sont des transistors MOS de type P, et les
transistors dont le signe de référence commence par "TN"
sont des transistors MOS de type N.In the particular embodiment illustrated by the
Figure 1, the two
La première branche 101 comprend un premier transistor
TP0 et un deuxième transistor TN0. La grille du deuxième
transistor TN0 et le drain du premier transistor TP0 sont
reliés à l'alimentation. La source du premier transistor TP0
est reliée au drain du deuxième transistor TN0, c'est-à-dire
que les premier et deuxième transistors TP0 et TN0 sont
montés en série.The
La deuxième branche 102 comprend un troisième
transistor TP1 et un quatrième transistor TN2 montés en
série : la grille du troisième transistor TP1 et la source
du quatrième transistor TN2 sont reliées à la masse, et la
source du troisième transistor TP1 est reliée au drain du
quatrième transistor TN2.The
Les deux branches 101, 102 sont reliées entre elles
comme suit : les grilles des premier et quatrième
transistors TP0 et TN2 sont reliées entre elles en un point
A ; la source du deuxième transistor TN0 est reliée au drain
du troisième transistor TP1 en un point B, et aux grilles
des premier et quatrième transistors TP0 et TN2, par
connexion des points A et B. La fonction inverseur logique
d'un tel circuit se trouve court-circuitée du fait de la
liaison entre ces points A et B.The two
Comme indiqué plus haut, lorsque la température
ambiante et/ou de fonctionnement varie, les branches 101 et
102 n'ont pas le même comportement. On choisit la longueur L
du canal des transistors TP0, TN0, TP1, TN2 de telle façon
que lorsque la température augmente, la tension de seuil des
premier et deuxième transistors TP0, TN0 augmente plus
fortement que la tension de seuil des troisième et quatrième
transistors TP1, TN2.As indicated above, when the temperature
ambient and / or operating varies,
On rappelle l'équation du comportement électrique des
transistors PMOS et NMOS :
Lorsque la température augmente, du fait que VT augmente plus fortement pour l'ensemble (TP0, TN0) que pour l'ensemble (TP1, TN2), l'impédance, liée à l'inverse du courant drain-source, qui diminue plus fortement pour l'ensemble (TP0, TN0) que pour l'ensemble (TP1, TN2), augmente plus fortement pour l'ensemble (TP0, TN0) que pour l'ensemble (TP1, TN2). Les deux branches ont donc un comportement asymétrique en réponse aux variations de température. Lorsque la température de fonctionnement augmente, cette asymétrie permet d'engendrer une diminution de la première tension continue NBGP fournie par l'étage d'entrée. Inversement, lorsque la température de fonctionnement diminue, une augmentation de la première tension continue NBGP est susceptible d'apparaítre.When the temperature increases, because V T increases more strongly for the set (TP0, TN0) than for the set (TP1, TN2), the impedance, linked to the inverse of the drain-source current, which decreases more strongly for the set (TP0, TN0) than for the set (TP1, TN2), increases more strongly for the set (TP0, TN0) than for the set (TP1, TN2). The two branches therefore have an asymmetrical behavior in response to temperature variations. When the operating temperature increases, this asymmetry makes it possible to generate a reduction in the first direct voltage NBGP supplied by the input stage. Conversely, when the operating temperature decreases, an increase in the first direct voltage NBGP is likely to appear.
Ces variations de température de fonctionnement sont liées à la qualité du procédé de fabrication des transistors et à la température ambiante. En effet, dans le cas d'un procédé de fabrication dit lent, c'est-à-dire ayant des paramètres de fabrication (précision des machines utilisées, qualité de diffusion, etc.) relativement mauvais, les transistors obtenus présentent une rapidité de commutation relativement faible. Inversement, dans le cas d'un procédé de fabrication dit rapide, ayant des paramètres relativement bons, les transistors réalisés ont une plus grande rapidité de commutation. Plus le procédé de fabrication est lent, plus la tension de seuil du transistor est élevée, ce qui réduit d'autant plus l'effet des variations de la température de fonctionnement et de la température ambiante sur la tension.These variations in operating temperature are linked to the quality of the transistor manufacturing process and at room temperature. Indeed, in the case of a so-called slow manufacturing process, i.e. having manufacturing parameters (precision of the machines used, broadcast quality, etc.) relatively poor, transistors obtained have a switching speed relatively small. Conversely, in the case of a process manufacturing said to be rapid, having relatively parameters good, the transistors produced have a higher speed of commutation. The slower the manufacturing process, the higher the threshold voltage of the transistor, which further reduces the effect of variations in operating temperature and room temperature on tension.
Comme le montre le schéma électrique équivalent de
la figure 2, l'étage d'entrée 10 est équivalent à un
diviseur potentiométrique à deux résistances, dont la
première, RTP0,TN0, est l'équivalent des premier et deuxième
transistors TP0, TN0, et la deuxième, RTP1,TN2, est
l'équivalent des troisième et quatrième transistors TP1,
TN2.As shown in the equivalent electrical diagram in FIG. 2, the
La figure 3 représente les variations de la première tension continue MBGP en fonction de la température dans un exemple particulier, où la tension continue d'alimentation est égale à 5 v, et où on fait varier la température ambiante entre -40°C et +125°C. On observe une baisse sensiblement linéaire de NBGP au fur et à mesure que la température augmente. A titre de comparaison, on a également représenté la troisième tension continue NREF obtenue en sortie du dispositif de génération de tension continue. On voit que la tension NREF est sensiblement constante et égale à 2,5 V, soit la moitié de la tension continue d'alimentation. Figure 3 shows the variations of the first continuous voltage MBGP as a function of the temperature in a particular example, where the DC supply voltage is equal to 5 v, and where we vary the temperature ambient between -40 ° C and + 125 ° C. There is a decrease substantially linear to NBGP as the temperature rises. For comparison, we also have represented the third DC voltage NREF obtained in output of the DC voltage generation device. We sees that the voltage NREF is substantially constant and equal at 2.5 V, half the DC voltage Power.
Le point B de l'étage d'entrée 10 est relié à
l'entrée de l'étage intermédiaire 11. Le rôle de l'étage
intermédiaire 11 est d'apporter une protection contre le
bruit de commutation, du type bruit conduit ou bruit
rayonné, engendré par les divers éléments du circuit
environnant.The point B of the
La première tension continue NBGP fournie par
l'étage d'entrée 11 présente une composante statique et une
composante dynamique. L'étage intermédiaire 11 effectue un
filtrage du type résistif et capacitif de la valeur
analogique NBGP pour en supprimer la composante dynamique.The first direct voltage NBGP supplied by
the
Dans un mode particulier de réalisation, l'étage
intermédiaire 11 comprend une cellule résistive 112 encadrée
de deux cellules capacitives 111 et 113.In a particular embodiment, the floor
intermediate 11 includes a framed
Dans le mode particulier de réalisation illustré par
la figure 1, la première cellule capacitive 111 comporte un
cinquième transistor TP2 et un sixième transistor TN1. Les
grilles de TP2 et TN1 sont reliées entre elles ainsi qu'au
point B de l'étage d'entrée 10. La source et le drain de TP2
sont reliés à l'alimentation, et la source et le drain de
TN1 sont reliés à la masse.In the particular embodiment illustrated by
FIG. 1, the first
Comme le montre la figure 2, la première cellule
capacitive 111 est équivalente à une paire de condensateurs,
dont le premier, CTP2, est formé par le cinquième transistor
TP2, et le deuxième, CTN1, est formé par le sixième
transistor TN1.As shown in FIG. 2, the first
La cellule résistive 112 comporte un septième
transistor TN3 et un huitième transistor TP3. La grille de
TN3 est reliée à l'alimentation. La grille de TP3 est reliée
à la masse. La source de TN3 et le drain de TP3 sont reliés
entre eux ainsi qu'aux grilles des cinquième et sixième
transistors TP2 et TN1 de la première cellule capacitive
111, et ont un potentiel égal à la première tension continue
NBGP.The
La cellule résistive 112 est équivalente à une
résistance RTN3,TP3 représentée sur le schéma équivalent de la
figure 2.The
La deuxième cellule capacitive 113 comporte un
neuvième transistor TP4 et un dixième transistor TN5. La
source et le drain de TP4 sont reliés à l'alimentation. La
source et le drain de TN5 sont reliés à la masse. Les
grilles de TP4 et TN5 sont reliées entre elles ainsi qu'au
drain du septième transistor TN3 et à la source du huitième
transistor TP3 de la cellule résistive, et constituent la
sortie de l'étage intermédiaire. La deuxième cellule
capacitive 113, de structure analogue à la première cellule
capacitive 111, a également un schéma équivalent analogue,
comportant une paire de condensateurs représentés sur la
figure 2, dont le premier, CTP4, est formé par le neuvième
transistor TP4, et le deuxième, CTN5, est formé par le
dixième transistor TN5.The second
Le drain du septième transistor TN3 et la source du huitième transistor TP3 sont reliés entre eux et ont un potentiel égal à une deuxième tension continue NARF.The drain of the seventh transistor TN3 and the source of the eighth transistor TP3 are interconnected and have a potential equal to a second NARF direct voltage.
Les variations de la tension NARF en fonction de la température sont illustrées par le graphique de la figure 4, dans un exemple particulier, où, de même que pour les courbes de la figure 3, la tension continue d'alimentation est égale à 5 V, et on fait varier la température ambiante entre -40°C et +125°C. On a également représenté la tension NREF, à titre de comparaison. Les variations de la deuxième tension continue NARF sont sensiblement identiques à celles de la première tension continue NBGP : on observe une baisse quasi linéaire de NARF lorsque la température augmente.The variations in the NARF voltage as a function of the temperature are illustrated by the graph in Figure 4, in a particular example, where, as well as for curves of Figure 3, the DC supply voltage is equal to 5 V, and the ambient temperature is varied between -40 ° C and + 125 ° C. We also represented the tension NREF, for comparison. The variations of the second NARF direct voltage are substantially identical to those of the first direct voltage NBGP: we observe a decrease quasi-linear of NARF when the temperature increases.
Il reste à compenser cette baisse pour obtenir en
sortie du dispositif une tension NREF sensiblement constante
et égale à la moitié de la tension continue d'alimentation.
C'est le rôle joué par l'étage de sortie 12, qui remplit une
double fonction d'inversion logique et de compensation des
variations de tension en fonction de la température.It remains to compensate for this drop to obtain
device output a substantially constant NREF voltage
and equal to half of the DC supply voltage.
This is the role played by the
Dans le mode particulier de réalisation représenté
sur la figure 1, l'étage de sortie 12 a une structure
analogue à celle de l'étage d'entrée 10, à l'exception des
points C et D qui, contrairement aux points A et B, ne sont
pas reliés entre eux, ce qui confère à l'étage de sortie 12,
outre sa fonction de diviseur potentiométrique, celle d'un
inverseur logique.In the particular embodiment shown
in FIG. 1, the
L'étage de sortie 12 comprend une première branche
121, qui comporte un onzième transistor TP5 et un douzième
transistor TN6, la grille de TN6 et le drain de TP5 étant
reliés à l'alimentation, la source de TP5 étant reliée au
drain de TN6.The
L'étage de sortie 12 comprend également une deuxième
branche 122, qui comporte un treizième transistor TP7 et un
quatorzième transistor TN8, la grille de TP7 et la source de
TN8 étant reliées à la masse, la source de TP7 étant reliée
au drain de TN8, les grilles de TP5 et TN8 étant reliées
entre elles au point C, ainsi qu'à la sortie de l'étage
intermédiaire 11.The
La source de TN6 est reliée au drain de TP7 au point
D, qui constitue la sortie de l'étage de sortie 12, et de
l'ensemble du dispositif. Le point D est au potentiel NREF.The source of TN6 is connected to the drain of TP7 at the point
D, which constitutes the output of the
On choisit les longueurs de canal des transistors
TP5, TN6, TP7, TN8 de telle façon que lorsque la température
varie, les tensions de seuil des transistors TP5 et TN6
varient plus fortement que les tensions de seuil des
transistors TP7 et TN8, et de telle façon que le
comportement asymétrique des deux branches 121, 122,
analogue à celui, déjà décrit, des deux branches 101, 102 de
l'étage d'entrée 10, induise des variations de tension de
même sens que celles de l'étage d'entrée, mais plus faibles.We choose the channel lengths of the transistors
TP5, TN6, TP7, TN8 in such a way that when the temperature
varies, the threshold voltages of the TP5 and TN6 transistors
vary more strongly than the threshold voltages of the
transistors TP7 and TN8, and in such a way that the
asymmetric behavior of the two
L'étage de sortie 12 agit en outre comme un
inverseur vis-à-vis des variations de tension induites par
les variations de température.The
Ainsi, en cas d'augmentation de la température par
exemple, la tension NARF, résultat du filtrage de la tension
NBGP qui tend à diminuer, a également tendance à diminuer.
La tension NREF tendrait aussi à diminuer du fait de
l'augmentation de température ; cependant, du fait de
l'inversion logique réalisée par l'étage de sortie 12, la
tendance à la diminution de la tension NARF est transformée
en une tendance à l'augmentation de la tension NREF
résultance, ce qui permet de compenser ainsi la tension NREF
délivrée.Thus, in the event of an increase in temperature by
example, NARF voltage, result of voltage filtering
NBGP which tends to decrease, also tends to decrease.
NREF tension would also tend to decrease due to
the increase in temperature; however, due to
the logic inversion carried out by the
Inversement, en cas de baisse de température, la tendance à l'augmentation de NREF est compensée par l'inversion logique de la tendance à l'augmentation de NARF, qui se traduit par une tendance à la diminution de NREF venant compenser sa tendance à l'augmentation.Conversely, in the event of a temperature drop, the increasing trend of NREF is offset by the logical reversal of the upward trend in NARF, which results in a decreasing trend in NREF compensating for its increasing trend.
Il en résulte que la tension NREF subit de faibles variations, illustrées dans un cas particulier par la figure 5, où la tension continue d'alimentation est de 5 V, et où on a relevé la valeur de NREF pour des températures ambiantes variant de -40°C à +125°C. On observe que NREF est stable et égale à 2,49980 V pour une plage de températures sensiblement comprises entre +5°C et +65°C, et présente des variations ne dépassant pas 2,4998 - 2,4995 = 3.10-4 V dans les intervalles de température [-40°C, +5°C] et [+65°C, +125°C].It follows that the voltage NREF undergoes slight variations, illustrated in a particular case by FIG. 5, where the DC supply voltage is 5 V, and where the value of NREF has been noted for ambient temperatures varying from - 40 ° C to + 125 ° C. We observe that NREF is stable and equal to 2.49980 V for a temperature range appreciably between + 5 ° C and + 65 ° C, and presents variations not exceeding 2.4998 - 2.4995 = 3.10 -4 V in the temperature ranges [-40 ° C, + 5 ° C] and [+ 65 ° C, + 125 ° C].
Comme le montre la figure 2, l'étage de sortie 12
est équivalent à un montage série comprenant, en cascade,
d'une part, un diviseur potentiométrique à deux résistances,
et d'autre part, un inverseur logique INV. La première
résistance du diviseur, RTP5,TN6, est l'équivalent des onzième
et douzième transistors TP5, TN6, et la deuxième résistance
du diviseur, RTP7,TN8, est l'équivalent des treizième et
quatorzième transistors TP7, TN8.As shown in FIG. 2, the
Dans un exemple particulier de réalisation, qui
correspond aux courbes des figures 3 à 5, on choisit les
longueurs et les largeurs de canal des différents
transistors de façon qu'elles vérifient les relations
suivantes :
Comme décrit précédemment, l'invention permet donc d'engendrer une tension de référence de type moitié d'alimentation. Des tests ont montré que la précision obtenue est de l'ordre de ± 1% pour une alimentation de 5 V ± 10%. As described above, the invention therefore allows to generate a half reference voltage Power. Tests have shown that accuracy obtained is around ± 1% for a 5 V supply ± 10%.
L'invention peut être utilisée dans de nombreux types de circuits intégrés, par exemple pour la génération de signaux logiques à partir d'un signal de faible amplitude ayant pour point de repos la tension de référence produite par l'invention.The invention can be used in many types of integrated circuits, for example for generation logic signals from a low amplitude signal having as its resting point the reference voltage produced by the invention.
Claims (5)
- A device for generating a DC reference voltage approximately equal to half a DC supply voltage provided to said device, said device including:an input stage, forming a first potentiometric divider comprising a first branch connected to the power supply voltage and a second branch connected to the reference potential, the first and second branches having an asymmetric behaviour in response to variations in the room and/or operating temperature, the variations in operating temperature being linked to the quality of the manufacturing process of the device, said input stage supplying a first DC voltage (NBGP) with a static component and a dynamic component;an intermediate stage, forming a resistive and capacitive filter, which receives the first DC input voltage (NGBP), eliminates its dynamic component, and supplies a second DC output voltage (NARF); andan output stage, forming a second potentiometric divider comprising a first branch connected to said power supply voltage and a second branch connected to said reference potential, the first and second branches of said second potentiometric divider having an asymmetric behaviour similar to the behaviour of the first and second branches of said first potentiometric divider, the relative voltage variations of said second divider as a function of the room and/or operating temperature being however smaller than the relative voltage variations of said first divider, the variations in operating temperature being linked to the quality of the manufacturing process, said output stage comprising in addition a logic inverter function, said output stage supplying a third DC voltage (NREF), the variations of which as a function of the room and/or operating temperature, said variations in operating temperature being linked to the quality of the manufacturing process, are the inverse of those of the said second DC voltage (NARF), said variations in the second DC voltage (NARF) being thus compensated.
- The device according to claim 1, wherein
the first branch of said input stage includes a first p-type MOS transistor (TP0) and a second n-type MOS transistor (TN0), the gate of said second transistor (TN0) and the drain of said first transistor (TP0) being connected to said power supply voltage, the source of said first transistor (TP0) being connected to the drain of said second transistor (TN0),
the second branch of said input stage includes a third p-type MOS transistor (TP1) and a fourth n-type MOS transistor (TN2), the gate of said third transistor (TP1) and the source of said fourth transistor (TN2) being connected to said reference potential, the source of said third transistor (TP1) being connected to the drain of said fourth transistor (TN2),
the gates of said first and fourth transistors (TP0, TN2) being connected to each other, the source of said second transistor (TN0) being connected to the drain of said third transistor (TP1) and to the gates of said first and fourth transistors (TP0, TN2), and constituting an output of the input stage. - The device according to claims 1 or 2, wherein said intermediate stage includes:a first capacitive cell, comprising a fifth p-type MOS transistor (TP2) arid a sixth n-type MOS transistor (TN1), the gates of said fifth and sixth transistors (TP2, TN1) being connected to each other and to the output of said input stage, the source and the drain of said fifth transistor (TP2) being connected to said power supply voltage, the source and the drain of said sixth transistor (TN1) being connected to said reference potential,a resistive cell, comprising a seventh n-type MOS transistor (TN3) and an eighth p-type MOS transistor (TP3), the gate of said seventh transistor (TN3) being connected to said power supply voltage, the gate of said eighth transistor (TP3) being connected to the reference potential, the source of said seventh transistor (TN3) and the drain of said eighth transistor (TP3) being connected to each other and to the gates of said fifth and sixth transistors (TP2, TN1) of said first capacitive cell and having a potential equal to said first DC voltage (NBGP), the drain of said seventh transistor (TN3) and the source of said eighth transistor (TP3) being connected to each other and having a potential equal to said second DC voltage (NARF), anda second capacitive cell, comprising a ninth p-type MOS transistor (TP4) and a tenth n-type MOS transistor(TN5), the source and the drain of said ninth transistor (TP4) being connected to the power supply voltage, the source and the drain of said tenth transistor (TN5) being connected to the reference potential, the gates of said ninth and tenth transistors (TP4, TN5) being connected to each other and to the drain of said seventh transistor (TN3) of said resistive cell and constituting an output of said intermediate stage.
- The device according to claims 1, 2 or 3, wherein:the first branch (121) of the output stage (12) comprises an eleventh P-type MOS transistor (TP5) and a twelfth N-type MOS transistor (TN6), the gate of the twelfth transistor (TN6) and the drain of the eleventh transistor (TP5) being connected to the power supply voltage, the source of the eleventh transistor (TP5) being connected to the drain of the twelfth transistor (TN6),the second branch (122) of the output stage (12) comprises a thirteenth P-type MOS transistor (TP7) and a fourteenth N-type MOS transistor (TN8), the gate of the thirteenth transistor (TP7) and the source of the fourteenth transistor (TN8) being connected to the reference potential, the source of the thirteenth transistor (TP7) being connected to the drain of the fourteenth transistor (TN8),the gates of the eleventh and the fourteenth transistors (TP5, TN8) being connected to each other, and to the output of the intermediate stage (11), the source of the twelfth transistor (TN6) being connected to the drain of the thirteenth transistor (TP7) and forming the output of the output stage (12).
- The use of a device according to any of the preceding claims 1 to 4 in an integrated circuit.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9715626A FR2772155B1 (en) | 1997-12-10 | 1997-12-10 | DEVICE FOR GENERATING A CONTINUOUS REFERENCE VOLTAGE |
FR9715626 | 1997-12-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0923014A1 EP0923014A1 (en) | 1999-06-16 |
EP0923014B1 true EP0923014B1 (en) | 2003-07-09 |
Family
ID=9514411
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98403068A Expired - Lifetime EP0923014B1 (en) | 1997-12-10 | 1998-12-07 | Reference DC voltage generating apparatus |
Country Status (4)
Country | Link |
---|---|
US (1) | US5998983A (en) |
EP (1) | EP0923014B1 (en) |
DE (1) | DE69816249T2 (en) |
FR (1) | FR2772155B1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1312498B1 (en) * | 1999-05-13 | 2002-04-17 | St Microelectronics Srl | INTEGRATED STRUCTURE WITH ANALOGUE UNIT SUPPLIED BY VOLTAGE EXTERNAL POWER SUPPLY THROUGH LOW-PASS FILTER AND ELEMENTS OF |
US6522185B2 (en) * | 2001-02-28 | 2003-02-18 | Agilent Technologies, Inc. | Variable delay CMOS circuit with PVT control |
US8924765B2 (en) * | 2011-07-03 | 2014-12-30 | Ambiq Micro, Inc. | Method and apparatus for low jitter distributed clock calibration |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5051686A (en) * | 1990-10-26 | 1991-09-24 | Maxim Integrated Products | Bandgap voltage reference |
US5281906A (en) * | 1991-10-29 | 1994-01-25 | Lattice Semiconductor Corporation | Tunable voltage reference circuit to provide an output voltage with a predetermined temperature coefficient independent of variation in supply voltage |
US5373226A (en) * | 1991-11-15 | 1994-12-13 | Nec Corporation | Constant voltage circuit formed of FETs and reference voltage generating circuit to be used therefor |
US5315231A (en) * | 1992-11-16 | 1994-05-24 | Hughes Aircraft Company | Symmetrical bipolar bias current source with high power supply rejection ratio (PSRR) |
DE69521287T2 (en) * | 1995-03-24 | 2002-05-02 | Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania | Circuit arrangement for generating a reference voltage and detection of a supply voltage drop and associated method |
KR0141157B1 (en) * | 1995-04-24 | 1998-07-15 | 김광호 | The circuit for reference voltage generating |
JP3592423B2 (en) * | 1996-01-26 | 2004-11-24 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
US5796244A (en) * | 1997-07-11 | 1998-08-18 | Vanguard International Semiconductor Corporation | Bandgap reference circuit |
-
1997
- 1997-12-10 FR FR9715626A patent/FR2772155B1/en not_active Expired - Fee Related
-
1998
- 1998-12-07 DE DE69816249T patent/DE69816249T2/en not_active Expired - Lifetime
- 1998-12-07 EP EP98403068A patent/EP0923014B1/en not_active Expired - Lifetime
- 1998-12-09 US US09/207,614 patent/US5998983A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
FR2772155A1 (en) | 1999-06-11 |
DE69816249D1 (en) | 2003-08-14 |
US5998983A (en) | 1999-12-07 |
FR2772155B1 (en) | 2000-02-11 |
EP0923014A1 (en) | 1999-06-16 |
DE69816249T2 (en) | 2004-04-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0733961B1 (en) | Reference current generator in CMOS technology | |
EP0424264B1 (en) | Current source with low temperature coefficient | |
CH628462A5 (en) | Source reference voltage. | |
FR2623307A1 (en) | TWO-TERMINAL CURRENT SOURCE WITH TEMPERATURE COMPENSATION | |
FR2975510A1 (en) | DEVICE FOR GENERATING AN ADJUSTABLE PROHIBITED BAND REFERENCE VOLTAGE WITH HIGH FEED REJECTION RATES | |
FR2975512A1 (en) | METHOD AND DEVICE FOR GENERATING AN ADJUSTABLE REFERENCE VOLTAGE OF BAND PROHIBITED | |
EP0619647B1 (en) | Amplifier architecture and application for a band gap voltage generator | |
FR2694851A1 (en) | Draw circuit to a determined state of an integrated circuit input. | |
CH632610A5 (en) | REFERENCE VOLTAGE SOURCE REALIZED IN THE FORM OF AN INTEGRATED CIRCUIT WITH MOS TRANSISTORS. | |
EP2067090A1 (en) | Voltage reference electronic circuit | |
FR2737319A1 (en) | INTEGRATED CIRCUIT VOLTAGE AND / OR CURRENT REFERENCE GENERATOR | |
FR2590697A1 (en) | LOW DIFFERENTIAL VOLTAGE REPEATER CIRCUIT. | |
EP0923014B1 (en) | Reference DC voltage generating apparatus | |
EP0687967B1 (en) | Temperature stable current source | |
EP0447729B1 (en) | Level detector hardened against noise | |
FR2767207A1 (en) | Generator of constant voltage under varying ambient temperature and with components having varying characteristics, applicable to microprocessor supply monitoring circuits | |
EP0738038B1 (en) | Current amplifier | |
EP1352302A1 (en) | Voltage regulator with static gain in reduced open loop | |
EP3357159A1 (en) | Elementary electronic circuit for stage of amplification or repeat of analog signals | |
EP1931030A1 (en) | Current preamplifier and associated current comparator | |
EP0480815B1 (en) | Integrated amplifier circuit with one input signal connection | |
EP1073201B1 (en) | Low consumption oscillator | |
EP1271440B1 (en) | High-voltage regulator with external control | |
FR2735301A1 (en) | Variable power supply CMOS inverter | |
EP1315062B1 (en) | Current generating circuit for high voltage applications |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE GB IT NL SE |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
17P | Request for examination filed |
Effective date: 19990529 |
|
AKX | Designation fees paid |
Free format text: DE GB IT NL SE |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: ATMEL NANTES SA |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Designated state(s): DE GB IT NL SE |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REF | Corresponds to: |
Ref document number: 69816249 Country of ref document: DE Date of ref document: 20030814 Kind code of ref document: P |
|
REG | Reference to a national code |
Ref country code: SE Ref legal event code: TRGR |
|
GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20031006 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20040414 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: NL Payment date: 20081118 Year of fee payment: 11 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: SE Payment date: 20081119 Year of fee payment: 11 Ref country code: IT Payment date: 20081219 Year of fee payment: 11 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20091209 Year of fee payment: 12 |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: V1 Effective date: 20100701 |
|
EUG | Se: european patent has lapsed | ||
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20100701 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091207 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091208 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20101207 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20101207 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20121231 Year of fee payment: 15 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 69816249 Country of ref document: DE Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUS, DE |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 69816249 Country of ref document: DE Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUS, DE Effective date: 20131023 Ref country code: DE Ref legal event code: R081 Ref document number: 69816249 Country of ref document: DE Owner name: ATMEL CORPORATION, SAN JOSE, US Free format text: FORMER OWNER: ATMEL NANTES S.A., NANTES, FR Effective date: 20131023 Ref country code: DE Ref legal event code: R081 Ref document number: 69816249 Country of ref document: DE Owner name: ATMEL CORPORATION, US Free format text: FORMER OWNER: ATMEL NANTES S.A., NANTES, FR Effective date: 20131023 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 69816249 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 69816249 Country of ref document: DE Effective date: 20140701 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20140701 |