EP1253709A2 - Appareil pour l'amplification de signaux - Google Patents

Appareil pour l'amplification de signaux Download PDF

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Publication number
EP1253709A2
EP1253709A2 EP02252261A EP02252261A EP1253709A2 EP 1253709 A2 EP1253709 A2 EP 1253709A2 EP 02252261 A EP02252261 A EP 02252261A EP 02252261 A EP02252261 A EP 02252261A EP 1253709 A2 EP1253709 A2 EP 1253709A2
Authority
EP
European Patent Office
Prior art keywords
current
signal
output
input
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP02252261A
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German (de)
English (en)
Other versions
EP1253709B1 (fr
EP1253709A3 (fr
Inventor
Seiji Takeuchi
Tatsuya Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
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Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of EP1253709A2 publication Critical patent/EP1253709A2/fr
Publication of EP1253709A3 publication Critical patent/EP1253709A3/fr
Application granted granted Critical
Publication of EP1253709B1 publication Critical patent/EP1253709B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
    • H03F3/345—DC amplifiers in which all stages are DC-coupled with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/375—Circuitry to compensate the offset being present in an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/91—Indexing scheme relating to amplifiers the amplifier has a current mode topology

Definitions

  • the present invention relates to a signal amplification device and, more particularly, relates to an amplification device which can be driven at a low voltage.
  • a conventional amplifier may have a circuit constitution such as shown in Fig. 1.
  • a charge signal obtained by a CCD (Charge Coupled Device) image sensor is converted into a voltage signal through a capacitance in a floating diffusion layer.
  • the voltage signal is amplified by a source follower amplifier on a sensor chip and is then output from the sensor.
  • a reset level of the floating diffusion layer periodically appears in output signals from the sensor.
  • a correlated double sampling (CDS) circuit extracts the portion corresponding to a pixel signal among the output signals.
  • the output signal extracted by the CDS circuit is further amplified by an amplifier using a differential amplifier circuit.
  • such an amplifier includes a differential amplifier circuit 2 using a current mirror as a load.
  • a reference voltage V STD is supplied to the gate of an MOS transistor MN02 as one input terminal.
  • a voltage signal V SIG as a CCD output signal is supplied to the gate of an MOS transistor MN01 as the other input terminal.
  • the differential amplifier circuit 2 generates an output signal according to a difference between the two supplied voltages. Because the differential amplifier circuit 2 uses a current mirror circuit as a load, the circuit 2 functions as a transconductance type amplifier. That is, a voltage signal is supplied as an input signal but a current signal is obtained as an output signal. The generated current signal is converted into a voltage signal V OUT by a resistor R L coupled to an output terminal 4 of the differential amplifier circuit 2.
  • the operating point of the signal V OUT is determined in accordance with a constant current which is supplied from a transistor MN04 (gate bias voltage V B2 ) as a constant-current source to the resistor R L .
  • the potential of the output terminal 4 of the differential amplifier circuit 2 namely, a node between the drain of the transistor MN02 and the drain of a transistor MP02 is equal to that of the voltage signal V OUT .
  • the potential is varied in accordance with the signal V OUT .
  • a plurality of transistors are arranged in series between a power supply voltage V DD and ground potential GND.
  • three MOS transistors of the transistor MP02 of the current mirror circuit, the transistor MN02 of the differential amplifier circuit, and a transistor MN03 (gate bias voltage V B1 ) as a constant-current source are connected in series. To operate, each transistor requires a predetermined potential difference between the source and the drain.
  • the remainder obtained by subtracting the potential difference from the V DD -GND voltage is a voltage fluctuation allowance ⁇ V OUT which is allowable at the output terminal 4.
  • the voltage V DD is set to a relatively large value, for example, +5V. In accordance therewith, the voltage fluctuation allowance ⁇ V OUT is held enough.
  • the CCD output signal processing circuit can be driven at a low voltage, namely, the power supply voltage V DD is reduced.
  • the present invention is made to solve the above problems. It is an object of the present invention to provide a signal amplification device in which low-voltage drive is realized while maintaining the amplitude of an output voltage signal, such that power consumption is reduced.
  • a signal amplification device including a differential amplifier circuit which generates a first output according to an input signal and a current mirror circuit which receives the first output of the differential amplifier circuit to an input-side current path to generate a mirror current through an output-side current path in accordance with a current flowing through the input-side current path, wherein the mirror current is converted into an output voltage by a resistive load in the output-side current path of the current mirror circuit.
  • the first output generated from the differential amplifier circuit is not converted into a voltage signal in principle at an output terminal of the differential amplifier circuit but is normally generated as a current signal, so that any fluctuation in potential at the output terminal is suppressed. Accordingly, the first output generated from the differential amplifier circuit is supplied to the input-side current path of the current mirror circuit.
  • the current mirror circuit generates a mirror current through the output-side current path in accordance with the input-side current flowing through the input-side current path. In other words, the mirror current also fluctuates in accordance with the current fluctuation of the first output from the differential amplifier circuit in the input-side current path.
  • the current signal is transmitted to the output-side current path of the current mirror circuit.
  • a resistor is not disposed in the path through which the current signal flows, in the input-side current path. Rather, a resistor is provided as a load in the output-side current path.
  • a fluctuation in mirror current signal is converted into a voltage fluctuation across the resistor.
  • the voltage fluctuation is extracted as an output voltage signal of the present voltage signal amplification device.
  • a driving voltage for the differential amplifier circuit and the input-side current path can be reduced as much as the suppressed amount of voltage fluctuation at the output terminal of the differential amplifier circuit. Only a single transistor in the output-side current path is required for controlling a mirror current signal in accordance with a signal from the input-side current path.
  • a plurality of transistors may be serially connected between power supply potential and ground potential in the differential amplifier circuit or the input-side current path. That is, the amplitude of the output voltage signal generated in the output-side current path can be large because there are fewer transistors in the output-side current path than in the differential amplifier circuit or the input-side current path. Accordingly, the driving voltage in the output-side current path can be reduced while the amplitude of the output voltage signal is maintained.
  • the signal amplification device may be constituted in such a manner that the current mirror circuit comprises a potential setting circuit for holding the potential on the input side at a predetermined value.
  • the current mirror circuit comprises a pair of transistors whose gates (or bases) are connected to each other in the input-side current path and the output-side current path.
  • a source-drain (emitter-collector) potential difference of the transistor disposed in the input-side current path can be fluctuated in accordance with a current on the input side.
  • a fluctuation in potential difference is smaller than voltage drop in a simple resistor element.
  • potential at a node between the differential amplifier circuit and the input-side current path may fluctuate as explained above.
  • the above-mentioned constitution includes means for holding the potential at the node to a predetermined value. Consequently, the voltage fluctuation at the output terminal of the differential amplifier circuit is fundamentally eliminated, so that the driving voltage for the differential amplifier circuit and the input-side current path can be reduced as much as the eliminated voltage fluctuation.
  • the signal amplification device may be constituted in such a manner that the current mirror circuit includes a constant-current source which supplies a constant current to the input-side current path such that a current signal from the differential amplifier circuit is superimposed on the supplied current from the constant-current source to form an input-side current.
  • the input-side current flowing through an input-side transistor constituting the current mirror circuit is a current obtained by combining the supplied current from the constant-current source with the current signal from the differential amplifier circuit. That is, the input-side current causes a fluctuation in range of the current signal in the vicinity of the supplied current.
  • the supplied current from the constant-current source is changed, the operating point of the output voltage signal generated in the output-side current path can be adjusted.
  • the source-drain (or emitter-collector) potential difference of the input-side transistor constituting the current mirror circuit can be fluctuated in accordance with the current signal from the differential amplifier circuit as mentioned above. The fluctuation allowance can be more suppressed as the input-side current, which is the supplied current, is larger.
  • the current mirror circuit includes, as the only transistor in the output-side current path, a mirror-current generating transistor connected to the input-side current path to generate the mirror current. Consequently, while the amplitude of the output voltage signal is maintained, the output-side current path can be driven at the same voltage as the driving voltage needed for the differential amplifier circuit and the input-side current path.
  • Fig. 2 is a circuit diagram of a CCD output signal processing amplifier according to a first embodiment of the present invention.
  • the amplifier includes a differential amplifier circuit section 10 and a current mirror circuit section 12.
  • the differential amplifier circuit section 10 has such a constitution that a current mirror circuit including MOS transistors MP1 and MP2 is connected as a load to a differential amplifier circuit including an MOS transistor MN1 which receives the CCD output signal V SIG at the gate thereof, an MOS transistor MN2 which receives the reference voltage V STD at the gate thereof, and an MOS transistor MN3 which is connected to both of the sources of the above transistors and which receives the predetermined gate bias voltage V B1 to function as a constant-current source.
  • the power supply voltage V DD and the ground potential GND are connected as power supplies to the differential amplifier circuit section 10.
  • MN as a transistor denotes an N-channel MOS transistor and reference symbol “MP” denotes a P-channel MOS transistor.
  • the transistors MN1 and MN2 are constructed as transistors having the same characteristics, and the transistors MP1 and MP2 are also constructed such that they have the same characteristics.
  • the source-drain current of each of the transistors MN1 and MN2 fluctuates in accordance with the difference ⁇ V IN .
  • the current change ⁇ i of the transistor MN1 is equal to a current change of the transistor MP1.
  • the current change ⁇ i generated in the transistor MP1 causes a current change ⁇ i in the transistor MP2 constituting the current mirror circuit.
  • a current supplied from the transistor MP2 is varied only by (+ ⁇ i) and a current supplied to the transistor MN2 is varied only by (- ⁇ i). Consequently, a current of (+2 ⁇ i) flows from the output terminal 14 to the current mirror circuit section 12.
  • the current of (+2 ⁇ i) is a current signal to be generated from the differential amplifier circuit section 10 to the current mirror circuit section 12.
  • a current path on the input side of the current mirror circuit section 12 includes the serial connection of MOS transistors MP3, MP4, and MN4 connected between the power supply voltage V DD and the ground potential GND.
  • a current path on the output side thereof includes the serial connection of the resistor R L and an MOS transistor MN6 connected between the power source voltage V DD and the ground potential GND.
  • An output terminal 18 of the current mirror circuit section 12 is disposed between the resistor R L and the transistor MN6.
  • the current mirror circuit section 12 has the serial connection of MOS transistors MP5 and MN5 connected between the power supply voltage V DD and the ground potential GND.
  • the transistors MN4 and MN6 realize mirroring of the current between the input-side current path and the output-side current path.
  • the transistor MP3 is arranged between the power supply voltage V DD and the node 16.
  • a predetermined DC bias voltage V B3 is applied to the gate of the transistor MP3.
  • the transistor MP3 functions as a constant-current source for supplying a constant current DCI to the input-side current path.
  • the source of the transistor MP4 is connected to the node 16 and the gate thereof is connected to the drain of the transistor MP5.
  • the gate of the transistor MP5 is connected to the node 16.
  • a feedback circuit for suppressing the potential fluctuation at the node 16 is constituted by the transistors MP4 and MP5.
  • the transistor MN5 functions as a constant-current source for receiving the predetermined gate bias voltage V B2 to supply a predetermined bias current to the transistor MP5.
  • the potential at the node 16 is fundamentally lower than the power supply voltage V DD by an amount equal to the gate-drain voltage of the transistor MP5 according to the predetermined bias current supplied from the transistor MN5.
  • the current signal AC IN supplied at the node 16 flows into the ground potential GND through the transistors MP4 and MN4.
  • the fluctuation of the signal AC IN can lead to fluctuation of the potential at the node 16. This amount of fluctuation is accommodated by the feedback circuit including the transistors MP4 and MP5.
  • the signal AC IN input at the node 16 is combined with the constant current DCI supplied by the transistor MP3 and the resulting current is then supplied to the transistor MN4.
  • the transistor MN6, whose gate is connected to that of the transistor MN4, generates a mirror current I M ( ⁇ ⁇ M I I ) that is proportional to an input-side current I I ( ⁇ DCI+AC IN ) flowing through the transistor MN4.
  • a ratio ⁇ M of the current I I to the current I M is fundamentally determined in accordance with a ratio of the size of the transistor MN4 to that of the transistor MN6.
  • the mirror current I M flows through the resistor R L , so that a current signal included in the current I M is converted into a voltage signal.
  • a voltage signal ⁇ V OUT which is expressed by the following expression, is generated at an output terminal 18.
  • the signal is an output of the present amplifier.
  • a gain G ( ⁇ ⁇ V OUT / ⁇ V IN ) of the present amplifier is obtained by the following equation using the expressions (1) to (3).
  • G ⁇ M ⁇ g m ⁇ R L
  • the differential amplifier circuit section 10 converts an output for the supplied CCD output signal V IN into not a voltage signal but a current signal and then supplies the resultant signal to the current mirror circuit section 12.
  • the current mirror circuit section 12 mirrors the supplied current signal AC IN to the output-side current path. In the resistor R L in the output-side current path, the mirrored current signal according to the current signal AC IN is converted into a voltage signal.
  • the three transistors MP2, MN2, and MN3 are connected in series between the power supply voltage V DD and the ground potential GND.
  • Each of the transistors requires a specific source-drain voltage V DS to operate.
  • a current signal is converted into a voltage signal in a resistor connected to the output terminal of a differential amplifier circuit section. Accordingly, in a conventional amplifier a voltage fluctuation is generated at the output terminal of the differential amplifier circuit section with the consequence that the power supply voltage V DD must have such magnitude that the source-drain voltages V DS of the three transistors and the voltage fluctuation at the output terminal can be held.
  • the conversion of a current signal into a voltage signal is not performed at the output terminal of the differential amplifier circuit section 10. That is, because a potential fluctuation at the output terminal is suppressed, the power supply voltage V DD capable of holding the voltages V DS of the three transistors is fundamentally enough. Therefore, the driving power supply voltage V DD for the differential amplifier circuit section 10 can be reduced compared with that of the conventional amplifier.
  • the input-side current path of the current mirror circuit section 12 includes the serial connection of the three transistors.
  • the node 16 has the same potential as that at the output terminal 14. Accordingly, no fluctuation in potential is generated. Consequently, the input-side current path can also be operated at the power supply voltage V DD , which is voltage lower than that of the conventional amplifier as in the case of the differential amplifier circuit section 10.
  • V DD power supply voltage
  • the path including the two transistors MP5 and MN5 can be driven.
  • the voltage signal ⁇ V OUT corresponding to the voltages V DS of two transistors is allowable. That is, the entire current mirror circuit section 12 can be driven at the low voltage V DD similarly used for the differential amplifier circuit section 10.
  • the entire amplifier can be driven at the voltage V DD and because this voltage is lower than the driving power supply voltage required for operating the conventional differential amplifier circuit section, power consumption of the amplifier is reduced.
  • Fig. 3 is a circuit diagram of a CCD output signal processing amplifier according to a second embodiment of the present invention. To simplify the following description, the same reference numerals and symbols are used as in the first embodiment where they designate the same components.
  • the example amplifier according to the present embodiment is constituted in such a manner that an output level compensator circuit section for adjusting an operating point of the output voltage signal V OUT , namely, a direct-current offset level (DC level) is added to the amplifier according to the first embodiment.
  • the output level compensator circuit section includes an operational amplifier OPA and a current mirror circuit section 32.
  • the current mirror circuit section 32 is constituted so as to be identical with the current mirror circuit section 12. Accordingly, each component of the current mirror circuit section 32 is designated by adding a comma (') to the reference numeral of the corresponding component of the current mirror circuit section 12.
  • the current mirror circuit section 32 is different from the current mirror circuit section 12 with respect to signals to be input and output.
  • a circuit corresponding to the differential amplifier circuit section 10 is not connected to the current mirror circuit section 32.
  • One terminal of a resistor R L ' of the current mirror circuit section 32 corresponds to the output terminal of the current mirror circuit section 12. This terminal is referred to as a dummy output terminal 34.
  • the dummy output terminal 34 is connected to one input terminal of the operational amplifier OPA.
  • a DC level V DC of the target voltage signal V OUT is supplied to the other input terminal of the operational amplifier OPA.
  • the operational amplifier OPA comprises an inverting amplifier performs control to feed back a gate voltage of a transistor MP3' so that the potential at the dummy output terminal 34 is equal to the output level V DC .
  • An output terminal of the operational amplifier OPA is also connected to the gate of the transistor MP3 of the current mirror circuit section 12.
  • the gate voltage of the transistor MP3' is controlled so that the potential at the dummy output terminal 34 is equal to the level V DC
  • the potential at the output terminal 18 of the current mirror circuit section 12 with the same constitution as that of the current mirror circuit section 32 is also set to the level V DC .
  • the DC level V DC of the output voltage signal can be also adjusted by changing a gate voltage V G of the transistor MP3.
  • V G of the transistor MP3 a gate voltage of the transistor MP3.
  • the DC level at the output terminal 18 is automatically adjusted to the target level V DC .
  • the driving voltage can be reduced, so that the power consumption can be reduced.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
EP02252261A 2001-03-29 2002-03-27 Appareil pour l'amplification de signaux Expired - Lifetime EP1253709B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001095895 2001-03-29
JP2001095895A JP4141111B2 (ja) 2001-03-29 2001-03-29 信号増幅装置

Publications (3)

Publication Number Publication Date
EP1253709A2 true EP1253709A2 (fr) 2002-10-30
EP1253709A3 EP1253709A3 (fr) 2004-05-26
EP1253709B1 EP1253709B1 (fr) 2007-11-14

Family

ID=18949885

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02252261A Expired - Lifetime EP1253709B1 (fr) 2001-03-29 2002-03-27 Appareil pour l'amplification de signaux

Country Status (6)

Country Link
US (1) US6642792B2 (fr)
EP (1) EP1253709B1 (fr)
JP (1) JP4141111B2 (fr)
KR (1) KR100440189B1 (fr)
DE (1) DE60223441D1 (fr)
TW (1) TW519791B (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1357663B1 (fr) * 2002-02-25 2011-06-29 NEC Corporation Amplificateur différentiel, circuit d'attaque, et dispositif d'affichage
JP4055683B2 (ja) * 2003-09-03 2008-03-05 ソニー株式会社 固体撮像素子
US8340614B2 (en) * 2008-12-18 2012-12-25 Plantronics, Inc. Antenna diversity to improve proximity detection using RSSI
US8390491B2 (en) * 2011-01-14 2013-03-05 Analog Devices, Inc. Buffer to drive reference voltage
US10734958B2 (en) 2016-08-09 2020-08-04 Mediatek Inc. Low-voltage high-speed receiver

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3914684A (en) * 1973-10-05 1975-10-21 Rca Corp Current proportioning circuit
EP0797296A2 (fr) * 1996-03-19 1997-09-24 Motorola, Inc. Etage d'entrée et procédé correspondant pour un amplificateur opérationnel à faible tension d'alimentation
US5966005A (en) * 1997-12-18 1999-10-12 Asahi Corporation Low voltage self cascode current mirror
US5994962A (en) * 1996-08-29 1999-11-30 Mitsumi Electric Co., Ltd. Differential amplifier device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3152818A (en) * 1961-05-08 1964-10-13 Bastian Blessing Co Bracket hold-down device
JPS5277563A (en) * 1975-12-24 1977-06-30 Hitachi Ltd Differential amplification circuit
JP2525346B2 (ja) * 1983-10-27 1996-08-21 富士通株式会社 定電流源回路を有する差動増幅回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3914684A (en) * 1973-10-05 1975-10-21 Rca Corp Current proportioning circuit
EP0797296A2 (fr) * 1996-03-19 1997-09-24 Motorola, Inc. Etage d'entrée et procédé correspondant pour un amplificateur opérationnel à faible tension d'alimentation
US5994962A (en) * 1996-08-29 1999-11-30 Mitsumi Electric Co., Ltd. Differential amplifier device
US5966005A (en) * 1997-12-18 1999-10-12 Asahi Corporation Low voltage self cascode current mirror

Also Published As

Publication number Publication date
EP1253709B1 (fr) 2007-11-14
EP1253709A3 (fr) 2004-05-26
US20020140508A1 (en) 2002-10-03
JP2002299969A (ja) 2002-10-11
DE60223441D1 (de) 2007-12-27
TW519791B (en) 2003-02-01
JP4141111B2 (ja) 2008-08-27
US6642792B2 (en) 2003-11-04
KR100440189B1 (ko) 2004-07-14
KR20020077242A (ko) 2002-10-11

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