Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
  • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
  • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
  • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
  • H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Definitions

• the present ir. . ention relates to phase locked loops (PLLs).
• a known PLL is shown in Figure 1.
• a reference frequency f m is applied to a phase or phase/frequency detector, to which is also applied a feedback signal derived from an output frequency signal f out of the PLL.
• the detector produces an error signal, which is filtered by a loop filter.
• An output signal of the loop filter is applied to a voltage-controlled oscillator (VCO). which produces the output frequency signal f out .
• VCO voltage-controlled oscillator
• a programmable divide-by-N counter divides down the output frequency signal f out to produce a lower frequency signal that is then applied to the detector. In this manner, an output frequency signal can be generated that is some multiple of the reference frequency.
• Such divide-by-N counters are typically realized in CMOS.
• CMOS complementary metal-oxide-semiconductor
• FIG. 3 One construction of such a circuit is shown in Figure 3, in which the dual- modulus counter is followed by a pair of lower-speed (e.g.. CMOS) programmable counters.
• CMOS lower-speed programmable counters.
• the reference and output frequencies are related as follows:
• Q is the quotient of the integer division N'P and R is the remainder of the integer division N/P.
• the value Q is used to preset a "tens " counter (so-called because its effect is multiplied by the modulus P) and R is used to preset a "ones " counter (the effect of which is not multiplied by the modulus).
• Trie value Q must be greater than or equal to the value R. With this restriction, the minimum division ratio achievable to guarantee continuous coverage of the possible integer divisors N using such a circuit is. in general, P(P - 1).
• the modulus control signal for controlling the dual-modulus prescaler can generate considerable noise within the frequency band of the reference signal, since the period of this modulus control signal is equal to the period of the PLL reference signal. As illustrated in Figure 3. this noise may be coupled by parasitic capacitance to the VCO input, causing frequency jitter. In addition, the same noise is input to the dual-modulus prescaler where it may cause variations in the input impedance of the prescaler. resulting in frequency pulling by the VCO. To alleviate frequency pulling, the output signal of the VCO to the dual-modulus prescaler may be buffered, as illustrated in dotted lines in Figure 3. Such buffering adds to the size and complexity of the PLL. Various filtering strategies have been used to attack this noise problem. An effective, low-cost solution to this problem remains a long-standing need.
• the present invention achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli.
• ones " and "tens” are not all counted consecutively. Instead, ones and tens are interleaved.
• the R count is doubled and the output of the R counter is toggled between high and low states. (The Q counter may remain unmodified.)
• ones and tens are interleaved in accordance with a ratio q:r.
• Figure 1 is a block diagram of a conventional PLL using a divide-by-N counter
• Figure 2 is a block diagram of a conventional PLL using a dual-modulus prescaler:
• Figure 3 is a more detailed block diagram of one realization of the circuit of Figure 2:
• Figure 4 is a timing diagram illustrating operation of the PLL of Figure 2:
• FIG. 5 is a diagram illustrating the principle of the invention in accordance with one embodiment thereof:
• FIG. 6 is a block diagram of a PLL in accordance with one aspect of the present invention:
• Figure 7 is a timing diagram illustrating operation of the PLL of Figure 6;
• Figure 8 is a waveform display showing noise levels using a conventional PLL circuit:
• Figure 9 is a waveform display showing noise levels using the present PLL circuit.
• modulus interleaving technique of the present invention may be applied in various forms with varying degrees of sophistication and complexity.
• a simple but effective implementation of modulus interleaving is illustrated in Figure 5.
• the Q count and the Q counter are left unchanged.
• the R count is doubled, and the R counter is toggled. For example, if the R count would normally be 15 with the counter output being held low for 15 counts, instead the count is doubled to 30.
• the counter output instead of being held low continuously, is toggled, i.e. low for 1 count, high for 1 count, low for 1 count, etc.
• the overall effect is the same as in the conventional case-referring again to the foregoing equations, the effect is to replace R with 2R 2.
• the difference is that the energy spectrum of the modulus control signal is shifted above and away from the PLL reference frequency. If desired, the same measure may be taken with respect to Q.
• FIG. 6 a block diagram is shown of a PLL circuit in accordance with another embodiment of the present invention.
• the R counter and the Q counter are modified by the addition of an r counter and an q counter, respectiveh .
• the resulting R counter counts R total counts, r at a time.
• the resulting Q counter counts Q total counts, q at a time.
• the apparatus operates in the following manner.
• the dual-modulus prescaler is set to divide by P - 1 at the start of the cycle.
• the output from the dual-modulus prescaler clocks both counters.
• the R counter ceases counting and sets the dual-modulus prescaler to divide by P. Only the Q counter is then clocked.
• the q counter reaches zero, the initial values r and q are again loaded into the counters and the next subcycle begins.
• the R counter counts down to zero, after which the Q counter counts down to zero.
• Figure 8 is a plot of the energy within the signal present on the modulus control line in accordance with the traditional modulus control setup of Figures 3 and 4. Excluding zero hertz, the noise margin at the first noise peak is about -5dbm.
• Figure 9 is a plot of the energy within the signal present on the modulus control line in accordance with the present modulus control setup of Figures 6 and 7. Excluding zero hertz, the noise margin at the first noise peak is about -25dbm.
• this example demonstrates a reduction in the noise from the modulus control signal at the reference frequency of 20dB. greatly alleviating the noise problems expe ⁇ enced in the prior art.

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• 2000
  • 2000-07-31 KR KR1020027001156A patent/KR20020019582A/ko not_active Application Discontinuation
  • 2000-07-31 JP JP2001513812A patent/JP2003506909A/ja active Pending
  • 2000-07-31 CN CNB008120595A patent/CN1207845C/zh not_active Expired - Fee Related
  • 2000-07-31 WO PCT/US2000/020749 patent/WO2001010028A1/en not_active Application Discontinuation
  • 2000-07-31 EP EP00952306A patent/EP1201034A1/de not_active Withdrawn
  • 2000-07-31 AU AU65030/00A patent/AU6503000A/en not_active Abandoned
  • 2000-07-31 CN CNA2005100669825A patent/CN1667955A/zh active Pending

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