EP1193672A2 - Dispositif d'affichage et méthode de visualisation d'image - Google Patents

Dispositif d'affichage et méthode de visualisation d'image Download PDF

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Publication number
EP1193672A2
EP1193672A2 EP01306864A EP01306864A EP1193672A2 EP 1193672 A2 EP1193672 A2 EP 1193672A2 EP 01306864 A EP01306864 A EP 01306864A EP 01306864 A EP01306864 A EP 01306864A EP 1193672 A2 EP1193672 A2 EP 1193672A2
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EP
European Patent Office
Prior art keywords
subfield
display
circuit
bit
resolution information
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EP01306864A
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German (de)
English (en)
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EP1193672A3 (fr
EP1193672B1 (fr
Inventor
Kazutaka Hitachi Ltd. Int. Prop. Office Naka
Masanori Fujitsu Hitachi Plas. Dis. Ltd Takeuchi
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Hitachi Ltd
Hitachi Plasma Display Ltd
Original Assignee
Fujitsu Hitachi Plasma Display Ltd
Hitachi Ltd
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Priority claimed from JP2000273545A external-priority patent/JP2002082647A/ja
Priority claimed from JP2000380289A external-priority patent/JP4633920B2/ja
Application filed by Fujitsu Hitachi Plasma Display Ltd, Hitachi Ltd filed Critical Fujitsu Hitachi Plasma Display Ltd
Publication of EP1193672A2 publication Critical patent/EP1193672A2/fr
Publication of EP1193672A3 publication Critical patent/EP1193672A3/fr
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Publication of EP1193672B1 publication Critical patent/EP1193672B1/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2059—Display of intermediate tones using error diffusion
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G09G3/2029—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames having non-binary weights
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G09G3/2037—Display of intermediate tones by time modulation using two or more time intervals using sub-frames with specific control of sub-frames corresponding to the least significant bits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/2803—Display of gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
    • G09G3/2932—Addressed by writing selected cells that are in an OFF state
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0266—Reduction of sub-frame artefacts

Definitions

  • the present invention relates to a display and an image displaying method, particularly relates to a display and an image displaying method wherein gradation representation is made in a subfield mode and data every line is sequentially output and displayed in each subfield.
  • a cathode ray tube (CRT) display which has been used heretofore
  • a flat panel display using liquid crystal and plasma which is thin and light, which has little distortion of the screen and is hardly influenced by earth magnetism is used.
  • a plasma display which has a large angle of visibility because of a spontaneous emission type and the large-sized panel of which can be manufactured relatively easily attracts attention as a display of a picture signal.
  • a method called a subfield mode is used to display a halftone.
  • the gradation of the luminance of one field is represented by dividing the time length of one field into plural subfields, allocating the proper weight of emission to each subfield and controlling the emission and non-radiation of each subfield.
  • one subfield includes a control pulse for respectively controlling a reset period for initializing a state of a discharge cell, an address control period for controlling the lighting and unlighting of the discharge cell and a sustention period for determining the amount of emission.
  • control pulses are not to be shorter than predetermined time length to realize the stable control of emission.
  • pseudo contour interference which deteriorates the quality of a dynamic image.
  • a method of increasing the number of subfields and controlling the distribution of emission and the centroid of emission respectively in one field is used. As the more the number of subfields is, the more controllable emission patterns are in case the number of representable gradations is the same, the effect of reducing pseudo contour interference increases. Therefore, there is a problem that incase enough subfields are not acquired, the quality of a dynamic image when it is displayed is remarkably deteriorated by this pseudo contour interference.
  • a conventional type display it is basically regarded as important that an input signal is faithfully displayed and a method of acquiring high quality in consideration of the characteristic of a human visual sense such as dither for compensating the shortage of gradations, error diffusion processing and the control of average luminance is also partly used, however, the control of the amplitude of a signal is main.
  • Each line of a picture signal is data sampled in a vertical direction of one screen and when sampled data is thinned out by interlaced scanning, vertical resolution is required to be reduced by half beforehand to reduce folding interference. Hereby, vertical resolution is reduced by half and an image is displayed in low resolution.
  • the object of the invention is to provide a display and an image displaying method wherein the amount of the information of the resolution of an displayed image is limited if necessary positively utilizing the characteristic of a human visual sense and the statistical property of a picture signal and the synthetic image quality is enhanced.
  • Another object of the invention is to provide a high-resolution display and an image displaying method wherein subfields of the enough number are secured by improving total address control periods which account for the time of a field and gradation representation, a measure against pseudo contour interference and further, the realization of high-luminance display are implemented.
  • the invention adopts the following methods to solve the above-mentioned problems.
  • Address control periods are reduced by simultaneously performing addressing for two lines based upon the same data in a predetermined subfield and the time is allocated to the improvement of image quality in luminance, gradation and a pseudo contour.
  • Display resolution information in units of subfield is limited by dividing an input picture signal into vertical frequency components and selectively synthesizing them again.
  • the average value for two lines of a display signal is possibly equalized to the average value for two lines of an input signal.
  • Fig. 1 is a schematic drawing showing the layout of discharge cells and electrodes of an AC3 electrode-type plasma display.
  • reference numbers 5101, 5102, 5103 and 5104 denote an X sustaining electrode
  • 5201, 5202, 5203 and 5204 denote a Y sustaining electrode
  • 5300 and 5301 denote an address electrode.
  • Each address electrode 5300, 5301 is formed on a rear plate
  • the X sustaining electrodes 5101 to 5104 and the Y sustaining electrodes 5201 to 5204 are formed on a front plate
  • a picture element is formed in the intersection of a pair of the X sustaining electrode and the Y sustaining electrode and the address electrode.
  • Picture elements 5410, 5411, 5620, 5421, 5430, 5431, 5440 and 5441 are formed by discharge between these electrodes on a panel as shown in Fig. 1.
  • Fig. 2 shows the waveforms of voltage applied to the Y sustaining electrode and the address electrode in the address control period.
  • a scan pulse is applied in the order of the Y1 sustaining electrode 5201, the Y2 sustaining electrode 5202, the Y3 sustaining electrode 5203 and the Y4 sustaining electrode 5204 and an address pulse for controlling lighting and unlighting every line is applied to the A0 address electrode 5300 and the A1 address electrode 5301.
  • a scan pulse is applied to the Y1 sustaining electrode 5201 at time 11, the lighting and unlighting of the picture elements 5410 and 5411 on a first line are controlled.
  • address voltage is applied to both the A0 address electrode 5300 and the A1 address electrode 5301, address discharge is caused between the A0 address electrode 5300 and the Y1 sustaining electrode 5201 and between the A1 address electrode 5301 and the Y1 sustaining electrode 5201 and a wall charge is generated so that emission is implemented in the succeeding sustention period.
  • addressing in which the lighting and unlighting of the picture elements 5420 and 5421 on a second line, the picture elements 5430 and 5431 on a third line and the picture elements 5440 and 5441 on a fourth line is controlled is respectively performed at time T2, T3 and T4.
  • a wall charge in a cell is generated by such addressing every line if necessary and emission is controlled in the succeeding sustention period.
  • Fig. 3 is a schematic drawing showing field configuration in case one field is constituted of five subfields.
  • a reference number 10 denotes a rest period for initializing a state of a discharge cell in each subfield
  • 20 denotes an address control period for controlling the lighting and unlighting of each picture element in each subfield
  • 31, 32, 33, 34 and 35 denote a sustention period in which the amount of emission in respective subfields is determined.
  • emission according to the number of sustaining pulses is made in a discharge cell in which a wall charge is generated in the address control period 20 so that emission is possible.
  • the weight of emission corresponding to each subfield is allocated to each subfield SF1 to SF5.
  • the number of sustaining pulses in the sustention periods 31, 32, 33, 34 and 35 of each subfield SF1 to SF5 is approximately 16:8:4:2:1.
  • the displayable maximum luminance (the gradation 31) is determined by the total of sustaining pulses in the sustention periods 31, 32, 33, 34 and 35 of the subfields SF1 to SF5, the luminance cannot be secured enough and satisfactory image quality cannot be acquired when time which does not contribute to emission such as the address control period 20 in one field is long.
  • the address control period 20 requires time proportional to the number of displayed lines and one address control period is required for one field. Therefore, in case a high-resolution display panel is to be realized, there is a problem that subfields of the enough number cannot be secured, the number of display gradations is short and the luminance and image quality are deteriorated.
  • Fig. 4 is a schematic drawing showing an embodiment of field configuration according to the invention that one field is constituted of plural subfields and shows field configuration that the address control periods in SF2, SF4 and SF5 having relatively small weight of emission of the subfields SF1 to SF5 are set to half length, compared with the conventional type field configuration shown in Fig. 3.
  • the address control periods in SF1 and SF3 are the same as the conventional type address control periods shown in Fig. 3.
  • reference numbers 21a to 21c denote address control periods which in the subfields SF2, SF4 and SF5 are set to half length, compared with those shown in Fig. 3.
  • the configuration of the other is equal to that of the same reference number shown in Fig. 3.
  • a discharge cell is initialized in the reset period 10, and lighted picture elements and unlighted picture elements are selected every line in the address control period 20.
  • the picture elements selected in the address control periods 20 are emitted according to respective weight of emission.
  • the address control periods 21 respectively following the reset periods 10 in the subfields SF2, SF4 and SF5 are reduced by the thinning out of data as a result of simultaneously performing addressing for adjacent two lines and address control processing is executed by half time per line.
  • Fig. 6 is a waveform illustration showing one embodiment of voltage applied to the Y sustaining electrode and the address electrode in the address control period of the display according to the invention.
  • addressing is simultaneously performed for two lines based upon the same data by simultaneously applying a scan pulse to the Y1 sustaining electrode 5201 and the Y2 sustaining electrode 5202.
  • the Y3 sustaining electrode 5203 and the Y4 sustaining electrode 5204 are simultaneously processed.
  • Time required for scanning total lines on one screen can be reduced up to a half by simultaneously applying a scan pulse to two lines and performing addressing as described above.
  • addressing is simultaneously performed for two lines, however, the invention is not limited to two lines, three lines or four lines may be also simultaneously processed and at this time, required address time can be reduced up to 1/3 or 1/4.
  • the invention is characterized in that subfields are divided into a group of high order subfields including the most significant subfield and a group of low order subfields except them, for the group of high order subfields, addressing is performed every line as in the prior art and for the group of low order subfields to which relatively small weight of emission is allocated, an address processing period is reduced up to a half. Further, for one subfield in the group of the low order subfields, as an independent control subfield, addressing is performed every line as in the prior art.
  • the group of the high order subfields includes SF1
  • the group of low order subfields includes SF2, SF3, SF4 and SF5
  • the independent control subfield is SF3.
  • the group of high order subfields means high order subfields including the most significant subfield
  • SF1 and SF2 may be also included in the group of high order subfields and in this case, the group of low order subfields includes SF3, SF4 and SF5.
  • Any subfield in the group of low order subfields except the subfield to which the largest weight of emission is allocated is set to the independent control subfield.
  • SF4 or SF5 can be set to the independent control subfield.
  • subfields up to this independent control subfield can be regarded as high order subfields and this case is similar to a case that there is no independent control subfield in the low order subfields.
  • the configuration that three or four lines are simultaneously processed and the address processing period is reduced up to 1/3 to 1/4 may be also adopted except the configuration that the address processing period is reduced to a half by simultaneously processing two lines.
  • the vertical resolution information of low order subfields to which small weight of emission is allocated is lost by simultaneously processing plural lines in the low order subfields as described above, however, a flat part of an image can be smoothly displayed substantially without a problem.
  • a signal of an edge is reproduced in the high order subfields to which large weight of emission is allocated, the deterioration of image quality is hardly caused and high-luminance image display is implemented.
  • an address control period which does not directly contribute to emission in one field is reduced by simultaneously controlling addresses on plural lines in a specific subfield, a period equivalent to the quantity is allocated to the sustention periods 31, 32, 33, 34 and 35 and the luminance of the screen can be enhanced.
  • a new subfield can be also added utilizing excess time produced by the reduced address period so as to enhance image quality.
  • Fig. 5 is a schematic drawing showing another embodiment of the field configuration according to the invention that one field is constituted of plural subfields and shows configuration that a subfield SF6 is increased keeping the maximum luminance (sum of sustention periods of each SF) similar, compared with the conventional type field configuration shown in Fig. 3.
  • reference numbers 21d and 21f denote an address control period set to a half, compared with the address control periods of the subfields SF3, SF5 and SF6 shown in Fig. 3 and 36 denotes a sustention period of the added subfield SF6.
  • the other configuration corresponds to the configuration of the same reference number shown in Fig. 3.
  • a discharge cell is initialized in a reset period 10, and lighted picture elements and unlighted picture elements are selected every line in the address control period 20 as in the case shown in Fig. 3.
  • the picture elements selected in the address control period are emitted according to respective weight of emission.
  • addressing is performed in half time by simultaneously performing addressing for two lines and the control of lighting and unlighting is made by equal data by two lines.
  • emission is made on the line selected in the addressing. That is, a group of high order subfields includes SF1 and SF2, a group of low order subfields includes SF3, SF4, SF5 and SF6 and an independent control subfield is SF4.
  • one field period can include the six subfields SF1 to SF6 by reducing each address control period 21 of the subfields SF3, SF5 and SF6 up to a half. Sixty-four gradations can be displayed by setting the emission ratio of these sustention periods 31, 32, 33, 34, 35 and 36 to 32:16:8:4:2:1.
  • the address control periods of the subfields SF3, SF5 and SF6 can be processed in half time though the address period and the reset period of the subfield SF6 are newly increased, the total of all sustention periods in one field period can be substantially equal to that in the conventional type configuration shown in Fig. 3.
  • the number of displayed gradations can be increased in a state in which luminance substantially equal to that in the conventional type method is kept and the high-quality display can be realized.
  • SF1 to SF3 have only to be set to a group of high order subfields
  • SF4 to SF8 have only to be set to a group of low order subfields
  • SF5 has only to be set to an independent control subfield in eight subfields which can be represented at 256 gradations for example SF1 to SF8 having the emission ration of 128:64:32:16:8:4:2:1.
  • a display mode the luminance of which is low though the mode has high resolution in which no reduction is made in the address control period if necessary and a display mode the luminance of which is high though the mode has low resolution in which the address control periods of more subfields are reduced may be also switched if necessary.
  • the display is used for a monitor of a computer, high-resolution display in which no address control period is reduced is made, when a picture signal is displayed, the same data is displayed for two lines in the two subfields SF5 and SF6 out of the eight subfields SF1 to SF8 and the two modes may be also switched to enable high-luminance display.
  • a range of the adjustment of the luminance may be also expanded by increasing subfields by the mode in which address control periods of two subfields are reduced and the reduction of address control periods of three subfields or the reduction of address control periods of four or five subfields according to the luminance of the periphery of the display, user setting and a level of a picture signal.
  • a part on the left side denotes high order subfields corresponding to most significant bits (MSB)
  • a part on the right side denotes low order subfields corresponding to least significant bits (LSB)
  • LSB least significant bits
  • a subfield in which address time is reduced by two-line simultaneous address is shown by '1'
  • a subfield in which display is made depending upon an address in normal units of line is shown by '0'. That is, in case the subfields are shown in the order of SF1, SF2, SF3, ---, SF8 from the left, address time is reduced in SF3, SF5, SF6, SF7 and SF8 if the number of subfields to which address compression is applied is 5.
  • the number of subfields to which address compression is applied is 4 [0, 0, 0, 1, 0, 1, 1, 1]
  • high order three subfields SF1 to SF3 have only to be set to a group of high order subfields
  • low order five subfields SF4 to SF8 have only to be set to a group of low order subfields
  • a fourth subfield SF5 from the least significant bit has only to be set to an independent control subfield.
  • high order one subfield SF1 has only to be set to a group of high order subfields
  • low order seven subfields SF2 to SF8 have only to be set to a group of low order subfields
  • a fifth subfield SF4 from the least significant bit has only to be set to an independent control subfield.
  • the deterioration of image quality can be greatly reduced by representing a difference component of small amplitude using an independent subfield.
  • this independent subfield has the effect of reducing a display error even if the independent subfield is a subfield having small weight of emission, however, even if original minute difference in a level can be represented without an error, the visual effect of improvement is low. Therefore, a striking error of small amplitude can be reduced by independently controlling a subfield equivalent to a fourth or fifth bit from the least significant bit and satisfactory image quality display is implemented.
  • the position of the added independent subfield may be also varied according to the number of reduced subfields.
  • a subfield which is not reduced in any setting and which can be controlled in units of line can be suitably arranged by this and display of high image quality is implemented.
  • Fig. 7 is a block diagram showing an embodiment of the display according to the invention.
  • reference numbers 101, 102 and 103 denote A/D converters that respectively convert any analog picture signal of R, G, B to a digital signal
  • 2 denotes a subfield converting circuit that converts a binary digital signal converted from analog to digital to subfield data showing the lighting and unlighting of a subfield
  • 20 denotes a control bit smoothing circuit which is provided inside the subfield converting circuit 2 and which executes the smoothing processing of a control bit corresponding to a subfield the address control period of which is reduced by two-line simultaneous addressing
  • 3 denotes a subfield sequent conversion circuit that converts subfield data generated in units of picture element to a plane-sequent form in units of subfield
  • 301 denotes a frame memory provided to the subfield sequent conversion circuit 3 for realizing plane sequence in units of bit
  • 4 denotes a driving circuit that adds a pulse required for driving to a signal converted to a format of plane sequence in units of subfield and converts it to voltage (or current) for driving
  • Each input signal of R, G, B is converted to a digital signal by the A/D converters 101, 102 and 103.
  • This digital signal complies with general binary notation and each bit has the weight of power of 2.
  • the least significant bit b0 has the weight of 1
  • b1 has the weight of 2
  • b2 has the weight of 4
  • b3 has the weight of 8
  • b7 has the weight of 128.
  • the digital signal is converted to subfield data showing the lighting and unlighting of a subfield in the subfield converting circuit 2.
  • This subfield data is constituted of information having the number of bits corresponding to the number of subfields for display and when display is made by eight subfields, a signal is constituted of eight bits of S0, S1, ---, S7. Further, a bit S0 shows whether the picture element emits in an emission period of the leading subfield SF1 or not and similarly, S1 and S2 correspond to the lighting and unlighting of the subfields SF2 and SF3.
  • a control bit smoothing circuit 200 the smoothing processing of a control bit corresponding to a subfield an address control period of which is compressed is executed. This is processing for converting so that the corresponding control bit is the same data as subfield data on the upside by one line or subfield data under on the downside by one line to be a pair for two-line simultaneous addressing using the same control bit.
  • the subfield control bit smoothing processing will be described later.
  • the subfield data is input to the subfield sequent conversion circuit 3 and is written to the frame memory 301 provided inside the subfield sequent conversion circuit 3 in units of picture element.
  • Reading from the frame memory 301 is performed according to plane sequence in units of subfield. That is, after the bit S0 showing whether emission occurs in the subfield SF1 or not is read for one field, the bit S1 showing whether emission occurs in the subfield SF2 or not is read, hereinafter, bits are read in the order of S2, S3, ---, S7 and each subfield is constituted by outputting them as address data.
  • the address control period of which is compressed one of two lines is thinned out and the data of a half of lines is read as address data.
  • the conversion of a signal required for driving the display and the insertion of a pulse are performed in the driving circuit 4 and a matrix display panel 5 is driven.
  • a scan pulse output together with address data of the address control period is output at timing shown in Fig. 2 in a subfield in which addressing is performed in units of normal line and is output at timing shown in Fig. 6 in a subfield in which addressing is simultaneously performed for two lines and the control period is compressed.
  • Fig. 6 shows the waveforms of voltage applied to the Y sustaining electrode and the address electrode in the address control period.
  • the address control period of a predetermined subfield can be reduced by configuring as described above and the display of high image quality can be realized by allocating surplus time produced by the reduction of the address control period to the sustention period so as to enhance the luminance, increasing the number of displayed gradations by increasing the number of subfields and enhancing resistance to pseudo contour interference.
  • All data is written to the frame data 301 and when the address control period is compressed in reading, one of two lines is thinned out, however, one of two lines may be also thinned out in writing.
  • memory capacity can be reduced and even if the memory has the same capacity, high-resolution or multiple-gradation display is implemented.
  • conversion from an input picture signal level to a subfield emission pattern is made in the subfield converting circuit 2. For example, in case an 8-bit input picture signal is displayed in ten subfields, conversion from the 8-bit input signal to 10-bit subfield data is made in a combinational logic circuit or using a lookup table.
  • Fig. 8 is a block diagram showing an embodiment of the control bit smoothing circuit shown in Fig. 7.
  • a reference number 201 denotes a line memory for delaying subfield data by one line
  • 202 denotes a processing circuit that converts so that bit data specified by a control signal CB is equal to two inputs P1 and P2 and outputs Q1 and Q2
  • 203 denotes a line memory for delaying the output Q1 of the processing circuit 202 by one line
  • 204 denotes a switching circuit that switches two inputs a and b in units of line and outputs it.
  • Subfield data S in which the lighting and unlighting of each subfield are related to bit data is input to the line memory 201 and the input terminal P1 of the processing circuit 202. Conversion is made based upon the subfield data delayed by one line in the line memory 201 is input to the input terminal P2 of the processing circuit 202. In the processing circuit 202, conversion is made based upon the subfield data from the input terminal P1 and the subfield data delayed by one line from the input terminal P2 so that predetermined bit data is equal to the subfield data of upper and lower adjacent two picture elements on the current line and a line on the upside by one line. The subfield data to which such conversion is applied are output from the processing circuit 202 as outputs Q1 and Q2.
  • the outputs Q1 and Q2 of the processing circuit 202 are the subfield data of picture elements vertically adjacent on the screen, they can be converted to subfield data D in which predetermined bit data has the same value on two lines by delaying the output Q1 by one line in the line memory 203, switching the switching circuit 204 every line and sequencing signals of two lines.
  • the position of a bit processed in the processing circuit 202 to be equal bit data is determined according to the control signal CB and it can be set the address control period of which subfield is reduced. Setting in case no reduction of the address control period is performed is also made according to the control signal CB and at this time, the processing circuit 202 outputs input P1 as output Q1 as it is and outputs input P2 as output Q2 as it is.
  • the subfield data S in which the lighting and unlighting of each subfield are related to bit data is input to the line memory 201 and the input terminal P1 of the processing circuit 202, however, a signal S of a natural binary number is input from the A/D converter, is processed so that bit data equivalent to a desired subfield is equal on adjacent two lines and the output D of the control bit smoothing circuit 200 may be also converted to a subfield emission control signal showing the lighting and unlighting of each subfield.
  • predetermined bit data of input P1 is output as bit data at the same position of input P2 as it is.
  • both bit data can be equal.
  • predetermined bit data of input P2 may be also output as bit data at the same position of input P1.
  • Either method may be also selected to reduce an error with an input signal.
  • a signal except a bit specified by the control signal CB may be also changed so that difference caused by conversion with an input signal is reduced.
  • the level 16 is represented as [1, 0, 0, 0, 0] (1 denotes a subfield in which emission occurs and 0 denotes a subfield in which no emission occurs) in subfield representation depending upon the weight of emission of the power of 2 and the level 15 is represented as [0, 1, 1, 1, 1].
  • the invention is first characterized in that to inhibit such extreme variation of a level and the occurrence of a flicker, a signal processing circuit that processes referring to signals of plural lines the low order subfields of which are common so that the image quality is hardly deteriorated and predetermined subfield data are equal is provided.
  • the invention is second characterized in that the image quality is improved by providing an independent control subfield in a group of common low order subfields.
  • Fig. 9 is a block diagram showing an embodiment of the processing circuit shown in Fig. 8.
  • reference numbers 205 and 208 denote an adding circuit
  • 206 and 209 denote a subtracting circuit
  • 207 denotes a quantizing circuit the characteristic of which varies according to a control signal CB from an external device
  • 210 denotes an independent bit adding circuit
  • 202 denotes a processing circuit.
  • Picture elements P1 and P2 adjacent in a vertical direction input to the processing circuit 202 are input to the adding circuit 205 and the subtracting circuit 206.
  • P1 and P2 are added and an average value f0 is calculated as shown in a mathematical expression (1).
  • P2 is subtracted from P1 and a value f1 based upon difference shown in a mathematical expression (2) is calculated.
  • f0 (P1 + P2)/2
  • f1 (P1 - P2)/2
  • f1 is input to the quantizing circuit 207 and is converted to f1'.
  • the quantizing circuit 207 processes so that a low order bit specified by the control signal CB is '0'.
  • f0 generated in the adding circuit 205 is added to a signal f1' the desired low order bit of which is converted to 0 by the control signal CB in the adding circuit 208 and is output as converted output O1.
  • f1' is subtracted from f0 and is output as converted output O2.
  • low order n bits of f1' are 0, low order n bits of f0 are output as an equal value as they are for the respective low order n bits of O1 and O2 acquired by adding or subtracting f0/from f0. That is, the respective low order n bits of O1 and 02 are equalized. Strictly speaking, as addition and subtraction have the equal result of calculation (operation according to binary notation) in a state without carrying and borrowing, the data of a low order 'n+1'th bit can be converted so that it is equal in O1 and O2.
  • the average value (O1 + O2)/2 of the outputs O1 and O2 at this time is always equal to the average value f0 of inputs P1 and P2 and the average signal level of adjacent two lines can be always kept the same.
  • an error caused by equalizing low order bits is equally dispersed by (
  • Q1 and Q2 are input to the independent bit adding circuit 210 and are output as Q1 and Q2 to which a predetermined independent bit is added.
  • Information EQ and RU based upon an error of conversion when f1 is converted to f1' in a process of quantizing processing are output from the quantizing circuit 207 to control the operation of the independent bit adding circuit 210.
  • the details of EQ and RU and the operation of the independent bit adding circuit 210 will be described later.
  • the deterioration of image quality depending upon bit data equivalent to a group of low order subfields is minimized and in addition, low order bit data for adjacent two lines can be commonized.
  • the operation of 1/2 can be realized by rounding down low order bits, it is not definitely shown, however, as shown in the mathematical express ions (1) and (2), the output of the adding circuit 205 and the subtracting circuit 206 may be halved.
  • a device connected to the adding circuit 208 and the subtracting circuit 209 may also halve.
  • the characteristic of the quantization of the quantizing circuit 207 is controlled according to a control signal CB and it can be controlled according to setting of the control signal CB from an external device how many low order bits are commonized.
  • the average signal level f0 of two lines is a low frequency component in the vertical direction of an image and a value f1 based upon difference between two lines is a high frequency component in the vertical direction.
  • the high frequency component f1 in the vertical direction becomes 0 in a subfield equivalent to a low order bit by the quantizing circuit 207 and only the low frequency component of f0 is included.
  • the low order subfield is limited to a low frequency component the vertical resolution of which is only f0 and display in a state in which the number of data in the address control period is thinned out (the same data is simultaneously addressed) can be made.
  • the resolution information of a specific subfield equivalent to a desired bit can be limited by dividing into plural vertical frequency components, selecting a bit to be added or subtracted by the quantizing means and synthesizing again as described above and hereby, the first characteristic of the invention to reduce the address control period can be acquired.
  • Figs. 10A to 10D show a state of bits of each signal output to terminals O1, O2, Q1 and Q2 shown in Fig. 9.
  • Fig. 10A shows the output O1 of the adding circuit 208 and Fig. 10B shows the output O2 of the subtracting circuit 209.
  • Figs. 10C and 10D show the outputs Q1 and Q2 of the independent bit adding circuit 210 shown in Fig. 9 and a bit ⁇ is added as an independent bit.
  • the position of the bit ⁇ is set to any of a bit 0 to a bit n-2.
  • Figs. 11 are explanatory drawings for explaining the principle of reducing the deterioration of image quality by the added independent bit.
  • Fig. 11A shows input picture elements P1 and P2 vertically adjacent and input to the processing circuit 202 shown in Fig. 9 and shows a part of a signal having gentle slope.
  • Fig. 11A shows input picture elements P1 and P2 vertically adjacent and input to the processing circuit 202 shown in Fig. 9 and shows a part of a signal having gentle slope.
  • Fig. 11A shows input picture elements P1 and P2 vertically adjacent and input to the processing circuit 202 shown in Fig. 9 and shows a part of a signal having gentle slope.
  • Fig. 11A shows input picture elements
  • FIG. 11B shows the output O1 of the adding circuit 208 shown in Fig. 9 and the output O2 of the subtracting circuit 209, and both O1 and O2 are converted to the average value f0 of P1 and P2 by quantizing f1' to zero by processing in the quantizing circuit 207.
  • Fig. 11C shows the outputs Q1 and Q2 of the independent bit adding circuit 210, Q1 and Q2 are not at the same level by the addition of the independent bit but difference in a level equivalent to the ⁇ th power of 2 can be made. To minimize a mean square error caused by conversion, 1/2 of the difference of the ⁇ th power of 2 has only to be equally distributed to Q1 and Q2 as shown in Fig. 11C and hereby, the average value of Q1 and Q2 is equal to the average value f0 of P1 and P2.
  • Display output signals Q1 and Q2 can be made at a level close to the original images of P1 and P2 by above-mentioned processing and there is effect of inhibiting the deterioration of image quality.
  • the location of the independent control bit ⁇ can be controlled according to a control signal CB from an external device, the configuration including subfields simultaneously addressed by the same data for two lines and a subfield independently controlled in units of line is suitably set and an image the quality of which is hardly deteriorated can be always displayed.
  • Fig. 12 is a block diagram showing an embodiment of the independent bit adding circuit shown in Fig. 9.
  • a reference number 211 denotes a logic inverting circuit
  • 212a and 212b denote a switching circuit
  • 212c denotes a bus switching circuit
  • 213 denotes a low order bits processing circuit
  • 210 denotes the independent bit adding circuit.
  • O1 [n] shown in Fig. 12 denotes a single signal of a bit n (an (n + 1)th bit from LSB, however, the bit may be 0) of a picture element
  • O1 [n:m] denotes (n - m + 1) pieces of bus signals from the bit n of the picture element O1 to a bit m. Another signal name is also similar.
  • the quantizing circuit 207 shown in Fig. 9 outputs two types of control signals EQ and RU generated according to the amount of an error caused when processing for quantizing f1' based upon f1 is executed and these two signals are input to the independent bit adding circuit 210.
  • the control signal EQ is a logic signal which has a value of 1 in case an error of conversion from f1 to f1' is relatively small, concretely, when the following mathematical expression (5) is met, the control signal EQ is at a high level and in other case, it is at a low level. + ⁇ > (f1' - f1) > - ⁇ However, (0 ⁇ [ ⁇ power of 2]).
  • the control signal RU is a logic signal which has a value of 1 when an error of conversion from f1 to f1' is relatively large and f1' is converted so that it becomes large, concretely, when the control signal RU meets the following mathematical expression (6), it is at a high level and in other case, it is at a low level. (f1' - f1) ⁇ ⁇ However, (0 ⁇ ⁇ ⁇ [ ⁇ power of 2]).
  • ⁇ is a threshold for determining whether an independent control bit is added or not and as a minute level varied by the independent control bit is [the ( ⁇ - 1) power of 2], the maximum effect is acquired when an error 6 of quantization is [the ( ⁇ - 1) power of 2]. Therefore, 6 may be (0 ⁇ ⁇ ⁇ [ ⁇ power of 2]), however, to prevent excess correction, it is desirable that 6 is in a range from [the ( ⁇ - 2) power of 2] to [the ( ⁇ - 1) power of 2].
  • 6 [( ⁇ - 1) power of 2] x 0.7.
  • the switching circuits 212a and 212b are respectively switched to the side of a high level and commonized bits O1 and O2 [ ⁇ :0] are output as a low order bit Q1 [ ⁇ :0] of Q1 and a low order bit Q1 [ ⁇ :0] of Q2 as they are via the switching circuits 212a, 212b and 212c. This shows that in case an error of conversion in the quantizing circuit 207 is small, output is made as it is without adding an independent bit.
  • the independent bits Q1 [ ⁇ ] and Q2 [ ⁇ ] are corrected according to the control signals EQ and RU from the quantizing circuit 207 so that an error with each original image becomes smaller and the deterioration of image quality can be reduced.
  • Fig. 13 shows truth values of the operation of the independent bit adding circuit 210 shown in Fig. 12 for the control signals EQ and RU.
  • Fig. 13 shows the logic operation of the independent bit adding circuit.
  • O1 [ ⁇ ] and O2 [ ⁇ ] respectively shown in Fig. 13 show that input O1 [ ⁇ ] and O2 [ ⁇ ] are output as Q1 [ ⁇ ] and Q2 [ ⁇ ] as they are.
  • '1' denotes that Q1 or Q2 is a little increased and '0' denotes that Q1 and Q2 are unchanged.
  • the position ⁇ of the independent bit is controlled by the control signal CB shown in Fig. 9.
  • a threshold 6 showing whether the independent bit is added or not is also set together with the value of ⁇ .
  • Fig. 14 is a block diagram showing an embodiment of the low order bits processing circuit shown in fig. 12.
  • a reference number 214 denotes an exclusive-OR (EXOR) circuit
  • 215 denotes a logic inverting circuit
  • 216a to 216d denote a switching circuit
  • 213 denotes a low order bits processing circuit.
  • the path representation of a signal and the representation of each bit are similar to those in Fig. 12.
  • the low order bits processing circuit 213 is provided to correct that the average value of Q1 and Q2 increases or decreases by [the ( ⁇ - 1) power of 2], compared with the average value (also equal to the average of inputs P1 and P2) of O1 and O2 when O1 [ ⁇ ] and O2 [ ⁇ ] which are the same signal (0, 0) or (1, 1) are converted to (0, 1) or (1, 0) as Q1 [ ⁇ ] and Q2 [ ⁇ ] as described above.
  • As low order bits of ( ⁇ - 1) and the following processed in the low order bits processing circuit 213 are converted to an equal value between O1 and O2 and between Q1 and Q2, they can be processed by one system of processing circuit.
  • O1 [ ⁇ - 1] and O2 [ ⁇ - 1](both are equal) are represented as O [ ⁇ - 1]
  • Q1 [ ⁇ - 1] and Q2 [ ⁇ - 1](both are also equal) are represented as Q [ ⁇ - 1].
  • O1 [ ⁇ ] and O2 [ ⁇ ] are also equally converted, they are represented by O [ ⁇ ].
  • Fig. 15 shows the logic operation of the independent bit adding circuit.
  • O[ ⁇ ] is 1
  • O [ ⁇ - 1] is 0, in case Q1 [ ⁇ ] and Q2 [ ⁇ ] are independently converted to (1, 0) or (0, 1), either of Q1 [ ⁇ ] or Q2 [ ⁇ ] is 0 though O1 [ ⁇ ] and O2 [ ⁇ ] are both 1 and the average value of Q1 and Q2 decreases by [the ( ⁇ - 1) power of 2].
  • Q [ ⁇ - 1](O [ ⁇ - 1]) is converted from 0 to 1.
  • the average value of Q1 and Q2 can be increased by [the ( ⁇ - 1) power of 2], as a whole, the average value of Q1 and Q2 can be equalized to the average value (also equal to the average of the inputs P1 and P2) of O1 and O2 and the deterioration of image quality can be reduced.
  • the average value of Q1 and Q2 can be also always substantially equal to the average value (also equal to the average of the inputs P1 and P2) of O1 and O2 and hereby, the deterioration of image quality can be reduced.
  • only one subfield is independently controlled in a group of low order subfields, however, the invention is not limited one and plural subfields may be also independently controlled.
  • the particle of noise caused by the diffusion of an error may be also finely controlled similarly as in prior art by independently controlling a subfield equivalent to a bit 4 or 5 according to this embodiment and independently controlling a bit equivalent to the least significant subfield.
  • the address control period of a predetermined subfield is reduced and this time can be allocated to the improvement of image quality in luminance, gradation and a pseudo contour.
  • the quality of display can be further improved by providing a subfield independently addressed every line in a part of the group of low order subfields.
  • the number of data is thinned out in many subfields, the acquired time is allocated to the sustention period, however, in the case of high-definition display though the luminance is low, the image quality suitable for the contents of an image and the purpose of a user can be realized by reducing subfields in which data is thinned out or by not thinning data out.
  • High quality display where the deterioration of image quality is hardly striking can be realized by dividing an input picture signal into vertical frequency components, limiting display resolution information and reducing time for controlling a lighted picture element.
  • a conversion error caused by the compression of the address control period can be dispersed substantially equally by equalizing the average value of two lines of a display signal to the average value of two lines of an input signal possibly and the deterioration of image quality can be reduced.
  • the address control period of a predetermined subfield is reduced and this time can be allocated to the improvement of image quality in luminance, gradation and a pseudo contour.
  • a conversion error caused by the compression of the address control period can be substantially equally dispersed by equalizing the average value of two lines of display signal to the average value of two lines of an input signal possibly and the deterioration of image quality can be reduced.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
EP20010306864 2000-09-05 2001-08-13 Dispositif d'affichage et méthode de visualisation d'image Expired - Lifetime EP1193672B1 (fr)

Applications Claiming Priority (4)

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JP2000273545A JP2002082647A (ja) 2000-09-05 2000-09-05 表示装置および表示方法
JP2000273545 2000-09-05
JP2000380289A JP4633920B2 (ja) 2000-12-14 2000-12-14 表示装置および表示方法
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WO2012098904A1 (fr) * 2011-01-20 2012-07-26 パナソニック株式会社 Et procédé de commande pour dispositif de visualisation d'image dispositif de visualisation d'image

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KR100578836B1 (ko) 2003-11-19 2006-05-11 삼성에스디아이 주식회사 플라즈마 디스플레이 패널의 구동 장치 및 플라즈마디스플레이 패널의 화상 처리 방법
KR20110026615A (ko) * 2009-09-08 2011-03-16 삼성전자주식회사 잔상을 저감시키는 디스플레이장치 및 그 구동방법

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EP0874349A1 (fr) * 1997-04-25 1998-10-28 THOMSON multimedia Procédé d'adressage de bits sur plusieurs lignes d'un écran à plasma
EP0890941A1 (fr) * 1997-07-07 1999-01-13 Matsushita Electric Industrial Co., Ltd. Méthode pour l'affichage de niveaux de gris dans un panneau d'affichage à plasma
US5874933A (en) * 1994-08-25 1999-02-23 Kabushiki Kaisha Toshiba Multi-gradation liquid crystal display apparatus with dual display definition modes

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US5874933A (en) * 1994-08-25 1999-02-23 Kabushiki Kaisha Toshiba Multi-gradation liquid crystal display apparatus with dual display definition modes
EP0874349A1 (fr) * 1997-04-25 1998-10-28 THOMSON multimedia Procédé d'adressage de bits sur plusieurs lignes d'un écran à plasma
EP0890941A1 (fr) * 1997-07-07 1999-01-13 Matsushita Electric Industrial Co., Ltd. Méthode pour l'affichage de niveaux de gris dans un panneau d'affichage à plasma

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Publication number Priority date Publication date Assignee Title
WO2012098904A1 (fr) * 2011-01-20 2012-07-26 パナソニック株式会社 Et procédé de commande pour dispositif de visualisation d'image dispositif de visualisation d'image

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EP1187089B1 (fr) 2008-05-21
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EP1193672A3 (fr) 2003-01-08
EP1187089A3 (fr) 2005-06-29
EP1193672B1 (fr) 2008-10-08
DE60134097D1 (de) 2008-07-03

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