EP1188233A1 - Circuit integre electronique comprenant un composant electronique et un element de temporisation connecte audit composant - Google Patents

Circuit integre electronique comprenant un composant electronique et un element de temporisation connecte audit composant

Info

Publication number
EP1188233A1
EP1188233A1 EP00925829A EP00925829A EP1188233A1 EP 1188233 A1 EP1188233 A1 EP 1188233A1 EP 00925829 A EP00925829 A EP 00925829A EP 00925829 A EP00925829 A EP 00925829A EP 1188233 A1 EP1188233 A1 EP 1188233A1
Authority
EP
European Patent Office
Prior art keywords
conductor
electronic circuit
circuit according
antenna elements
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00925829A
Other languages
German (de)
English (en)
Inventor
Roger Ahlm
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Bofors AB
Original Assignee
Avancerade Logikmaskiner AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Avancerade Logikmaskiner AB filed Critical Avancerade Logikmaskiner AB
Publication of EP1188233A1 publication Critical patent/EP1188233A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30—Time-delay networks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
    • H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q7/00—Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Integrated electronic circuit comprising an electronic component and a delay element which is connected to the component
  • the invention relates to a delay circuit with at least one active electronic component and a delay element connected to the component.
  • components or configurations with a certain time constant or delay are used.
  • delay components separated from the other components.
  • An example of such an electronic circuit is the oscillator.
  • a well-known way to set up an oscillator is to feed back a gate circuit with an inverter function, for example a simple inverter, via some form of time delay.
  • the time delay can be implemented in various ways, for example by special delay circuits.
  • crystal oscillator In applications where high working frequencies are used, and particu- larly when the requirements of a frequency-stable oscillator are high, a crystal oscillator is used instead.
  • a problem with use of crystal oscillators is that they are relatively large. In connection with certain types of integrated circuits this becomes a problem in that a special circuit must be used with the oscillator or a crystal must be connected from outside the integrated circuit.
  • a phase array antenna incorporates a group of identical radiation elements. By controlled feeding of the elements by means of a conductor network so that they act in phase, an electromagnetic beam with good direc- tionality can be achieved.
  • the conductor network can also incorporate electronically controlled phase inverters and possibly amplifiers, one for each element, by means of which the direction of the beam can be varied without need of mechanically moveable components.
  • phase inverters are complicated and ex- pensive instruments, and for that reason this type of antenna has not enjoyed great commercial success.
  • Another factor which limits the use of this type of antenna is the frequency dependency of the phase inverters.
  • the foremost area of use for the phase array antenna is within the radar area.
  • One purpose of the invention is to produce an electronic circuit that can be embodied in a simple manner and that can be combined with other circuits in an integrated form.
  • the electronic circuit enables electronic delay of an electric signal. This purpose is achieved by inclusion in the invention of the special features cited in Claim 1.
  • an oscillator has been achieved that is realizable in all components in integrated form.
  • an electronically controlled antenna has been achieved that lacks the disadvantages of the phase inverters.
  • Electric signals from individual antenna elements are differentially delayed dependent on the position of the antenna elements in relation to the impinging electromagnetic wave fronts. Emanating from one matrix of the antenna elements that are distributed across a surface, the signals can be selectively delayed from indi- vidual antenna elements and thus affect the direction in which the antenna will be sensitive.
  • the delay is preferably produced in integrated circuits, which are provided in connection with the antenna elements.
  • an installation of conductors of different length is provided between the antenna elements and a receiving unit.
  • a conductor of a certain length is switched on by a control unit dependent on the position of the antenna element in relation to an impinging wave front of an electromagnetic wave.
  • the given position affects the detectable characteristics of the electric signals that are received.
  • the installation of conductors and the control unit are joined with other electronic components in a cell unit.
  • the conductor is embodied in integrated form on an insulating layer.
  • FIG 1 schematically shows an embodiment according to the invention of an electronic circuit in the form of an oscillator
  • FIG 2 schematically shows the distributed resistance and capacitance of a conductor
  • FIG 3 is a diagram of the delay in a conductor as a function of the length of the conductor
  • FIG 4 is a principle block diagram that shows an alternative embodiment according to the invention of an electronic circuit in the form of a cell unit with antenna peripherals, shows in principle how several cell units are provided on a portion of an antenna surface
  • schematically shows an embodiment of a delay element in the form of a conductor, which constitutes part of the invention shows an embodiment schematically of a conductor that can be connected in different lengths
  • an inverter coupling 10 is shown schematically, whose input 11 is connected to its output 12 via a long conductor 13.
  • a time period T is given by the following formula where v c is the velocity of electromagnetic propagation in the conductor.
  • the frequency is 200MHz. This is under the condition that the delay in the inverter coupling itself is on the magnitude of some picoseconds. With low propagation in the inverter coupling's delay of, for example, 10% the inaccuracy is in the same class as that of a crystal oscillator. This length required for attainment of the desired delay acts in many cases as a deterrent. The actually delay in the conductor is also dependent on the conductor's distributed resistance and the conductor's distributed capacitance.
  • the conductor is embodied as a metal conductor in an integrated process, for example a CMOS process.
  • Conductor 13 is embodied with width w and rests on some form of insulating layer 14.
  • the insulating layer contains both metal oxide and field oxide and has thickness b.
  • the dielectric constant of the insulating layer affects the choice of the dimensions of the conductor and of other components. As the dielectric constant of the insulating layer increases, the dimensions can be reduced.
  • the insulating layer is constituted of silicon oxide.
  • the insulating layer can also be embodied in glass or another ceramic material.
  • the insulating layer can be embodied as an air layer.
  • the conductor rests on stanchion-like formations that extend from the semiconductor or base material used.
  • the conductor should be embodied so that it gives rise to as little in- ductance as possible.
  • the conductor preferably runs in a loop with several parallel conductor sections so that the directions of the current in adjacent conductor sections are opposite to each other. It is also possible to provide two parallel loops in opposition or in double loops.
  • the conductor is embodied in two loops running in parallel of which one is fed with the signal to be delayed and the other is fed with the inverse of the signal. See FIG 7 and FIG 9. In this way the influence of several different forms of interference is minimized.
  • time delay occurs as a result of the conductor's distributed resistance and the conductor's distributed capacitance according to the formula below.
  • the distributed characteristics can be illustrated according to FIG 2.
  • the total length of the conductor is I.
  • C is the total capacitance of the conductor
  • R is the total resistance of the conductor.
  • K c —
  • b ⁇ the dielectricity constant for the insulating (oxide) layer
  • p the resistance in the conductor material
  • a the thickness of the conductor
  • b the thickness of the insulating (oxide) layer
  • w the narrowest width of the conductor.
  • the time delay can be reformulated as time delay in small time segments, where the following obtains:
  • the diagram in FIG 3 with the curve t A shows the delay that depends on the velocity of propagation in the conductor.
  • the curve t RC shows the de- lay that depends on the resistance R of the conductor and capacitance C.
  • the velocity of propagation v in the conductor cannot be affected to any great degree. It can be shown that
  • Insulation layer 14 is embodied preferably with significantly greater thickness b than the occurring oxide layer.
  • a suitable thickness exceeds 10 ⁇ m and is preferably in the range of 10-100 ⁇ m if the oscillator is to be used at frequencies around 1 GHz.
  • a thickness b suitable for many applications is 20 ⁇ m. With increasing values of b other dimensions can also increase. External dimensions naturally also affect the final dimensions.
  • the thickness of conductor 13 is in commonly occurring processes around 1 ⁇ m, and an increase in thickness, but not width, improves the oscillator's characteristics and performance.
  • Inductive characteristics also need special attention as regards the length of the conductor. It is thus not suitable to embody the conductor in a spiral form or similar.
  • the length should also be suited to the desired wavelength of the oscillator.
  • the length of the conductor preferably amounts to a multiple of the half wavelength or, more preferably, half the wavelength.
  • the invention comprises antenna elements 16, which are connected to a cell unit 22.
  • Cell unit 22, which is designated by dashed lines in FIG 4, comprises an installation of individually switchable delay elements 18, by means of which a signal received in antenna element 16 is directed on to a receiver 17 acting in common for a number of cell units 22. The received signal is amplified in an amplifier 23.
  • Switching of delay elements 18 is accomplished in the embodiment according to FIG 4 by means of a demultiplexer 19 and a multiplexer 21.
  • Delay elements 18 in the form of conductors connect demultiplexer 19 and multiplexer 21 , and an individual delay element 18 is switched by means of adjustment of demultiplexer 19 and/or multiplexer 21. Adjustment is done by a control unit 20, which is connected to a central processing unit (CPU) 24 in common for several cell units 22.
  • CPU central processing unit
  • the incoming signal is prefera- bly merged with a signal from a local oscillator 25 and sent to a mixer 26. See also FIG 8. From mixer 26 the signal suitably has a frequency on the order of magnitude of some GHz.
  • the different control units 20 and possibly also the local oscillators 25 are connected to a CPU 24, preferably by a buss connection 27. It can be suitable to include in CPU 24 means for synchronization of the different oscillators 25. Synchronization can also occur via control unit 20.
  • the oscillator is not included in the cell unit. A common oscillator is instead preferably located in the CPU. The embodiment of the oscillator used should be adjustable for different frequency bands.
  • All components, which are included in cell unit 22, can be embodied to be integrated in semiconducting materials.
  • the semiconductor process used should be selected with regard to high frequency characteristics, especially as regards amplifier 23, and to characteristics that affect conductors that can be included in the delay elements.
  • the noise ratio should be on the order of magnitude of 0.5 dBu.
  • Very low capacity switches should be sought.
  • the conductor is embodied as a metal conductor in an integrated process, for example a CMOS process.
  • Receiver 17 can be embodied in a conventional way as a satellite receiver. It can be the case that satellite receivers are provided with control instruments for motorized control of a conventional parabola antenna. Receiver 17 includes similar control instruments, and a control output 28 transfers control information to CPU 24.
  • the control information can include instructions to sweep with the electrically controlled antenna across a certain arc in connection with finding a new transmitter. When a transmitter is found, the control information will continuously control the adjustment of the antenna so that the transmitter can be followed if the antenna is physically angled or displaced in relation to the transmitter.
  • a signal conductor 29, preferably from each of the cell units 22, conducts a received signal from the antenna to receiver 17.
  • the quality and certain characteristics of the signal from the antenna affect how CPU 24 will be controlled in turn in order to affect the different control units 20 in the cell units 22.
  • the number of delay elements 18, which are required in order that the desired possibilities for fine tuning of the antenna can be achieved, varies with the current application. For normal satellite receiver application some hundreds of delay elements 18 should be sufficient.
  • the characteristics of amplifier 23 also affect how many delay elements 18 are required. With very good amplification characteristics and signal-noise relation in the amplifier the number of directionally adjusting delay elements 18 can be held down.
  • An antenna embodied with components according to the above can be embodied as indicated by FIG 5.
  • Provided on a surface are a number of cell units 22. Every cell unit 22 is connected to four antenna elements 16A-16D attached in pairs. Two opposing first antenna elements 16A and 16B are dedicated to reception of horizontally polarized signals, and two opposing second antenna elements 16C and 16D are dedicated to reception of verti- cally polarized signals. Other configurations can also be used for reception of different types of signals. Every antenna element 16A-16D can be some mil- limeters long and wide, and different forms can occur. Antenna elements 16A-16D are preferably embodied of metal. The outer dimensions of the antenna with a suitable number of antenna elements can be such that the surface of the antenna is on the order of magnitude of 0.1-1.0 m 2 . Buss connection 27 preferably runs through or past each cell unit 22.
  • the different antenna elements 16A-16D can be attached to amplifier 23 directly or via a multiplexer, which is suitably controlled by control unit 20.
  • FIG 6 shows in principle how conductors 18 can be embodied.
  • Each conductor 18 is embodied with width w and rests on some form of insulating layer 14.
  • the insulating layer is normally comprised of both metal oxide and field oxide and had thickness b.
  • the semicon- ductive material amplifier 23 and further semiconductor circuits can be embodied.
  • the insulating layer is made of silicon oxide.
  • the insulating layer can also be embodied of glass.
  • the insulating layer can be embodied as a layer of air.
  • the conductor rests on stanchion-like formations which emerge from the semicon- ductive or base material used.
  • An example of a double conductor with selectable delay is shown in
  • Signal S that is to be delayed is directed into a buffer or line amplifier 30.
  • the inverse of the signal S' is also directed into line amplifier 30.
  • Two parallel conductors that run together in a long loop extend from line amplifier 30. As indicated above, the total length of the loop can be as great as 0.5 m. From each of the two parallel conductors 13, terminal conductors 31 ,
  • the selection of conductor length and thus the terminal conductor is made in a demultiplexer (not shown) that directs the delayed signal via control lines 33 and adjustable gate circuits 34.
  • the signal that is delayed can be analog, for example in conjunction with an antenna of the type that is shown in FIG 4 and FIG 5 or digital in conjunction with an oscillator or similar.
  • the delay can be selected in stepwise fashion with each step corresponding to the length of the conductor between two output sites.
  • mixer 26 When the device according to the invention is used with antennas and receivers, mixer 26 is normally used.
  • An example of such a mixer 26 is shown in FIG 8.
  • Two signals in opposite phase are output from a local oscillator 25.
  • the signals in opposite phase are directed to a mixer 26 that comprises four MOS transistors in the embodiment shown.
  • a preferred embodiment of conductor 13 is shown in FIG 9.
  • Conductor 13 runs in two parallel tracks in elongated loops. The two tracks are fed with signals in opposite phase. In this way the circuit is less sensitive to interference.
  • a portion of a ground conductor 35 is located in each loop. Ground conductor 35 suitably runs in the center between two loops and essentially to the bottom of a loop. Ground conductor 35 is connected to a ground plane.
  • the distance between two conductors in a loop is on the same order of magnitude as the distance between two loops. These distances preferably are approximately 20 ⁇ m.
  • the width of the conductor is on the order of magnitude of half of the given distance or about 8 ⁇ m. See also FIG 12.
  • the total length of the conductor is determined by the current application and can be on the order of magnitude of 0.5 m or larger.
  • a ground conductor 35 can also be used if conductor 13 is embodied as a single conductor.
  • Amplifiers can be provided in different sections of the long conductor track.
  • a suitable embodiment of an amplifier for use in digital applications is shown in FIG 10.
  • Two NAND gate circuits 36 provided with two inputs are fed back via their outputs so that change in the gate circuits occurs at the same time.
  • the signal is directed to the amplifier as an input signal and its inverse S'.
  • FIG 11 shows schematically an example of how a chip with delay elements according to the invention can look in cross section.
  • Both the conductors 13 are embodied so that an insulating material 14 surrounds them.
  • the insulating material is made of silicon oxide.
  • Silicon oxide layer 14 has a thickness that means that the distance N to a underlying silicium layer can amount to 20 ⁇ m.
  • the width of conductors 13 amounts to approximately 8 ⁇ m, while the width of the ground conductor amounts to approximately 2 ⁇ m.
  • a glass layer 37 is provided on top of silicon oxide layer 14. If air is used as the insulating mate- rial, glass layer 37 can be eliminated.
  • FIG 13 to FIG 15 are diagrams that schematically show propagation of electromagnetic fields around conductors 13 when ground conductor 35 is used.
  • a loop surrounds the two central conductors 13, while conductor 13 to the farthest on the right belongs to an adjacent loop.
  • a boundary line 38 indi- cates in the figures that two different dielectric constants occur.
  • Conductors 13 and ground conductors 35 are completely recessed into the insulating layer.
  • the solid field lines reference the magnetic field and the arrows indicate electric field strength.
  • the electric field strength at the ends of the arrows should be proportional to the length of the arrows.
  • the dielectric constant 35 in the example in FIG 13.
  • ground conductor 35 acts to diminish the connection between the conductors in different loops.
  • a higher dielectric constant also offers the possibility of diminishing the distance between the conductors without increased risk of interference.
  • the dielectric constant ⁇ 3.9 in the material under boundary line 38.
  • a suitable silicon dioxide layer has proven to have this dielectric constant.
  • FIG 16 to FIG 18 are diagrams that schematically show propagation of electromagnetic fields around conductors 13 when ground conductor 35 is not present. Other parameters are in agreement with the examples in FIG 13 to FIG 15. In all of these three cases it is clearly indicated that the risk of cross talk and other interference between the conductors in different portions of the loop increases when the ground conductor is not present.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un circuit électronique possédant au moins un composant électronique actif (10) et un élément de temporisation connecté audit composant. L'élément de temporisation comprend un conducteur électrique (13, 18) composé d'un matériau conducteur sur une couche isolante (14), aménagé en sorte que le couplage capacitif du conducteur avec son entourage devienne faible. On tire le conducteur (13, 18) de manière à réduire au minimum son inductance. Le composant électronique (10) et le conducteur (13, 18) sont intégrés dans un circuit intégré. Le conducteur (13, 18) est tiré pour former des boucles d'une certaine longueur, et un conducteur à la terre (35) possédant une certaine longueur et connecté au plan de masse est créé entre les boucles. L'élément de temporisation peut être utilisé dans un couplage d'oscillateur ou dans une antenne pilotée électroniquement. Dans le couplage d'oscillateur le composant électronique (10) comprend un couplage d'inverseur (11) avec une entrée (11) et une sortie (12). Le conducteur (13) sert à connecter l'entrée (11) à la sortie (12) et à créer ainsi un oscillateur. L'antenne pilotée électroniquement comprend un récepteur (17) et un certain nombre d'éléments antenne (16) connectés au récepteur (17). Des éléments antenne individuels (16) sont connectés au récepteur (17) à travers des éléments de temporisation sélectionnables automatiquement (18) en sorte que les signaux électriques provenant de différents éléments antenne (16) soient temporisés de façon différentielle en fonction de la position des éléments antenne par rapport aux fronts d'ondes électromagnétiques incidentes.
EP00925829A 1999-04-21 2000-04-19 Circuit integre electronique comprenant un composant electronique et un element de temporisation connecte audit composant Withdrawn EP1188233A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9901450A SE519587C2 (sv) 1999-04-21 1999-04-21 Fördröjningskrets
SE9901450 1999-04-21
PCT/SE2000/000744 WO2000065714A1 (fr) 1999-04-21 2000-04-19 Circuit integre electronique comprenant un composant electronique et un element de temporisation connecte audit composant

Publications (1)

Publication Number Publication Date
EP1188233A1 true EP1188233A1 (fr) 2002-03-20

Family

ID=20415319

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00925829A Withdrawn EP1188233A1 (fr) 1999-04-21 2000-04-19 Circuit integre electronique comprenant un composant electronique et un element de temporisation connecte audit composant

Country Status (4)

Country Link
EP (1) EP1188233A1 (fr)
AU (1) AU4445700A (fr)
SE (1) SE519587C2 (fr)
WO (1) WO2000065714A1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0446405A (ja) * 1990-06-13 1992-02-17 Murata Mfg Co Ltd ディレイライン及びその製造方法
WO1994017558A1 (fr) * 1993-01-29 1994-08-04 The Regents Of The University Of California Composant monolithique passif
JP2513405B2 (ja) * 1993-06-11 1996-07-03 日本電気株式会社 ２周波共用アレイアンテナ
US5619061A (en) * 1993-07-27 1997-04-08 Texas Instruments Incorporated Micromechanical microwave switching

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0065714A1 *

Also Published As

Publication number Publication date
SE519587C2 (sv) 2003-03-18
SE9901450L (sv) 2000-10-22
AU4445700A (en) 2000-11-10
SE9901450D0 (sv) 1999-04-21
WO2000065714A1 (fr) 2000-11-02

Similar Documents

Publication Publication Date Title
Tousi et al. A Ka-band digitally-controlled phase shifter with sub-degree phase precision
JP5132054B2 (ja) オンチップ回路パッド構造
US5754145A (en) Printed antenna
US8138989B2 (en) Transmission line distributed oscillator
KR20080051180A (ko) 칩 안테나 상 ㎜-파 완전 집적 위상 어레이 수신기 및송신기
US20060208957A1 (en) Dipole antenna having a periodic structure
US11075050B2 (en) Miniature slow-wave transmission line with asymmetrical ground and associated phase shifter systems
US4604591A (en) Automatically adjustable delay circuit having adjustable diode mesa microstrip delay line
CN101326681A (zh) 差动供电缝隙天线
Abdalla et al. A planar electronically steerable patch array using tunable PRI/NRI phase shifters
EP2707925B1 (fr) Lignes à retard de temps réel à bande ultra-large
KR100980678B1 (ko) 위상 천이기
US20090237306A1 (en) Compact integrated monopole antennas
US6486829B1 (en) Integrated electronic circuit comprising an oscillator with passive circuit elements
WO2000065714A1 (fr) Circuit integre electronique comprenant un composant electronique et un element de temporisation connecte audit composant
WO2000072442A1 (fr) Circuit electronique integre comprenant un composant electronique et un circuit a retard presentant une structure de conducteur a paire torsadee
US20220416382A1 (en) Tsv phase shifter
JP3398527B2 (ja) 伝送線路の交差構造
JPH0646682B2 (ja) 一端短絡型マイクロストリツプアンテナ
JP2002217636A (ja) ダイポールアンテナ
Zaitsev et al. Patch-MMIC-ferrite integration in novel phased array technology
Lesko et al. Compact time-delay shifters that are process insensitive
JP2000151204A (ja) 可変位相偏移を有する高周波回路
JPH09172304A (ja) コプレーナ線路のインピーダンス調整器
SE518928C2 (sv) Elektroniskt styrd antenn

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20011121

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: BOFORS DEFENCE AB

17Q First examination report despatched

Effective date: 20060727

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: BAE SYSTEMS BOFORS AB

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20070207