EP1181682A1 - Systeme de traitement de donnees pour affichage sur un ecran matriciel - Google Patents

Systeme de traitement de donnees pour affichage sur un ecran matriciel

Info

Publication number
EP1181682A1
EP1181682A1 EP00927318A EP00927318A EP1181682A1 EP 1181682 A1 EP1181682 A1 EP 1181682A1 EP 00927318 A EP00927318 A EP 00927318A EP 00927318 A EP00927318 A EP 00927318A EP 1181682 A1 EP1181682 A1 EP 1181682A1
Authority
EP
European Patent Office
Prior art keywords
pixels
correlator
display
color
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00927318A
Other languages
German (de)
English (en)
French (fr)
Inventor
Jean-Jacques Thomson-CSF Prop. Int. Dépt. FAVOT
Jean-Christophe Thomson-CSF Prop. Int. ABADIE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Callahan Cellular LLC
Original Assignee
Thales Avionics SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales Avionics SAS filed Critical Thales Avionics SAS
Publication of EP1181682A1 publication Critical patent/EP1181682A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/395Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed

Definitions

  • the present invention relates to a data processing system for display on a matrix screen. It applies more particularly to the display on a liquid crystal screen of symbolic representations concerning the parameters making it possible to assist in the piloting and in the navigation of an airplane.
  • the representation of a line will correspond to a distribution of the luminance having the shape of a Gaussian in a direction transverse to this line, which will give the thickness desired for a good visibility and "erase” the effects of steps of 'staircase.
  • numerous distribution laws are known which make it possible to respond to most of the situations encountered.
  • the processing corresponding to the use of these microplates often called filtering, is carried out in a processing unit known by the name of "UMIP", for microplate unit, placed between the memory of pixels and the matrix screen. This implies that digital processing is carried out on all of the pixels, which requires particularly high computing power.
  • the invention proposes a data processing system for display on a matrix screen, of the type comprising a symbol generator connected to an image memory itself connected to a correlator making it possible to implement a processing based on micro-ranges to generate the final image to be displayed on a matrix screen, mainly characterized in that the image memory is organized to be able to read n pixels in parallel and in that the correlator is organized to process these n pixels in parallel.
  • the correlator is divided into two parts allowing the luminance and the chrominance to be treated separately in order to allow a hierarchical processing of the colors.
  • it comprises means for separately processing the color of the lines and the color of the background, and a mixer to enable the decoration elements displayed on the background to be cut out in tone on tone.
  • the correlator is organized in m substantially identical parallel lines making it possible to process in parallel the m pixels of one of the axes of the micro-ranges used.
  • FIG. 3 a block diagram of a correlator for a system according to the invention.
  • the invention therefore proposes to place the UMlP between the image memory and the matrix screen, which corresponds to the basic structure described in the first patent cited above.
  • the memory volume is then strictly limited to the quantity necessary to represent all the pixels and sub-pixels of this matrix screen, which very significantly limits the volume and the cost.
  • the processing between the memory and the UMlP is carried out in parallel on n pixels or sub-pixels. The number of points processed per cycle is thus multiplied by n and the bit rate of the UMlP, with identical display capacity, is itself multiplied by n.
  • FIG. 1 shows a general block diagram of a system according to the invention.
  • This system therefore comprises a symbol generator 101, known in the art, which makes it possible to obtain the values of the positions and the chrominances of the different sub-pixels intended to represent the symbols which will ultimately be displayed on a display screen.
  • the data thus obtained from the generator 101 are stored in an image memory 103.
  • This memory is of the double page type, each page of which has a capacity at least equal to the number of sub-pixels of the display 102.
  • the double page organization makes it possible, in a known manner, to simultaneously write to a page from the symbol generator and read the other page for transmission to the display via processing means of the UMIP type. 104.
  • the memory 103 is further organized so as to allow simultaneous reading of two sub-pixels in parallel, which can be done without any particular problem with the means known in the art.
  • the UMlP 104 comprises on the one hand a correlator 105 with two parallel channels and on the other hand a sequencer 106.
  • This sequencer makes it possible to manage the recording in the memory 103 of information coming from the symbol generator 101, and on the other hand to synchronize the reading of this memory with the processing in the correlator, as well as the display on the screen 102 sub-pixels thus treated.
  • This sequencing is carried out according to a timing diagram which is illustrated in FIG. 2.
  • the synchronization signal is supplied simultaneously to the symbol generator 101, to the image memory 103, to the correlator 105 and to the display 102. for example, the real time cycle taking place between two synchronization pulses lasts 16 ms.
  • This sequencer is made up of a set of logic circuits operating from a clock and which are connected to deliver, according to Boolean logic for example, the signals necessary for the various organs to which the sequencer is connected. To obtain the most compact possible assembly, the sequencer is preferably implanted in a known manner in a circuit of the FPGA type.
  • the correlator 105 makes it possible to process two points in parallel with 4x4 size microplates. This provides real-time processing corresponding to the display speed of the sub-pixels in the i02 display.
  • the position in the sub-pixel of the point to be displayed makes it possible to determine the filter (type, or profile, of the microplate) to be used to move the light point in this sub-pixel so as to obtain the desired effect.
  • the filter type, or profile, of the microplate
  • 16 different filters are used, which therefore allows processing with a fineness of Va of sub-pixels.
  • the luminance and chrominance processing are separate, color codes are used to represent the chrominance, which makes it possible to manage a priority between these colors when the lines of two symbols overlap, in for example displaying a red dot at the intersection of a red line and a blue line.
  • the correlator performs a clipping of the patterns, consisting for example of bordering this white line by two thin lines black lines.
  • FIG. 3 shows a block diagram of the correlator 105. It receives as input the values of the positions and the colors (chrominances) of the two sub-pixels 1 and 2 read in parallel in the memory 103.
  • the values of the positions are applied to two identical tables 301 and 302, which contain the values of 16 filters (microplates) used.
  • the values of these filters have been determined, either experimentally or by calculation, to each correspond to a framing between the position of the physical sub-pixel and that of the plotted sub-pixel, as explained above. For each sub-pixel, a filter is therefore selected respectively in each table.
  • Each of these filters contains light weighting coefficients of the 4x4 sub-pixels that make up the microplage corresponding to the filter. In the embodiment described, this number of light levels is limited to 8, which is perfectly sufficient as experience shows. Therefore for each incoming sub-pixel, the filter tables 301 and 302 each make it possible to obtain 16 coefficients of light levels each corresponding to one of the sub-pixels of the microplage.
  • FIG. 4 shows a table of 16 filters, each of which is selected as a function of the dx and dy offsets of the sub-pixel with respect to the light center of the microplate. These coefficients are then applied to a luminance correlator 303 which will be described later. The values of the colors of the sub-pixels 1 and 2 are in turn applied to a chrominance correlator 304, itself described below.
  • the data from this chrominance correlator are then applied on the one hand to a line color generator 305 and on the other hand to a background color generator 306, also described below.
  • the data coming from the luminance correlator 303 and from the two color generators 305 and 306 are applied to a mixer 307, itself described below, which finally delivers the effective values of the sub-pixels 1 and 2 to be displayed in the matrix screen 102 to obtain the viewing effect.
  • the luminance and chrominance correlators 303 and 304 are formed by the union of independent and generic subsets whose number is equal to that of the sub-pixels contained in the vertical dimension of the micro-ranges. For the rest of this text we will call these subsets "lines", because they are used to process the successive sub-pixels of a display line of the matrix display.
  • the connection between these different lines to take into account the relationships between the sub-pixels of the micro-ranges in the vertical direction is done by means of FIFO type memory placed at the output of the lines and which reinject the content of the lines into the lines. exits. This aspect of the correlators will be described at the level of the complete block diagram represented in FIG. 6.
  • FIG. 5 shows the block diagram of one of these lines, comprising a correlator for the luminance and a correlator for the chrominance.
  • These correlators essentially use logic functions of the OU, SUP and SUP / ECR type. These functions will be described later in this text.
  • This diagram also includes D 504 flip-flops whose well-known role is essentially to ensure the link between the other organs by providing both a memory effect and a delay effect in order to respect the sequencing necessary for the operation of the assembly.
  • a single flip-flop D has been represented each time for the understanding of the operation, but there will possibly be the number necessary in series for obtaining the correct sequencing.
  • the luminance correlator thus produced allows at a time T to combine the coefficients of two new incoming micro-ranges with the coefficients already contained in the correlator and which come from successive correlations of the coefficients of all the previous micro-ranges.
  • the values of the coefficients of the micro-ranges immediately preceding those entering will in the general case be predominant but, as in any correlation, the coefficients of the previous micro-ranges will have a certain effect which will fade as they move away in time.
  • the luminance correlator produced according to this diagram makes it possible to obtain a smoothing effect of the actor elements of the image (the lines) which pass through it.
  • the decor elements of the image are not smoothed and therefore do not pass through the luminance correlator, it would nevertheless be possible, as an alternative embodiment, to use a second luminance correlator to also smooth the elements of the decor.
  • the chrominance correlator as produced in this exemplary embodiment, has two channels which make it possible to independently process the actor elements of the image and the background decoration elements, as defined above.
  • each incoming sub-pixel comprises an attribute, generated at the level of the symbol generator 101, which makes it possible to route the corresponding information to the line path or to the background channel.
  • This attribute also makes it possible to direct the sub-pixels corresponding to the decoration elements to the luminance channel.
  • the data corresponding to the colors, developed in the symbol generator, are in the form of color codes which are hierarchical. This makes it possible to obtain priority for the display of certain colors, in order on the one hand not to have a mixture of colors giving an erratic result, and on the other hand to pass certain priority information, we refer for this to the example given above of the crossing of a red line and a blue line.
  • the line of line colors is connected to the luminance channel so as to correctly manage the intersections and the superpositons of lines of different colors, which therefore have different priority levels for display.
  • This hierarchy is obtained in the diagram using the SUP functions, which are wired from such that after correlation only the most significant codes, corresponding to the priority colors, are retained.
  • the background channel only duplicates the color codes entering via the OR 501 function. It therefore does not make it possible to deal with the problem of the superposition of two different colors for the background. This corresponds to a simplification which is justified by the fact that in the display modes used until now this kind of conflict does not exist. If in the future we had to deal with this problem, we could perfectly use, as for the line path, SUP functions to allow managing the hierarchy between these colors. This would itself be obtained using color codes as for the line.
  • the action of the color correlators is to thicken the theoretical plot with a square profile of width equal to the width of the microplates, that is to say 4 sub-pixels in the example of embodiment described.
  • two sub-pixels are simultaneously processed by injecting the respective coefficients of the associated micro-ranges, into the interlaced structure of the two channels of the correlators.
  • the processing is synchronous, that is to say that at each clock front the coefficients propagate from cell to cell to undergo the correlations.
  • the D flip-flops are used to carry out this propagation.
  • the correlation with the results of the correlations carried out on the preceding lines is effected at the level of the last cells of the correlators, which receive, by return channels coming from FIFO memories loaded by these preceding results, the coefficients corresponding to these results.
  • the SUP / ECR function is a complex logical function which has 3 inputs of coefficients which will be denoted A, B, and C, 2 control inputs denoted E and ABC, and one output denoted S. It is carried out by conventional means combinatorial analysis, so as to perform the functions corresponding to the following truth table:
  • This SUP / ECR function is used in the luminance correlator to combine light levels from the two control inputs which receive as control signals those from the corresponding outputs of the SUP functions.
  • the SUP function is used in the chrominance correlator to combine color codes.
  • the complete correlator represented in FIG. 6, comprises four lines.
  • the value obtained must be multiplied by a fixed factor to adapt it to the dynamics of the display used. This is done in mixer 604.
  • each outgoing color code is transformed into a single primary color as a function of its position in the output stream. In this way one can assign to each of the two green sub-pixels of the pixel QUAD different levels of intensity.
  • the data leaving the correlator corresponding to the luminance, the line color and the background color of the two pixels are combined in a mixer 604 which makes it possible to constitute the sub-pixels actually intended for display in the matrix display. . It can perform two distinct functions.
  • a first function consists in carrying out the luminance product by chrominance in order to obtain inside an object of determined color the intensity profile of the color required.
  • the color information has a rectangular shape 701 in this section, and the luminance a Gaussian shape 702. note that it is this Gaussian form that is characteristic of the micro-range treatment.
  • the product of luminance by color gives a Gaussian-shaped section colored 703, which corresponds well to what is desired, that is to say a color whose intensity gradually increases from the edges of the line to its center, then descends on the other side in a symmetrical manner. This corresponds well to the thickening of the line to make it more visible, with a blurring on its edges allowing among other things, to erase the staircase effects.
  • the second function of the mixer consists in managing the overlay of the image elements in the background, by performing a clipping function, in particular in the case mentioned above where it is necessary to display a tone-on-tone color, by making highlight for example a white line on a white background.
  • the mixer performs the background product by the image.
  • the background is represented here by a rectangle 801 significantly wider than the image element 802.
  • FIG. 9 shows a block diagram of an exemplary embodiment of such a mixer.
  • the luminance and line color information are applied to linearization circuits 901, intended to compensate for the non-linear response of the matrix display, more particularly in the case of LCD type displays.
  • Min 902 The product between this luminance and line color data is produced by the Min 902 function. This function ensures that only the weakest data of the two channels are retained. This ensures the extinction of the sub-pixel if it does not correspond to the required color and a correct luminance level as a function of the luminance profile of the level fixed by the primary color. This saturates the display to always have a clearly visible image.
  • the two pieces of information are then applied to a multiplexer 903 controlled by the output of the MIN circuit. It delivers the line luminance information LT for a sub-pixel belonging to the edge of the smoothed line.
  • the background color information is also applied to a linearization circuit which makes it possible to obtain the background luminance LF, for a pixel belonging to a background element.
  • an averaging circuit 904 which receives both LT and
  • LS is the level of luminance coming out of the correlator
  • ⁇ 1 is a threshold fixed according to the content of the table of filters used so that the central pixels of the micro ranges have priority on the display in order to always see the line
  • ⁇ 2 is a fixed threshold so that a line overlay on a low level background maintains an optimal level of smoothing in order to be able to maintain the line profile:
  • a calculation function 907 makes it possible to obtain a threshold value intended for use by external circuits to allow an optimal overlay of the synthetic image thus processed in a video image coming from an external source.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
  • Liquid Crystal Display Device Control (AREA)
EP00927318A 1999-05-11 2000-05-05 Systeme de traitement de donnees pour affichage sur un ecran matriciel Withdrawn EP1181682A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9906000 1999-05-11
FR9906000A FR2793588B1 (fr) 1999-05-11 1999-05-11 Systeme de traitement de donnees pour affichage sur un ecran matriciel
PCT/FR2000/001232 WO2000068925A1 (fr) 1999-05-11 2000-05-05 Systeme de traitement de donnees pour affichage sur un ecran matriciel

Publications (1)

Publication Number Publication Date
EP1181682A1 true EP1181682A1 (fr) 2002-02-27

Family

ID=9545466

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00927318A Withdrawn EP1181682A1 (fr) 1999-05-11 2000-05-05 Systeme de traitement de donnees pour affichage sur un ecran matriciel

Country Status (6)

Country Link
EP (1) EP1181682A1 (enrdf_load_stackoverflow)
JP (1) JP4990437B2 (enrdf_load_stackoverflow)
FR (1) FR2793588B1 (enrdf_load_stackoverflow)
IL (1) IL146415A0 (enrdf_load_stackoverflow)
WO (1) WO2000068925A1 (enrdf_load_stackoverflow)
ZA (1) ZA200109265B (enrdf_load_stackoverflow)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4460958A (en) * 1981-01-26 1984-07-17 Rca Corporation Window-scanned memory
FR2619982B1 (fr) * 1987-08-28 1994-04-29 Thomson Csf Systeme de visualisation d'image couleur sur ecran matriciel
CA2024745C (en) * 1989-11-06 2002-08-06 William Ray Hancock Beamformer for matrix display
JPH0954576A (ja) * 1995-08-11 1997-02-25 Yamaha Corp 画像表示装置
JP2001257886A (ja) * 2000-03-09 2001-09-21 Canon Inc 画像データ処理装置および方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0068925A1 *

Also Published As

Publication number Publication date
JP4990437B2 (ja) 2012-08-01
WO2000068925A1 (fr) 2000-11-16
IL146415A0 (en) 2002-07-25
ZA200109265B (en) 2002-10-30
FR2793588A1 (fr) 2000-11-17
JP2002544549A (ja) 2002-12-24
FR2793588B1 (fr) 2002-03-15

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