EP1177641A1 - Ensemble circuit de conditionnement d'energie - Google Patents

Ensemble circuit de conditionnement d'energie

Info

Publication number
EP1177641A1
EP1177641A1 EP00930194A EP00930194A EP1177641A1 EP 1177641 A1 EP1177641 A1 EP 1177641A1 EP 00930194 A EP00930194 A EP 00930194A EP 00930194 A EP00930194 A EP 00930194A EP 1177641 A1 EP1177641 A1 EP 1177641A1
Authority
EP
European Patent Office
Prior art keywords
conductive
differential
ground
energy
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00930194A
Other languages
German (de)
English (en)
Other versions
EP1177641A4 (fr
Inventor
Anthony A. Anthony
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X2Y Attenuators LLC
Original Assignee
X2Y Attenuators LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X2Y Attenuators LLC filed Critical X2Y Attenuators LLC
Publication of EP1177641A1 publication Critical patent/EP1177641A1/fr
Publication of EP1177641A4 publication Critical patent/EP1177641A4/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021—Constructional details
    • H03H2001/0078—Constructional details comprising spiral inductor on a substrate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/42—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
    • H03H7/425—Balance-balance networks
    • H03H7/427—Common-mode filters
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • the invention includes the use of energy conditioning assemblies, pathway intersections and layered architectures such as those described and claimed in commonly owned U.S. Patent No. 5,909,350, U.S. Patent No. 6,018,448, and currently pending U.S. Patent Application, Serial No. 09/008,769, all incorporated herein by reference.
  • a series of preferred embodiments are directed to energy conditioning that occurs when unenergized elements are combined and electrified to act as part of a circuit that provides conditioned energy to an integrated circuit or any other active energy loads within electronic equipment or systems.
  • the present invention also provides electrical interference suppression and/or shielding for improved performance of active electronic components located within larger electronic systems.
  • Background of the Invention The majority of electronic equipment produced presently, and in particular computers, communication systems, military surveillance equipment, stereo and home entertainment equipment, televisions and other appliances include miniaturized components to perform new high speed functions and electrical interconnections which according to the mate ⁇ als from which they are made or their mere size are very susceptible to stray electrical energy created by electromagnetic interference or voltage transients occurring on electrical lines.
  • ESR causes the capacitor to dissipate power during high flowing ac currents.
  • the equivalent series inductance (ESL) of a capacitor is the inductance of the capacitor leads in series with the equivalent inductance of the capacitor plates.
  • An additional form of parasitic that goes beyond the component itself is stray capacitance which is attributed to the attachment of the capacitor element within an electrical circuit. Stray capacitors are formed when two conductors are in close proximity to each other and are not shorted together or screened by a Faraday shield. Stray capacitance usually occurs between parallel traces on a PC board or between traces/planes on opposite sides of a PC board. Stray capacitance can cause problems such as increased noise and decreased frequency response. Several other sources of electrical noise include cross talk and ground bounce.
  • a component carrier which receives either a thru-hole or surface mount differential and common mode filter and decoupler as disclosed in the above referenced, commonly owned U.S. patents and pending U.S. patent applications (hereinafter referred to as "differential and common mode filter” or "layered architecture").
  • One embodiment consists of a plate of insulating material, also referred to as a planar insulator, having a plurality of apertures for accepting the leads of a thru-hole differential and common mode filter.
  • a surface mount component carrier comprised of a disk of insulating material having at least two apertures.
  • the disk is substantially covered by a metalized or conductive ground surface and includes at least two conductive pads surrounding the apertures, and insulating bands which surround each conductive pad.
  • the insulating bands separate and electrically isolate the conductive pads from the metalized ground surface.
  • a surface mount component such as a differential and common mode filter, is positioned lengthwise between the two conductive pads and operably coupled to the carrier. Once the surface mount component is coupled to the carrier, the combination can be manipulated, either manually or through various types of automated equipment, without subjecting the surface mount component to mechanical and physical stresses normally associated with the handling of miniature components.
  • the carrier also provides the added benefit of improved shielding from electromagnetic interference and over voltage dissipation due to the surface area of the metalized ground surface.
  • Fig. 1 A is a perspective, exploded view of a thru-hole differential and common mode filter coupled to a portion of the thru-hole component carrier of the present invention
  • FIG. 1 B is a perspective, exploded view of a differential and common mode filter coupled to a portion of a carrier circuit
  • Fig. 2 is an elevational view in cross section of a single-sided surface mount component carrier of the present invention
  • Fig. 3 is a top plan view of the surface mount component carrier shown in Fig. 2
  • Fig. 4 is an elevational view in cross section of a double-sided surface mount component carrier of the present invention
  • Fig. 5 is a top plan view of the surface mount component carrier shown in Fig. 4
  • Fig. 6 is an elevational view in cross section of an alternate embodiment of a single-sided surface mount component carrier of the present invention
  • Fig. 7 is a top plan view of the surface mount component carrier shown in Fig. 6
  • FIG. 8 is an elevational view in cross section of an alternate embodiment of a double-sided surface mount component carrier of the present invention
  • Fig. 9 is a top plan view of the surface mount component carrier shown in Fig. 8
  • Fig. 10 is a partial perspective view of a further embodiment of a connector surface mount differential and common mode filter carrier of the present invention
  • Fig. 11 is a partial top plan view of the connector surface mount differential and common mode carrier shown in Fig. 10
  • Fig. 12A is a top plan view of a carrier energy conditioning circuit assembly of the present invention
  • Fig. 12B is a side elevational view of the carrier energy conditioning circuit assembly shown in Fig. 12A;
  • FIG. 13A is a top plan view of a carrier energy conditioning circuit assembly applied to a crystal base portion of a crystal component
  • Fig. 13B is a side elevational view of the carrier energy conditioning circuit assembly applied to a crystal base portion of a crystal component shown in Fig. 13A
  • Fig. 13C is a front elevational view of the carrier energy conditioning circuit assembly enclosed in a crystal component application shown in Fig 13B with a metal enclosure
  • Fig. 13D is a side elevational view of the carrier energy conditioning circuit assembly enclosed in a crystal component application shown in Fig. 13C
  • Fig. 14A is a top plan view of a carrier energy conditioning circuit assembly comprising a differential and common mode filter mounted on a single layer substrate carrier within an integrated circuit package
  • Fig. 14A is a top plan view of a carrier energy conditioning circuit assembly comprising a differential and common mode filter mounted on a single layer substrate carrier within an integrated circuit package
  • Fig. 14A is a top plan view of a carrier energy conditioning circuit assembly comprising
  • FIG. 14B is a top plan view of a single point ground area located beneath the differential and common mode filter in Fig. 14A;
  • Fig. 15 is a top plan view of a carrier energy conditioning circuit assembly 9 comprising a differential and common mode filter mounted transversely on a single layer substrate carrier within an integrated circuit package;
  • Fig. 16A is a top plan view of a two layer substrate carrier having a differential and common mode filter mounted to bus traces on a top surface of the carrier;
  • Fig. 16B is a front cross-sectional view of the two layer substrate carrier of Fig. 16A;
  • Fig. 16C is a side sectional view of the two layer substrate carrier of Fig.
  • Fig. 17A is a top plan view of a three layer substrate carrier having a differential and common mode filter mounted to power bus traces on a top surface of the carrier
  • Fig. 17B is a front cross-sectional view of the three layer substrate carrier of Fig. 17A
  • Fig. 17C is a side sectional view of the three layer substrate carrier of Fig. 17A
  • Fig. 17D is a front cross-sectional view of the three layer substrate carrier of Fig. 17A including a top potting layer
  • Fig. 17A is a top plan view of a three layer substrate carrier having a differential and common mode filter mounted to power bus traces on a top surface of the carrier
  • Fig. 17B is a front cross-sectional view of the three layer substrate carrier of Fig. 17A
  • Fig. 17C is a side sectional view of the three layer substrate carrier of Fig. 17A
  • Fig. 17D is a front cross-sectional view of the three layer substrate carrier of Fig. 17A including
  • FIG. 18 is a side sectional view of a multi-layer substrate carrier having a differential and common mode filter embedded on a layer within the substrate;
  • Fig. 19A is a top plan view of a shielded twisted pair feed through differential and common mode filter; and
  • Fig. 19B is a top plan view of the coplanar elements that comprise the shielded twisted pair feed through differential and common mode filter of Fig. 19A;
  • Fig. 19C and Fig. 19D are schematic representations of a shielded twisted pair feed through differential and common mode filter showing differential noise cancellation;
  • Fig. 19E and Fig. 19F are schematic representations of a shielded twisted pair feed through differential and common mode filter showing common mode noise cancellation;
  • 10 Fig. 19A is a top plan view of a shielded twisted pair feed through differential and common mode filter
  • Fig. 19B is a top plan view of the coplanar elements that comprise the shielded twisted pair feed through differential and common mode filter of Fig.
  • FIG. 20A is a top plan view of a carrier energy conditioning circuit assembly comprising a shielded twisted pair feed through differential and common mode filter embedded in a multi-layer substrate carrier within an integrated circuit package; and Fig. 20B is a front cross-sectional view of the integrated circuit package of Fig. 20A; and Fig 20C is a top plan view of the ground plane layer of the integrated circuit package of Fig. 20A; Fig. 21 is a top plan view of a carrier energy conditioning circuit assembly comprising a shielded twisted pair feed through differential and common mode filter mounted underneath a multi-layer substrate carrier within an integrated circuit package; and
  • Fig. 1A shows the present invention in its simplest form.
  • Component carrier 132 iiss s sh. own coupled with a differential and common mode filter 130 having thru-hole leads 140 for electrical coupling to carrier 132.
  • Differential and common mode filter 130 is disclosed in commonly owned U.S. Patent No. 5,909,350 (Serial No. 08/841 ,940); application Serial No. 09/008,769; and U.S. Patent No. 6,018,448 (Serial No. 09/056,379), incorporated herein by reference. Briefly, the structure of differential and common mode filter 130 will be described.
  • Filter 130 consists of a first electrode 136 and a second electrode 138 which are physically separated by and electrically isolated from each other by a plurality of ground layers 134 and by a dielectric medium.
  • the particular architecture creates a line-to-line capacitor and two line-to-ground capacitors which provide for differential and common mode filtering and decoupling.
  • component carrier 132 provides a physical support to which filter 130 is physically and electrically coupled.
  • the first and second electrodes 136 and 138 each have one or more conductive leads 140 which are inserted into apertures 148 of conductive pads 144. Each conductive pad 144 is electrically isolated from the conductive surface 142 of component carrier 132 by insulating bands 146.
  • component carrier 132 provides additional physical strength to differential and common mode filter 130 but it also acts as a conductive shield, which substantially improves the electrical characteristics of filter 130.
  • the plurality of common conductive electrodes or layers 134 are electrically coupled to one another and then electrically coupled to conductive surface 142 by any number of means known by those of ordinary skill in the art.
  • One common means of coupling is through the use of solder points 150 connecting portions of the common conductive layers 134 to conductive surface 142.
  • solder points 150 connecting portions of the common conductive layers 134 to conductive surface 142.
  • Fig. 1 B shows an alternate version of the present invention in its simplest form.
  • Fig. 1 B The difference in Fig. 1 B as compared to Fig. 1A is that the carrier 132' of Fig. 1 B has a pair of circuit traces 145A insulated from conductive surface 142A by insulating bands 146A.
  • First electrode 136 and second electrode 138 are each electrically connected through conductor 140A to a solder pad 144A on one of the circuit traces 145A and coupled thereto by solder 150A.
  • Common conductive layers 134 are electrically connected by conductor 140A to conductive surface 142A.
  • each embodiment can include one or more connections between the 12 common conductive layers 134 and conductive surface 142A.
  • Both embodiments shown in Figs. 1A and 1B disclose a layered architecture (differential and common mode filter 130) in combination with a conductive substrate (carrier 132) that comprises an energy conditioning circuit assembly (hereinafter "ECCA").
  • ECCA energy conditioning circuit assembly
  • Each embodiment of the ECCA receives and conditions energy when electrically coupled between an active load and an energy source.
  • the conditioning functions provided by the ECCA are facilitated, in part, by the physical and electrical connection of the common conductive electrodes (ground layers 134) of the layered architecture with an external conductive path provided by the conductive substrate.
  • the conductive substrate is positioned apart from the differentially energized electrodes of the layered architecture.
  • the common conductive electrodes alone or in combination with the conductive substrate are normally electrically coupled to a separate energy path from the energy path between first electrode or layer 136 and conductive area 142 ( or 142A) and second electrode or layer 138 and conductive area 142 (or 142A), at the same time.
  • the common conductive electrodes and/or the conductive substrate may be connected to a circuit ground or return, an isolated ground, a chassis ground, or earth ground.
  • the energy return path 13 could be any desired reference including a zero voltage reference or even a offset reference in either the positive or negative direction, as used for inverted digital logic for example.
  • ground will be used generally but is not intended to be limited to any one particular electrical reference point.
  • the ECCA When one or more pairs of differential electrodes (first and second electrodes 136 and 138 respectively) of the layered architecture are electrically connected to external energy pathways or planes, i.e., electrical connections to and from a power source and load, and energy is applied to the pathways, the ECCA performs simultaneous energy conditioning functions. These conditioning functions include but are not limited to filtering of common mode and differential mode noise, bypassing of noise to ground, circuit decoupling and/or transient voltage suppression or minimization. Depending upon the type of energy source and load, the ECCA may also perform primarily an energy conditioning function or simply a circuit decoupling function, however in many applications it will perform multiple functions as just described upon propagating energy, simultaneously. The ECCA can act as a system conduit for energy propagating along multiple external energy pathways.
  • Energy will also propagate within the layered architecture in a balanced manner from multiple directions 3 dimensionally; meaning the reactance of the propagated energy will be approximately balanced. Due to the unique arrangement of the ECCA, energy received and conditioned provides an active load with a defacto constant energy source, which can be drawn upon by the active load without detrimental voltage drops. The ECCA also effectively minimizes loop currents or unwanted emissions that would otherwise exist in the form of common mode noise coupled to energy 14 pathways or conductive planes. The ECCA also prevents radiation of common mode noise that would detrimentally influence the energy coupled to the loads serviced by the ECCA.
  • the common conductive electrodes of the layered architecture are electrically connected to the larger conductive area of the conductive substrate, the larger conductive area becomes an extension of the common conductive electrodes found within the layered architecture, and conversely, common conductive electrodes found within the layered architecture become an extension of the larger conductive area of the conductive substrate.
  • the differential pathways are coupled to an active load, for example the silicon wafer or active integrated circuit, the conductive substrate extension is in a position such that it nearly comes in contact with the differential conductive pathways containing energy that is propagating to and from a source and a load.
  • the common conductive layers also provide a physical barrier of separation interposed between differential conductive electrodes and at the same time, in an energized state, it also acts as a common electrostatic shield that functions between a dielectric medium to partially enveloping the differential conductors contained internally within the layered architecture of the ECCA.
  • the larger conductive area or extension provided to the common conductive electrodes within the layered architecture functions as an enveloping shield that decreases unwanted energy radiating from the differential electrodes that would otherwise detrimentally affect nearby energy propagating along the differentially phased opposite conductors.
  • the energized combination that makes up the ECCA provides efficient simultaneous conditioning and/or decoupling on portions of energy propagating across the internal energy pathways or planes that are servicing a load.
  • the parallel arrangement of the common conductive electrodes within the layered architecture and the extension into the same of the externally located conductive area provided by the conductive substrate also functions to minimize and/or suppress unwanted parasitics and emissions. Such emissions can radiate from or be received by portions of internal differential energy pathways as energy propagates along the internal energy pathways to an active load.
  • Portions of the energy radiated from the internal energy pathways that is trapped within the boundary formed by the layered architecture and the larger conductive area of the conductive substrate will be returned to its source.
  • the opposing differentially phased conductors within the layered architecture will also suppress or minimize electromagnetic emissions of portions of the propagating energy not contained elecrostatically by the common conductive pathways by utilizing the commonly know principals of inductive cancellation between closely positioned yet opposing, energy pathways.
  • Some or all of any undesirable energy (signals, noise, and/or transients) conditioned and/or decoupled by the ECCA will be contained, suppressed and/or bypassed to the common conductive electrodes of the layered architecture and the larger conductive area provided by the conductive substrate.
  • FIG. 2 A more specific embodiment of the present invention illustrated in Fig. 2 is surface mount component carrier 10 for maintaining a ceramic planar surface mount electrical component, such as a differential and common mode filter as is disclosed in commonly owned U.S. Patent No. 5,909,350 (Serial No. 08/841 ,940); application Serial No. 09/008,769; and U.S. Patent No. 6,018,448 (Serial No. 09/056,379), incorporated herein by reference.
  • Carrier 10 is a disk comprised of an insulator 14, such as ceramic, having at least two apertures 18.
  • Insulator 14 is covered by a conductive metalized ground surface 16, at least two conductive pads 24 surrounding apertures 18, and insulating bands 22 surrounding each conductive pad 24.
  • Insulator or “insulating material” may also be referred to as "planar insulator.”
  • Insulating bands 22 separate and electrically isolate conductive pads 24 from metalized ground surface 16.
  • the preferred embodiment of the invention is circular in shape with square insulating bands 22 surrounding partially rounded conductive pads 24.
  • Carrier 10 and its various elements can be formed into many different shapes and Applicant does not intend to limit the scope of the invention to the particular shapes shown in the drawings. Referring again to Fig.
  • metalized ground surface 16 covers a substantial portion of the top and sides of carrier 10.
  • Through-hole plating 20 covers the inner walls of aperture 18 and electrically couples to the corresponding conductive pad 24.
  • Through-hole plating 20 provides greater surface area for electrical coupling of conductors 34 to conductive pads 24 as the conductors 34 are disposed through apertures 18.
  • the configuration of metalized ground surface 16, insulating bands 22 and conductive pads 24 provide the necessary contacts for connecting a surface mount component, such as differential and common mode filter 12, to the upper surface of carrier 10, which in turn provides electrical connection between conductors 34 and surface mount component 12.
  • the surface mount components referred to, such as differential and common mode filter 12 are provided in standard surface mount packages which include a number of solder terminations for electrically coupling the device to external circuitry or in this case to carrier 10.
  • Filter 12 includes first differential electrode band 28 and second differential electrode band 30 extending from either end of filter 12. Extending from the center of filter 12 is at least one and more typically two, common ground conductive bands 26.
  • An insulated outer casing 32 electrically isolates first and second differential electrode bands 28 and 30 and common ground conductive bands 26 from one another.
  • a top plan view of a standard surface mount device as just described is shown in Fig. 11 as differential and common mode filter 104.
  • the filter 104 is comprised of first differential conductive band 116, second differential conductive band 118 and two common ground conductive bands 120.
  • Fig. 1A shows the present invention in its simplest form.
  • Component carrier 132 is shown coupled with a differential and common mode filter 130 having thru-hole leads 140 for electrical coupling to carrier 132.
  • Differential and common mode filter 130 is disclosed in commonly owned U.S. Patent No. 5,909,350 (Serial No. 08/841 ,940); application Serial No. 09/008,769; and U.S. Patent No. 6,018,448 (Serial No. 09/056,379), incorporated herein by reference. Briefly, the structure of differential and common mode filter 130 will be described.
  • Filter 130 consists of a first electrode 136 and a second electrode 138 which are separated by and electrically isolated from a plurality of ground layers 134 and each other by a dielectric medium.
  • the particular architecture creates a line-to-line capacitor and two line-to-ground capacitors which provide for differential and common mode filtering and decoupling.
  • component carrier 132 provides a physical support to which filter 130 is electrically coupled.
  • the first and second electrodes 136 and 138 each have conductive leads 140 which are inserted into apertures 148 of conductive pads 144. Each conductive pad 144 is electrically isolated from the conductive surface 142 of component carrier 132 by insulating bands 146.
  • component carrier 132 provides additional physical strength to differential and common mode filter 130 but it also acts as a ground shield which substantially improves the electrical characteristics of filter 130.
  • the plurality of ground layers 134 are electrically coupled to one another and then coupled to conductive surface 142 by any number of means known by those of ordinary skill in the art.
  • One common means of electrical coupling is through the use of solder 150 points connecting portions of the ground layers 134 to conductive surface 142.
  • One advantage to the relatively large conductive surface 142 of component carrier 132 is that if cracks 152 or electrical openings form on conductive surface 142 its shielding effect is not lost.
  • Fig. 1 B shows an alternate version of the present invention in its simplest form. The difference in Fig.
  • Fig. 1 B as compared to Fig. 1A is that the carrier 132' of Fig. 1 B has a pair of circuit traces 145A insulated from conductive surface 142A by insulating bands 146A.
  • First electrode 136 and second electrode 138 are each electrically connected through conductor 140A to a solder pad 144A on one of the circuit traces 145A and coupled thereto by solder 150A.
  • Ground layers 134 are electrically connected through conductor 140A to conductive surface 142A.
  • Both embodiments shown in Figs. 1A and 1 B disclose a layered architecture (differential and common mode filter 130) in combination with a conductive substrate (carrier 132) that comprises an energy conditioning circuit assembly (hereinafter "ECCA").
  • ECCA energy conditioning circuit assembly
  • the ECCA When the ECCA is coupled between an energy source and an active load, the ECCA simultaneously receives and conditions energy propagating to the load in a differentially balanced manner.
  • the ECCA of the present invention is disclosed in a plurality of embodiments, which will be described subsequently. Each embodiment of the ECCA simultaneously receives and conditions energy when coupled between an active load and an energy source.
  • the conditioning functions provided by the ECCA are facilitated, in part, by the electrical connection of the common conductive electrodes (ground layers 134) of the layered architecture with an external conductive path provided by the conductive substrate.
  • the conductive substrate is positioned apart from the differentially energized electrodes of the layered architecture.
  • the common conductive electrodes alone or in combination with the conductive substrate are normally electrically coupled to an energy return path, i.e., ground.
  • an energy return path i.e., ground.
  • the common conductive electrodes and/or the conductive substrate may be connected to a circuit ground or return, an isolated ground, a chassis ground, or earth ground.
  • the energy return path could be any desired reference including an offset reference in either the positive or negative direction, as used for inverted digital logic for example.
  • the term ground will be used generally but is not intended to be limited to any one particular electrical reference point.
  • first and second electrodes 136 and 138 respectively When one or more pairs of differential electrodes (first and second electrodes 136 and 138 respectively) of the layered architecture are electrically connected to external energy pathways or planes, i.e., electrical connections to and from a power source and load, and energy is applied to the pathways the ECCA simultaneously performs energy conditioning and decoupling. Depending upon the type of energy source and load, the ECCA may perform only energy conditioning or decoupling, although in many applications it will perform both upon propagating energy simultaneously. The ECCA can receive and source energy along multiple external energy pathways. Energy will also propagate within the layered architecture in a balanced manner, meaning the reactance of the propagated energy will be approximately equal.
  • the ECCA Due to the unique arrangement of the ECCA, energy received and conditioned provides an active load with a defacto constant energy source which can be drawn upon by the active load.
  • the ECCA also effectively minimizes loop currents that would otherwise exist in the energy pathways or planes coupled to the loads. Because the common conductive electrodes of the layered architecture are electrically connected to the larger conductive area of the conductive substrate, the larger conductive area becomes an extension of the common conductive electrodes found within the layered architecture.
  • an active load for example the silicon wafer of an integrated circuit, the conductive substrate will be positioned such that it nearly comes in contact with the active load thereby minimizing the distance of separation or loop area.
  • This close positioning relationship of the active load, the conductive 21 substrate, and the layered architecture minimizes the current loop path of the differentially energized electrodes, which are separated by dielectric medium.
  • the larger conductive area or extension provided to the common conductive electrodes functions as an enveloping shield that decreases electrostatic energy.
  • the combination that makes up the ECCA provides efficient simultaneous conditioning and/or decoupling on energy propagating across portions of the external energy pathways or planes.
  • the parallel arrangement of the common conductive electrodes within the layered architecture and the externally located conductive area provided by the conductive substrate also functions to cancel and/or suppress unwanted parasitics and electromagnetic emissions. Such emissions can radiate from or be received by portions of external differential energy pathways as energy propagates along the external energy pathways to an active load.
  • FIG. 2 shows filter 12 positioned upon the top surface of carrier 10 so that the common ground conductive bands 26 come in contact with the portion of the metalized ground surface 16 which separates both of the insulating bands 22 from one another. This is accomplished by positioning differential and common mode filter 12 lengthwise between the two conductive pads 24 such that first differential electrode band 28 is in contact with one of the two conductive pads 24 and second differential electrode band 30 comes in contact with the other conductive pad 24.
  • insulated outer casing 32 of filter 12 aligns with portions of insulating bands 22 thereby maintaining electrical isolation between the various conductive and electrode bands of filter 12.
  • First and second differential conductive bands 28 and 30 and the common ground conductive bands 26 consist of solder terminations found in typical surface mount devices.
  • filter 12 is positioned upon carrier 10 standard solder refiow methods are employed causing the solder terminations to refiow thereby electrically coupling and physically bonding filter 12 to carrier 10.
  • Customary solder refiow methods which can be used include infrared radiation (IR), vapor phase and hot air ovens or any other means which can be used to expose the solder to sufficiently elevated temperatures.
  • IR infrared radiation
  • vapor phase vapor phase
  • hot air ovens any other means which can be used to expose the solder to sufficiently elevated temperatures.
  • Component carrier 10 reduces mechanical and physical stresses such as shock, vibration and various thermal conditions which filter 12 would otherwise be subjected to and provides a complete ground shield for filter 12. Because carrier 10 has a greater surface area then filter 12 and a substantial portion of that surface area is covered by metalized ground surface 16, carrier 10 acts as a ground shield which absorbs and dissipates electromagnetic interference and over voltages. These added benefits improve the overall functional performance and characteristics of filter 12. Figs.
  • Carrier 40 is identical to carrier 10, as shown in Fig. 2, except that carrier 40 is double-sided and as a bottom surface which is substantially identical to the top surface.
  • This configuration allows two differential and common mode surface mount filters 12a and 12b to be mounted to the upper and lower surfaces of carrier 40.
  • metalized ground surface 16 covers substantial portions of the top, sides and bottom of carrier 40 providing a greater overall surface area. The increased surface area of metalized ground surface 16 imparts greater shielding characteristics in carrier 40 which absorb and dissipate electromagnetic interference.
  • both the top and bottom of carrier 40 include corresponding conductive pads 24 which are electrically connected to one another by thru-hole plating 20 which covers the inner walls of apertures 18.
  • Double-sided carrier 40 is also advantageous in that it allows for flexibility needed to meet electromagnetic interference (EMI) and surge protection requirements simultaneously through integration of different surface mount components on the same carrier substrate.
  • EMI electromagnetic interference
  • a differential and common mode filter could be coupled to the top of carrier 40 while a MOV device could be coupled on the bottom of carrier 40 effectively placing the filter and MOV devices in parallel to provide EMI and surge protection in one compact, durable package.
  • carrier 40 provides a rigid base for maintaining various electronic surface mount components, the components themselves are subjected to less physical stress during manufacturing processes which in turn increases yields and lowers manufacturing costs.
  • FIG. 5 shows a modified configuration of metalized ground surface 16, conductive pads 24 and insulating bands 22.
  • insulating bands 22 have been substantially increased such that the surface area of carrier 40 is substantially covered by insulation as opposed to a metalized ground surface.
  • This configuration can be used when decreased shield characteristics are desired or the particular interaction between carrier 40 and the surface mount component needs to be precisely controlled.
  • parasitic capacitance values must be maintained below a certain level.
  • the particular shapes of insulating bands 22, shown in Fig. 5, are not necessary. All that is required is that the surface area covered by metalized ground surface 16 be varied which in turn varies the electrical characteristics of double-sided carrier 40. It should also be noted that the surface pattern shown in Fig.
  • Figs. 6 through 9 illustrate further alternate embodiments of the single and double-sided carriers shown in Figs. 2 through 5.
  • single-sided carrier 50 is similar to carrier 10 of Fig.
  • carrier 50 includes a conductive core 38 imbedded within insulator 14 which is electrically coupled to metalized ground surface 16. As shown in Figs. 6 and 7, conductive core 38 abuts and comes in contact with metalized ground surface 16 along the sides of carrier 50.
  • a via 36 is disposed within the center of carrier 50 which provides an additional electrical connection between the metalized ground surface 16 which covers the top of carrier 50 and conductive core 38. Via 36 is a small aperture formed in the surface of carrier 50 which passes through insulator 14 and comes in contact with conductive core 38.
  • via 36 includes thru-hole plating which electrically connects conductive core 38 and metalized ground surface 16.
  • Fig. 7 shows the surface configuration for carrier 50 which is identical to that shown in Fig. 5 with the addition of via 36.
  • the surface configuration of carrier 50 can vary.
  • the surface configuration could be similar to that shown in Fig. 3 with the addition of via 36 disposed within its center.
  • the benefit to embedding conductive core 38 within insulator 14 and electrically connecting conductive core 38 to metalized ground surface 16 is that a greater surface area is provided for absorbing and dissipating electromagnetic interference and over voltages without an increase in the overall dimensions of carrier 50.
  • Figs. 8 and 9 disclose a further alternate embodiment of the present invention in double- sided carrier 60.
  • Carrier 60 is identical to carrier 50, shown in Figs. 6 and 7, except that it is double-sided as the embodiment shown in Fig.
  • connector carrier 100 is illustrated in Fig. 10.
  • the surface mount component carrier is directly incorporated within an electronic connector.
  • Connector carrier 100 is comprised of a metalized plastic base 1 12 having a plurality of apertures 98 disposed through base 112, each of which receives a connector pin 102. Although not shown, portions of each connector pin 102 extends through base 112 and out of the front 110 of connector carrier 100.
  • pins 102 extending from the front 110 of carrier 100 form a male connector which is then, in turn, received by a female connector as is known in the art.
  • a female connector which then receives male pins.
  • the particular embodiment of connector 100 shown in Fig. 10 is of a right angle connector in which the tips of pins 102 would be inserted within apertures in a printed circuit board. Pins 102 would then be soldered to the individual apertures or pads in the printed circuit board to provide electrical connection between pins 102 and any circuitry on the printed circuit board.
  • two insulating bands 106 and 107 are provided to electrically isolate each of the connector pins 102 from the metalized plastic base 112 which covers substantially all of the surface area of connector carrier 100. Referring to Fig. 11 , the relationship between insulating bands 106 and 107, metalized plastic base 112 and differential and common mode filter 104 will be explained in more detail. While only one example is shown, both insulating bands 106 and 107 include a plurality of conductive pads 108 which surround apertures 98. Conductive pads 108 are electrically coupled to connector pins 102 disposed through apertures 98.
  • Insulating bands 106 and 107 provide a non-conductive barrier between the conductive pads 108 and the metalized plastic base 112.
  • Surface mount components such as differential and common mode filter 104, are positioned between insulated bands 106 and 107 so that first differential conductive band 116 of filter 104 comes in contact with a portion of a conductive pad 108 and second differential conductive band 118 comes in contact with a portion of an opposite conductive pad 108.
  • Insulated outer casing 122 of filter 104 slightly overlaps onto each insulating band 106 and 107 and metalized plastic base 112 to maintain electrical isolation of first and second differential conductive bands 116 and 118 and metalized plastic base 112 of connector carrier 100.
  • each of the various conductive bands of filter 104 are comprised of solder terminations which, when subjected to known solder refiow methods, physically and electrically couple to any metallic surfaces which they come in contact thereby permanently coupling the surface mount components, i.e. filter 104, to connector carrier 100.
  • connector carrier 100 allows miniature, fragile surface mount components to be used without subjecting those components to increased physical stress which can cause damage to the components, lowering production yields and increasing overall production costs.
  • Metalized plastic base 112 also provides a large conductive surface area connected to the ground terminations of filter 104 improving the ground shield used to absorb and dissipate electromagnetic interference and over voltages.
  • the primary advantages are the additional physical strength the filter carriers provide to the differential and common mode filters and the increased shield and ground effects provided by the enlarged conductive surface areas coupled to the differential and common mode filters.
  • Figs. 12A and 12B show the carrier energy conditioning circuit assembly 400 which resulted from the combination of the previously described component carriers with the differential and common mode filter 12. Shown in Fig. 12A, differential and common mode filter 12 is placed upon conductive ground surface 402 making physical contact between conductive ground surface 402 and common ground conductive electrode bands 26.
  • First and second differential conductive bands 30 and 28 are placed upon insulation pads 408 with differential signal conductors 404 and 406 disposed through each insulation pad 408.
  • First differential electrode band 28 and first differential signal conductor 404 are then further coupled physically and electrically to each other through a well known means in the art such as solder 410.
  • second differential electrode band 30 and second differential signal conductor 406 are coupled physically and electrically to one another and common ground conductive electrode bands 26 are coupled physically and electrically to ground area 402.
  • the internal construction of differential and common mode filter 12 electrically 29 isolates differential signal conductor 404 and first differential electrode band 28 from second differential signal conductor 406 and second differential electrode band 30.
  • the internal construction of the differential and common mode filter 12 creates a capacitive element coupled between the first and second differential signal conductors 404 and 406 and creates two capacitive elements, one coupled between the first differential signal conductor 404 and the common conductive ground surface 402 and the other coupled between the other second differential signal conductor 406 and the common conductive ground surface 402. While this arrangement of line-to-line and line-to- ground filtering is occurring the first and second differential signal conductors 404 and 406 remain electrically isolated from one another. From Fig. 12B it can be seen that first and second differential electrode bands 28 and 30 are prevented from coming into direct physical contact with conductive ground surface 402 due to insulating pads 408 interposed between differential signal conductors 404 and 406 and the conductive ground surface 402.
  • the combination of the differential and common mode filter 12 with its capacitive elements coupled line-to-line between differential signal conductors 404 and 406 and line-to-ground between the differential signal conductors 404 and 406 and conductive ground surface 402 provides substantial attenuation and filtering of differential and common mode electrical noise. At the same time the combination also performs simultaneous differential line decoupling. Another benefit provided by the combination include mutual cancellation of magnetic fields generated between differential signal conductors 404 and 406. By connecting the common ground conductive electrode bands 26 to a large conductive ground surface 402, increased shielding of the ground plane is provided to differential and common mode filter 12 which further enhances the desired functional characteristics of differential and common mode filter 12.
  • differential and common mode filter 12 with the internal partial Faraday-like shields electrically connected to conductive ground surface 402 cause noise and coupling currents from different elements of carrier energy conditioning circuit assembly 400 to be contained at their source or to conductive ground surface 402 without affecting differential signal conductors 404 and 406 or other elements of carrier energy conditioning circuit assembly 400 when differential and common mode filter 12 is attached between differential signal conductors 404 and 406.
  • Carrier energy conditioning circuit assembly 400 reduces, and in some cases eliminates, forms of capacitor parasitics and stray capacitance between differential signal conductors 404 and 406 .
  • Differential and common mode filter 12 provides these benefits due to its internal, partial Faraday-like shields that almost envelope the internal differential electrodes of differential and common mode filter 12 which connect to ground conductive electrode bands 26. These benefits are significantly increased when the partial Faraday-like shields are electrically connected by ground conductive electrode bands 26 to conductive ground surface 402.
  • Figs. 13A - 13D show one application of carrier energy conditioning circuit assembly 400 used in conjunction with a crystal.
  • differential and common mode filter 12 is physically and electrically coupled between first and second differential signal conductors 404 and 406 and to ground conductive surface 402.
  • ground conductive surface 402 is comprised of the metal base of the crystal, which in turn is connected to a metal cover 415 shown in Figs.
  • First and second differential signal conductors 404 and 406 of carrier energy conditioning circuit assembly 400 are electrically isolated from ground conductive surface 402 by insulation pads 408.
  • Common ground conductive electrode bands 26 are electrically connected to ground conductive surface 402 using solder 410 or other similar means.
  • a ground conductor pin 414 is also attached or molded monolithically to conductive ground surface 402 by soldering, welding or casting. Ground conductor pin 414 allows for further connection of crystal component application 416 to a system ground (not shown).
  • the internal construction of the differential and common mode filter 12 creates a capacitive element coupled between the first and second differential signal conductors 404 and 406 and creates two capacitive elements, one coupled between the first differential signal conductor 404 and ground conductive surface 402 and the other coupled between the other second differential signal conductor 406 and ground conductive surface 402. While this arrangement of line-to-line and line-to- ground filtering is occurring the first and second differential signal conductors 404 and 406 remain electrically isolated from one another. From Fig. 13B it can be seen that first and second differential electrode bands 28 and 30 are prevented from coming into direct physical contact with ground conductive surface 402 due to insulating pads 408 interposed between differential signal conductors 404 and 406 and the ground conductive surface 402. Figs.
  • FIG. 13C and 13D show the final combination of crystal component assembly 416 and its metal housing 415 which provides an additional ground shield for the combination.
  • the carrier energy conditioning circuit assembly 400 shown in crystal component assembly 416 simultaneously filters and attenuates common mode and 32 differential mode electrical noise attributed to such circuitry including such noise found between differential electrical line conductors 404 and 406.
  • Crystal component assembly 416 can also substantially reduce and in some cases eliminate or prevent differential current flow, mutual inductive coupling such as cross talk and ground bounce between either differential electrical line conductor 404 and 406 and the common voltage reference located on ground conductive surface 402.
  • the carrier energy conditioning circuit assembly 400 also simultaneously provides mutual cancellation of opposing magnetic fields attributed to and existing between differential electrical line conductors 404 and 406.
  • carrier energy conditioning circuit assembly 400 complements the inherent, internal ground structure and internal shield structures that nearly envelope or surround each opposing electrode within differential and common mode filter 12 to substantially improve overall noise attenuation on differential signal conductors 404 and 406 that would otherwise affect and degrade the desired performance of crystal component application 416.
  • carrier energy conditioning circuit assembly 400 consist of differential and common mode filter and decoupler 12 as defined herein with a capacitive element coupled between the first and second differential signal conductors 404 and 406 and two capacitive elements, one coupled between the first differential signal conductor 404 and ground conductive surface 402 and the other coupled between the other second differential signal conductor 406 and ground conductive surface 402 while maintaining electrical isolation between the first and second differential signal conductors 404 and 406; at least two energized differential electrical line conductors; and a physical and electrical coupling of common ground conductive electrode bands 26 of differential and common mode filter 12 to ground conductive surface 402.
  • carrier energy conditioning circuit assembly 400 The various elements listed that make up carrier energy conditioning circuit assembly 400 are interconnected using solder 410, conductive epoxy 417 or other means well known in the art.
  • the carrier energy conditioning circuit assembly is created when a differential and common mode filter, of the type shown above or of variations incorporated by reference, is used in any application combination of the specific elements that can be assembled on, into or within an energized, electrical circuit system.
  • the addition of the differential and common mode filter to the existing circuit creates a unique electrical circuit system.
  • the electrical circuit system including the differential and common mode filter can be located on or in, but not limited to, a carrier, an interposer, a PCB, a connector, an IC package, a chip carrier, or a silicon die.
  • the electrical circuit system comprises an energy source or load energized through a minimum of one or more phased or oppositely phased or charged line conductor elements to receive conditioning. These can consist of single or mixed elements, such as, but not limited to, traces, vias, wires, conductors, or any other element that can be electrically charged.
  • the invention consists of a differential and common mode filter and decoupler connected internally within an integrated circuit in order to filter and protect the integrated circuit power bus. The invention functions without debilitating ground return EMI or parasitics returning back through the differential and common mode filter and decoupler, which would otherwise affect the integrated circuit. Other advantages are in the elimination of multiple external and/or internal decoupler capacitors that have been needed in the past.
  • the prior art has required decoupling capacitors both on the outside and inside of the integrated circuit package or substrate.
  • the present invention consisting of the differential and common mode filter and decoupler internally connected to the power bus lines of an integrated circuit makes up a single unit that handles and/or conditions all energy sources required by the load demands of an integrated circuit through a single point of conditioning.
  • the invention also provides a reference ground for all power and return lines, traces or conductors entering and leaving the integrated circuit package or substrate.
  • various differential and common mode filters are used in combination with a carrier substrate of the type used in an integrated circuit package such as, but not limited to, a digital signal processor or microprocessor, to form a carrier energy conditioning circuit assembly.
  • the substrate carrier is typically made of a conventional material such as, but not limited to, glass, ceramic, special thermoplastic, or any conventional material used in the electronics industry.
  • the carrier may have one or more layers in which a power bus, a return bus, and a ground plane are configured.
  • the ground plane is typically made of conventional trace material such as, but not limited to, gold, copper, conductive layering or doping, etc.
  • the ground plane may either be floating or electrically connected to the system ground, chassis ground, etc.
  • the combination of the layered architecture and carrier can dissipate and/or accept energy in a balanced manner from the circuit , acting as a central energy source or reservoir through multiple conductive pathways.
  • the differential and common mode filter can be attached to the carrier on top, on bottom, or imbedded within the carrier as discussed below.
  • Fig. 14A a top view of an integrated circuit 220 is shown.
  • the center area of integrated circuit package 220 is typically covered with a glob sealant or a substrate cover as is commonly used in the electronics industry, to electrically insulate and protect the integrated circuit components.
  • integrated circuit package 220 which comprises a novel substrate carrier 180 attached to a silicon die (not shown) of the integrated circuit that is mounted in a lead frame 221.
  • Carrier substrate 180 has a power bus trace 182, a return bus trace 184, and a ground plane 186 all attached in a single layer to a top surface of the carrier 180.
  • Bus traces 182 and 184 are shown in a concentric pattern on the top surface of the carrier 180. The concentricity of the bus traces 182 and 184 provide a cancellation of inductance due to the opposite current flow through the bus traces.
  • Bus traces 182 and 184 are shown in a concentric octagonal pattern.
  • a plurality of loads 188 are connected to traces 182 and 184 by bond wires 190, jumper wires, or other conventional interconnects used in the electronics industry.
  • the bond wire 190 lengths are kept as short as possible to reduce stray impedance.
  • Loads 188 are representative of internal loads of the integrated circuit 220 and comprise the various functions and devices supported by the integrated circuit. Loads 188 are typically connected by bond wires 190 to leads 223, which surround the perimeter of the integrated circuit 220. The loads 188 are symbols which are shown on the top surface of the lead frame for communication convenience.
  • Ground plane 186 comprises three regions; a ground trace 222 that is concentric with and in between bus traces 182 and 184, an outer ground area 224 that surrounds the outermost bus trace 184, and an inner ground area 226 that is surrounded by the innermost bus trace 182.
  • Ground trace 222 separates and provides some inductive cancellation, cross talk suppression, and line to line isolation of the bus traces 182 and 184.
  • bus traces 182, 184 are electrically separated from ground plane 186 by open areas on the surface of substrate carrier 180, which are generally concentric with the bus traces 182, 184.
  • each of bus traces 182 and 184 have a predetermined space of physical separation between them.
  • the integrated circuit package is designed such that multiple power entry points are reduced to one pair of power entry pins 82 and 83 which are connected to the traces 182, 184 by bond wires 190 or other conventional interconnects.
  • Differential and common mode filter 200 is located in a predetermined position as close as possible to power entry pins 82 and 83 which also corresponds to the predetermined space of 37 physical separation between traces 182 and 184.
  • the single power entry portal represented by pins 82 and 83 and the proximity of the filter 200 to the power entry portal reduces the noise that can enter or exit the integrated circuit and interfere with circuitry both internal or external to the integrated circuit package.
  • Ground areas 222, 224, and 226 are interconnected by a single point ground area 228 (see Fig. 14B) which is located directly beneath the differential and common mode filter 200.
  • the ground layer 186 of the carrier substrate 180 in combination with the positioning of the filter 200 in proximity to the power entry pins 82, 83 results in isolation of noise generated by the integrated circuit package 220 from the external circuitry such as, but not limited to, a printed circuit board.
  • Differential and common mode filter 200 comprises first differential electrode bands 202, second differential electrode bands 206, and common ground conductive bands 204, all separated from each other by insulated outer casing 208.
  • the filter 200 is oriented on the carrier 180 such that the first differential electrode bands 202 and the second differential electrode bands 206 can be attached to the ends of the traces 182 and 184 to connect the individual traces and complete the circuit path. Continuity of traces 182 and 184 reduces reflections and ESL.
  • Common ground conductive bands 204 are electrically connected to the ground plane 186 through single point ground area 228 shown in Fig. 14B.
  • connection of the common ground conductive bands 204 and the differential electrode bands 202 and 206 can be accomplished using industry standard means such as solder, springs, etc., as previously discussed herein.
  • the alignment of filter 200 in parallel with the loads and the arrangement of the single layer carrier substrate 180 results in improved decoupling performance.
  • Fig. 15 generally the same top view of an integrated circuit 220 is shown, except that the orientation of filter 200 is rotated 90 degrees. This rotation requires minor modifications related to the mounting of the filter 200, and the location of differential electrode bands 202 and 206.
  • the differential electrode bands 202 and 206 are now on the same longitudinal side of the filter 200, respectively, instead of opposite sides as shown in Fig. 14A.
  • the common ground conductive bands 204 are attached to a single point ground area (not shown) underneath the filter 200 which connects the ground areas 222, 224, and 226 to form ground plane 186 in a similar manner as described for the previous embodiment.
  • carriers 180, 280 should be at least the size of the integrated circuit 220 it is covering so as not to allow sneak currents to couple back on the floating image reference created by the energized energy conditioning circuit assembly.
  • the power bus 182, return bus 184 and ground plane 186 can be imbedded in the carrier substrate on different levels. Referring now to Fig.
  • a top plan view of a carrier substrate 280 is shown having a power bus trace 182 and a return bus trace 184 attached to a top surface thereof.
  • a ground plane 186 is attached to a bottom surface of the carrier 280 as shown in a front cross-sectional view in Fig. 16B and side cross-sectional view Fig. 16C.
  • a plurality of loads 188 are connected to traces 182 and 184 by bond wires 190, or other conventional interconnects used in the electronics industry.
  • the loads 188 are internal microprocessor and/or integrated circuit loads representing the various functions and devices supported by the microprocessor and/or integrated circuits, and are typically connected thereto by bond wires attached to leads, which surround the perimeter of the integrated circuit (not shown).
  • the loads 188 are shown as symbols on the top surface of the carrier for ease of understanding.
  • the traces 182 and 184 are shown in a concentric pattern on the top surface of the carrier 280.
  • the concentricity of the traces 182 and 184 provide a cancellation of inductance due to the opposite current flow through the bus traces, as previously discussed.
  • differential and common mode filter 200 is located in a predetermined position on substrate carrier 280 as close as possible to power entry pins 82 and 83 and at a predetermined space of physical separation between each of the traces 182 and 184.
  • the single power entry portal represented by pins 82 and 83 and the proximity of the filter 200 to the power entry portal reduces the amount of noise that can enter or exit the integrated circuit and interfere with the circuitry, both internal and external to the integrated circuit package.
  • Differential and common mode filter 200 is oriented on the carrier 280 such that the first differential electrode bands 202 and the second differentia! electrode bands 206 can be attached to the ends of the traces 182 and 184 to connect the individual traces and complete the circuit path.
  • the common ground conductive bands 204 are electrically connected to the ground plane 186 by vias 192 as shown in Figs. 16B and 16C.
  • Via 192 is a small aperture formed in the surface of carrier 280, which is disposed through the body of carrier 280 to provide an electrical connection to ground plane 186 on the bottom surface of carrier 280.
  • via 192 includes thru-hole plating to provide the electrical connection.
  • the connection of the common ground conductive bands 204 and the differential electrode bands 202 and 206 can be accomplished using industry standard means such as solder, springs, etc., as previously discussed above.
  • carrier 280 also includes an insulation layer 194 attached underneath ground plane 186. Insulation layer 194 can be made of any predetermined insulating material, such as that of the carrier 280, or of a non-conductive epoxy.
  • bus traces 182 and 184 are on different layers of the substrate carrier 380.
  • a top plan view of carrier substrate 380 is shown having power bus trace 182 attached to a top surface thereof.
  • a return bus trace 184 is shown embedded within the carrier substrate 380 at a second layer, as best shown in Figs. 17B and 17C.
  • a ground plane 186 is shown embedded within the carrier substrate 380 at a third layer below the second layer.
  • An insulation layer 194 is optionally attached to a bottom surface of the carrier 380.
  • a plurality of loads 188 are connected to power bus trace 182 by bond wires 190.
  • the loads 188 are also connected by bond wires 190 to vias 196 which provide an electrical connection to the imbedded return bus trace 184 on the second layer as shown in Figs. 17B and 17C. Since the bus traces 182 and 184 are on different layers, the traces are aligned directly over top of each other to provide enhanced cancellation of inductance due to the opposite current flow through the bus traces which are the same size, shape, and length.
  • filter 200 is attached to the top surface of the carrier 380 in the same manner as described in relation to Fig.
  • the vias 196 are offset from the return bus 184.
  • the vias 196 are electrically connected to return bus 184 by electrical extension connectors (not shown) positioned between the return bus 184 and via 196.
  • the offset allows the busses 182 and 184 to directly lie over top of each other on different levels without having the via 196 of the return bus 184 coming straight up through the carrier 380 and into the power bus 182.
  • power entry pin 82 is also electrically connected to return bus 184 through a bond wire 190 connected to a via 196 that extends down through the carrier to return bus 184.
  • insulation layer 194 is attached on the bottom surface of carrier 380 to prevent electrical connection to the silicon die when the carrier 380 is assembled onto other components within the integrated circuit package (not shown).
  • Fig. 17D shows a cross-sectional view similar to Fig. 17B that also shows potting layer 187 over the top surface of carrier 380.
  • filter 200 is embedded on a second layer within the substrate carrier 480.
  • First and second differential electrode bands 202 and 206 of filter 200 are connected to power bus 182 on a first layer (on the top surface of the carrier 480) and return bus 184 on a fourth layer, respectively, by vias 196 extending through carrier 480.
  • Common ground conductive band 204 of filter 200 is connected to the ground plane layer 186 by vias 192.
  • Loads 188 are connected to the power bus 182 by bond wires 190 in the same manner as in previous embodiments.
  • the ground plane 186 is between the power bus trace 182 and the return bus trace 184.
  • Vias 196 from the filter 200 and the 42 loads 188 must extend through apertures in the ground plane 186 to electrically connect to the return bus trace 184.
  • the vias 196 are electrically insulated from the ground plane 186 by insulating band 208 surrounding the interior surface of the apertures of the ground plane 186.
  • bus traces 182 and 184 are on different layers and are aligned directly over top of each other to provide enhanced cancellation of inductance due to the opposite current flow through the bus traces which are the same size, shape, and length.
  • the differential and common mode filter has been presented in many variations both above and in commonly owned patents and patent applications, previously incorporated herein by reference.
  • a further embodiment of the present invention utilizes a variation of the filter previously discussed. Shielded twisted pair feed through differential and common mode filter 300 is shown in Fig. 19A.
  • first differential electrode bands 302A, 302B and second differential electrode bands 306A, 306B which are located diagonally from each other, respectively.
  • Common ground conductive bands 304 are separated from first and second differential electrode bands 302 and 306 by insulating material 308 as in the previous filter embodiments.
  • Shielded twisted pair feed through differential and common mode filter 300 comprises a minimum of a first and second differential electrode plate 312 and 316, respectively, and a minimum of three common ground conductive plates 314 as shown in Fig. 19B.
  • the plates 312, 314, and 316 are stacked and insulated from each other by material 308 as in the previous filter embodiments. Referring now to Figs.
  • FIG. 19C and 19D show schematic representations of shielded twisted pair feed through differential and common mode filter 300 and how it is used to eliminate differential noise.
  • Current I is shown flowing in opposing directions through first and second differential electrode bands 302A and 306B, crossing over each other, and flowing out through first and second differential electrode bands 302B and 306A.
  • the crossover point of the current I acts as a line to line capacitor while the common conductive ground plate 314 provides line to ground capacitors on either side of the crossover point.
  • the filter 300 is depicted as coplanar plates 312, 314, and 316, with electrode plates 312, 316, each sandwiched by common ground conductive plates 314 in a Faraday cage configuration.
  • the current I is shown flowing in opposite directions through the differential electrode plates.
  • Figs. 19E and 19F show schematic representations of shielded twisted pair feed through differential and common mode filter 300 and how it is used to eliminate common mode noise.
  • Current I is shown flowing in the same directions through first and second differential electrode bands 302A and 306A, crossing over each other, and flowing out through first and second differential electrode bands 302B and 306B.
  • the crossover point of the current I acts as a line to line capacitor while the common conductive ground plate 314 provides line to ground capacitors on either side of the crossover point.
  • Fig. 19E and 19F show schematic representations of shielded twisted pair feed through differential and common mode filter 300 and how it is used to eliminate common mode noise.
  • Current I is shown flowing in the same directions through first and second differential electrode bands 302A and 306A, crossing over each other, and flowing out through first and second differential electrode bands 302B and 306B.
  • the crossover point of the current I acts as a line to line capacitor while the common conductive ground plate 314 provides line to ground capacitors on either side of the
  • the filter 300 is again depicted as coplanar plates 312, 314, and 316, with electrode plates 312, 316, each sandwiched by common ground conductive plates 314 in a Faraday cage configuration.
  • the current I is shown flowing in the same direction through the differential electrode plates.
  • the common ground conductive plates 314 are electrically interconnected, but insulated from the differential electrodes as has been disclosed in filter embodiments previously incorporated by reference herein.
  • the shielded twisted pair feed through differential and common mode filter 300 is shown embedded within an integrated circuit package 320.
  • FIG. 20A shows a top plan view of an integrated circuit package 320 with a top insulating layer 322 removed to reveal power bus trace 324 and return bus trace 326 servicing internal loads 188 through bond wires 190 which are connected to leads 319 surrounding the perimeter of the integrated circuit package 320.
  • the bus traces 324, 326 are shown as concentric squares which provide a cancellation of inductance due to the opposite current flow through the bus traces. Note that the traces 324, 326 are connected to vias 196 at the center of the integrated circuit 320 in a manner that the connecting via 196 to each respective trace 324, 326 are positioned diagonally from each other for connection to shielded twisted pair feed through differential and common mode filter 300.
  • a cross-sectional view shows shielded twisted pair feed through differential and common mode filter 300 embedded within the integrated circuit 320 and positioned on ground plane 328 at a second level and connected to the bus 45 traces by vias 196 which extend vertically down from the bus trace level, through ground plane 328 to the bottom surface of the integrated circuit 320.
  • the vias 196 are electrically insulated from the ground plane by insulation 330 as best shown in Fig. 20C.
  • the integrated circuit package is designed such that multiple power entry points are reduced to one pair of power entry pins (not shown).
  • the shielded twisted pair feed through differential and common mode filter 300 is located in a predetermined position as close as possible to the power entry pins which also corresponds to the predetermined space of physical separation between traces 324 and 326, which in this example is shown at the center of the integrated circuit 320, although it is not limited to a particular location.
  • the single power entry portal and the proximity of shielded twisted pair feed through differential and common mode filter 300 to the power entry portal reduces the amount of noise that can enter or exit the integrated circuit 320 and interfere with the remaining circuitry, both internal or external to the integrated circuit package.
  • the ground plane is also shown with vias 332 extending downward from the ground plane 328 to the bottom surface of the integrated circuit 320.
  • the vias 332 enable the ground plane 328 to be connected to external ground (not shown) if needed for a particular application.
  • Vias 196 and vias 332 are connected by wire bonds or other conventional interconnects (not shown) to their respective external connections.
  • Another related embodiment is shown in a cross-sectional view in Fig. 21. The main difference between this embodiment and the embodiment shown in Figs. 20A-20C is that shielded twisted pair feed through differential and common mode filter 300 is attached to the bottom of integrated circuit package 320 mounted on a printed circuit 46 board 334. Substrate cover 336 is shown displaced from the integrated circuit 320 to reveal internal loads 188.
  • the bottom of the integrated circuit includes a ground substrate layer 338, which is electrically connected to ground plane 340 on printed circuit board 334 through ball grids 342 or other conventional interconnects and vias 344 extending through printed circuit board 334.
  • Common ground conductive bands (not shown) of shielded twisted pair feed through differential and common mode filter 300 are attached to ground substrate layer 338 by solder or other conventional means.
  • Bus traces 324, 326 are connected to differential electrode bands (not shown) of shielded twisted pair feed through differential and common mode filter 300 by vias 196. Although not completely shown, both the vias 196 and the differential electrode band attachments are electrically insulated from ground substrate layer 338 by insulation 330.
  • Interconnects 346 and 348 extend downward from vias 196 and are connected to a single power entry portal (not shown) serving the integrated circuit package 320. It should also be evident that using the differential and common mode filters, as compared to the labor intensive aspects of combining discrete components found in the prior art, provides an easy and cost effective method of manufacturing. Because connections only need to be made to either end of electrical conductors to provide a differential mode coupling capacitor and two common mode decoupling capacitors, time and space are saved. As can be seen, many different applications of the differential and common mode filter architecture are possible and review of several features universal to all the embodiments must be noted.
  • the material having predetermined electrical properties may be one of a number in any of the embodiments including but not limited to dielectric material, metal oxide varistor material, ferrite material and other more exotic substances such as Mylar film or sintered polycrystalline.
  • the combination of common ground plates and electrode plates creates a plurality of capacitors to form a line-to-line differential coupling capacitor between and two line- to-ground decoupling capacitors from a pair of electrical conductors.
  • the material having electrical properties will vary the capacitance values and/or add additional features such as over-voltage and surge protection or increased inductance, resistance, or a combination of all the above.
  • the number of plates, both common conductive and electrode can be multiplied to create a number of capacitive elements in parallel which thereby add to create increased capacitance values.
  • additional common ground conductive plates surrounding the combination of a center conductive plate and a plurality of conductive electrodes may be employed to provide an increased inherent ground and surge dissipation area and a Faraday cage-like structure in all embodiments. Additional common ground conductive plates can be employed with any of the embodiments shown and is fully contemplated by Applicant.
  • the differential and common mode filter structure has the ability to balance its own electrical characteristics and to effect a cancellation of internal inductance attributed to it's structure thus preventing performance disruption of the electrical circuit system line conductors.
  • the portability of the differential and common mode filter allows insertion into sub-electrical systems that mate with main electrical circuit system such as, but not limited to, integrated circuit carriers, integrated chip modules, system interposers, connector embodiments or any other sub-electrical systems that are subsequently mated to larger or more sophisticated electrical circuit systems.
  • main electrical circuit system such as, but not limited to, integrated circuit carriers, integrated chip modules, system interposers, connector embodiments or any other sub-electrical systems that are subsequently mated to larger or more sophisticated electrical circuit systems.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structure Of Printed Boards (AREA)
  • Filters And Equalizers (AREA)

Abstract

L'invention concerne un support (132) de composant constitué par une plaque de matériau isolant pourvue d'une pluralité d'ouvertures (140) servant à laisser passer les conducteurs d'un filtre différentiel et de mode commun (130). Dans un autre mode de réalisation, un support (10) de composant montable en surface est constitué par un disque (16) de matériau isolant comportant une pluralité d'ouvertures (24). Plusieurs autres modes de réalisation intègrent également le même concept de support se présentant soit de façon indépendante, soit encastré à l'intérieur de connecteurs électroniques. La configuration générale et les caractéristiques électriques de ces concepts s'appliquent également à un ensemble circuit de conditionnement d'énergie basé sur la combinaison de filtres différentiels et de mode commun avec des supports de composants optimisés pour ce type de filtres. Ces supports, dans leurs différents modes de réalisation, permettent d'obtenir une résistance physique améliorée, de protéger des filtres différentiels et de mode commun et, de ce fait, d'améliorer sensiblement les caractéristiques électriques de ces filtres, étant donné l'augmentation du blindage produite par ces supports. Des modes de réalisation de cet ensemble circuit de conditionnement d'énergie comprennent des architectures de circuits intégrés pour filtres différentiels et de mode commun couplés au bus de puissance d'un circuit intégré.
EP00930194A 1999-04-28 2000-04-28 Ensemble circuit de conditionnement d'energie Withdrawn EP1177641A4 (fr)

Applications Claiming Priority (17)

Application Number Priority Date Filing Date Title
US13138699P 1999-04-28 1999-04-28
US131386P 1999-04-28
US13554299P 1999-05-24 1999-05-24
US135542P 1999-05-24
US13645199P 1999-05-28 1999-05-28
US136451P 1999-05-28
US13918299P 1999-06-15 1999-06-15
US139182P 1999-06-15
US14698799P 1999-08-03 1999-08-03
US146987P 1999-08-03
US16503599P 1999-11-12 1999-11-12
US165035P 1999-11-12
US18010100P 2000-02-03 2000-02-03
US180101P 2000-02-03
US18532000P 2000-02-28 2000-02-28
US185320P 2000-02-28
PCT/US2000/011409 WO2000065740A1 (fr) 1999-04-28 2000-04-28 Ensemble circuit de conditionnement d'energie

Publications (2)

Publication Number Publication Date
EP1177641A1 true EP1177641A1 (fr) 2002-02-06
EP1177641A4 EP1177641A4 (fr) 2003-04-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP00930194A Withdrawn EP1177641A4 (fr) 1999-04-28 2000-04-28 Ensemble circuit de conditionnement d'energie

Country Status (7)

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EP (1) EP1177641A4 (fr)
JP (1) JP2002543661A (fr)
KR (1) KR100427111B1 (fr)
CN (1) CN1223107C (fr)
AU (1) AU4805700A (fr)
HK (1) HK1045915A1 (fr)
WO (1) WO2000065740A1 (fr)

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US7321485B2 (en) 1997-04-08 2008-01-22 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
US7336468B2 (en) 1997-04-08 2008-02-26 X2Y Attenuators, Llc Arrangement for energy conditioning
US20020122286A1 (en) * 2000-10-17 2002-09-05 X2Y Attenuators, Llc Energy pathway arrangement
US7356050B2 (en) 2003-12-17 2008-04-08 Siemens Aktiengesellschaft System for transmission of data on a bus
US7675729B2 (en) * 2003-12-22 2010-03-09 X2Y Attenuators, Llc Internally shielded energy conditioner
KR20070107746A (ko) 2005-03-01 2007-11-07 엑스2와이 어테뉴에이터스, 엘.엘.씨 내부 중첩된 조절기
US10363425B2 (en) * 2015-06-01 2019-07-30 Avx Corporation Discrete cofired feedthrough filter for medical implanted devices
CN106527600A (zh) * 2016-12-21 2017-03-22 北京灵铱科技有限公司 一种调节滑块式三屏显示设备
CN108665944A (zh) * 2018-04-19 2018-10-16 常州利明屏蔽有限公司 MR屏蔽室专用集成pp板
CN113556872A (zh) * 2021-08-23 2021-10-26 环旭(深圳)电子科创有限公司 设有阻抗敏感电子元件的多层电路板及其制造方法

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Also Published As

Publication number Publication date
AU4805700A (en) 2000-11-10
HK1045915A1 (zh) 2002-12-13
CN1223107C (zh) 2005-10-12
WO2000065740A1 (fr) 2000-11-02
KR20020007391A (ko) 2002-01-26
KR100427111B1 (ko) 2004-04-17
EP1177641A4 (fr) 2003-04-23
JP2002543661A (ja) 2002-12-17
CN1373938A (zh) 2002-10-09

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