EP1174839A2 - Dispositif anti-sabotage et méthode pour la détection de sabotage dans un composant - Google Patents

Dispositif anti-sabotage et méthode pour la détection de sabotage dans un composant Download PDF

Info

Publication number
EP1174839A2
EP1174839A2 EP01109800A EP01109800A EP1174839A2 EP 1174839 A2 EP1174839 A2 EP 1174839A2 EP 01109800 A EP01109800 A EP 01109800A EP 01109800 A EP01109800 A EP 01109800A EP 1174839 A2 EP1174839 A2 EP 1174839A2
Authority
EP
European Patent Office
Prior art keywords
signal
detection
casing
tamper
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP01109800A
Other languages
German (de)
English (en)
Other versions
EP1174839A3 (fr
EP1174839B1 (fr
Inventor
Piero Camillo Gusi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vimar SpA
Original Assignee
Vimar SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vimar SpA filed Critical Vimar SpA
Priority to SI200130494T priority Critical patent/SI1174839T1/sl
Publication of EP1174839A2 publication Critical patent/EP1174839A2/fr
Publication of EP1174839A3 publication Critical patent/EP1174839A3/fr
Application granted granted Critical
Publication of EP1174839B1 publication Critical patent/EP1174839B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B29/00—Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
    • G08B29/02—Monitoring continuously signalling or alarm systems
    • G08B29/04—Monitoring of the detection circuits
    • G08B29/046—Monitoring of the detection circuits prevention of tampering with detection circuits

Definitions

  • the present invention refers to an anti-tamper device and related method for the detection of tampering with a component.
  • the invention is intended in particular for devices for the protection of sensors in surveillance systems, such as anti-burglar or anti-intrusion systems.
  • a known solution provides for the use of magnetically operated devices consisting of a fixed part, integral with the recessed casing, housing a permanent magnet.
  • the module which is the component of the security system, is provided with a reed relay kept in the closed position by the magnetic field generated by the magnet mounted on the fixed part integral with the casing.
  • Movement of the component from the position in which it is mounted causes the relay to move away from the magnet, with a consequent opening of the contact of the relay and production of an alarm signal.
  • anti-tamper devices of the optoelectronic type comprising a transmitter to generate a signal that is propagated inside the casing and a detector to detect said signal and any changes in the signal due to tampering.
  • the transmitter and the detector are mounted on the outer rear wall of the module, consequently the detector detects the signal emitted by the transmitter and reflected by the rear wall of the casing.
  • the transmitter and the detector Being disposed inside the casing containing the electrical modules, the transmitter and the detector can be damaged, for example by the wires passing inside the casing.
  • Such devices in any case have the drawback of detecting the signal inside the casing; consequently their operation is closely influenced by the configuration and the structure of the casing.
  • the casings and in particular their rear walls can be made of various materials, for example plastics having different surface or chromatic characteristics. Or else the casing may have been accidentally smeared, before or after flush mounting on the wall, with various materials such as plaster, paint and the like.
  • the depth of embedding of the casing in the wall too can vary from one instance to another. Since the component is generally supported by the front plate of the casing, applied flush with the wall, it can be situated at different distances with respect to the rear wall of the casing.
  • the wires for connection of the component in question there are usually the wires for connection of the component in question, any wires of other components present in the casing, and possibly wires passing through the casing but not belonging to any of the components.
  • An object of the present invention is to overcome the above-mentioned drawbacks by providing an anti-tamper device that is efficient and safe irrespective of the type, configuration and structure of the casing inside which the component that must not be tampered with is mounted.
  • Another object of the present invention is to provide such an anti-tamper device that is economical and simple to make.
  • Another object of the present invention is to provide a method for detection of tampering with components that is efficient and immune from disturbances due to the configuration of the inside the casing in which the components are housed.
  • the anti-tamper device according to the invention is suitable to be applied to components inserted like modules in a casing.
  • Said anti-tamper device provides a transmitter or generator to transmit a signal inside the casing, a receiver or detector to detect the signal that is propagated in the casing and alarm means which, on the basis of the signal detected, signal any tampering with the component.
  • the peculiarity of the anti-tamper device according to the invention is due to the fact that the signal which is propagated inside the casing is detected inside the body of the component. Consequently said signal is better protected from disturbances due to the shape of the casing and the presence of wires inside the casing.
  • the transmitter and the receiver are advantageously positioned inside the body of the component. In this manner the transmitter and the detector are protected against any breakage or damage caused by wires disposed inside the casing that can interfere therewith or from knocking against the walls of the casing during assembly.
  • the transmitter and the detector have greater immunity against electrostatic discharge generated by the movement of the wires inside the casing.
  • Another advantage of the anti-tamper device according to the invention is represented by the fact that the alarm signal that tampering has occurred is obtained by means of a control unit in which software is provided that implements a comparison of the signal detected with a threshold signal that is continuously updated.
  • Said software-implemented comparison system is more flexible and reliable than the comparison systems of known anti-tamper devices that are developed by means of hardware comparators.
  • Figure 1 shows as a whole a casing 1 of the type currently used in domestic and industrial electrical systems.
  • the casing 1 is intended to be flush-mounted in a wall with its open front side 2 facing toward the outside of the wall.
  • the casing 1 is closed by means of a cover plate 3 comprising a plurality of apertures 4 forming respective seats for mounting of the modules 5.
  • the modules 5 consist of a shell 8 that encloses a component 9, such as, for example, a switch, an electrical socket, a sensor etc.
  • a sensor is considered as a component.
  • the outer surface of the plate 3 is generally closed by a cover element 6 (the so-called “switch plate") provided with respective apertures 7 in alignment with the seats 4 of the plate 3 provided for mounting the modules 5 that are to be housed in the casing 1.
  • switch plate the so-called "switch plate”
  • the anti-tamper device designated as a whole with reference numeral 10 is mounted inside the shell 8 of the module 5 that contains the component 9.
  • the anti-tamper device 10 consists of an optoelectronic pair comprising an emitter 11 and a receiver 12.
  • the emitter 11 emits an optical radiation, typically in the infrared range, that is propagated inside the casing 1.
  • the emitter 11 can be a LED, for example, that emits in the infrared or ultraviolet range.
  • the receiver 12, which detects at least a fraction of the radiation generated by the emitter 11, can be a photodetector, such as a photodiode, with spectral characteristics complementary to those of the emitter 11.
  • the radiation generated by the emitter 11 diffuses inside the casing 1 and is reflected and diffused according to a somewhat complex propagation line distribution determined by a combination of factors such as the type and shape of the casing, the possible presence of numerous sources of diffusion/reflection such as wires, etc.
  • the intensity of the radiation detected by the receiver 12 thus depends on the sum of these factors.
  • one or more windows or apertures 13 are situated at least in the rear wall 14 of the shell 8 of the module.
  • the windows 13 can be left open or covered with a light-transparent material.
  • the windows 13 influence the propagation of the radiation which, from the inside of the casing 1, passes into the shell 8 of the module 5. Thanks to the action of these windows 13, a stationary wave which is detected by the receiver 12 is generated inside the shell 8. Said wave detected by the receiver 12 is used to detect possible tampering with the module 5 or the casing 1.
  • the anti-tamper device 1 When it is installed, the anti-tamper device 1 is set according to the conditions of propagation of the radiation that goes from the emitter 11 to the receiver 12, in the specific situation of installation.
  • any change in said conditions of propagation of the radiation which can be induced by even a minimal movement of the component 9, such as tampering or total removal, for example, causes a change in the signal detected by the detector 12. Consequently the detector sends a control signal to a control unit 20 ( Figure 3) which emits an alarm signal indicating the attempt to tamper with the component 9.
  • the control unit 20 can be a microcontroller such as a CPU already provided in the component 9 if it is a sensor, or a CPU used for the anti-tamper device 10.
  • the control unit 20 sends an activation signal to a pilot circuit 21.
  • the pilot circuit 21 can be obtained for example by means of a digital-to-analog converter of the R-2R type which performs a digital-to-analog conversion using four resistors R1, R2, R3 and R4 with different values.
  • the pilot circuit 21 sends the emitter (LED) 11 a constant current piloting signal V1 so that the emitter 11 turns on for a time of about 0.5 milliseconds.
  • the anti-tamper device 10 provides a data bus to receive and send messages.
  • the data bus is a logical entity that allows management and control of each individual device, including the anti-tamper device 10.
  • the data bus may be radiofrequency or cabled.
  • the transmission or reception time of a message by the data bus, depending on the length of the message, is about 1.5-20 milliseconds.
  • the data bus is organized to manage the reception/transmission event as a top priority event. That is to say if the transmission event is simultaneous with the reception event, control of the bus is taken by the reception event.
  • the top diagram represents, in an arbitrary scale of ordinates, the activation pulse V1 applied at intervals T (equal to about 130 milliseconds) to the pilot circuit 21 of the emitter 11.
  • the receiver 12 thus reads the status of the wave reflected by the walls of the casing 1 every 130 milliseconds.
  • the signal received by the receiver 12 is sent to an amplifier block 22 that brings it to voltage levels between 1-4 volts.
  • the voltage output signal from the amplifier block 22, designated as V2 is sent to the control unit 20, in which it is sampled and digitally filtered, as will be further explained below.
  • the amplifier block 22 can be made with an operational amplifier having the inverting input (-) connected to the receiver 12 and the non-inverting input (+) connected to a voltage source Vref of about 1 Volt which serves to eliminate the non-linearity of the operational amplifier.
  • the amplifier block 22 comprises a feedback loop 23 consisting of an analog filter which serves to remove disturbance and amplify the useful signal.
  • the feedback block 23 amplifies only the reflected wave, whilst it leaves any disturbance outside the useful frequency band unchanged.
  • the feedback block 23 can be made by means of a resistor R and a condenser C placed in parallel.
  • the output signal V2 from the integrator block is sent to the control unit 20.
  • the control unit 20 comprises an analog-to-digital converter 33 that converts the analog signal V2 to a digital signal. Inside the control unit 20 the digital signal indicating the voltage V2 detected is filtered by means of digital filters and compared with a threshold signal that will set off a possible alarm.
  • FIR filtering techniques are used to obtain said threshold signal. Said threshold will be updated dynamically so as to compensate the variations of the components 9 and the slow variations due to the dust or anything else present on the casing 1.
  • a comparator is implemented by means of a special software and carries out a comparison logic of the mathematical type comparing the digital signal indicating the voltage V2 detected with the dynamically updated threshold value.
  • the initialisation phase of the anti-tamper device is activated by a control signal sent by the control unit 20 by means of the data bus.
  • the value of the voltage measurement indicative of the light intensity is taken as the reference (mean flow). Furthermore the voltage value when the transmitter 11 is not emitting is also measured. This value serves to make a differential measurement that increases the immunity to disturbances.
  • V_background noise a signal indicative of the background noise
  • V_background noise + V_reflected wave a signal indicative of the background noise
  • V_anti-tamper V_reflected wave - V_background noise
  • V_anti-tamper is measured in the initialisation phase a mean signal value (V_mean anti-tamper) is obtained.
  • V_mean anti-tamper value is updated every minute to compensate for very slow variations of the components of the system.
  • a threshold value (V_threshold) indicative of tampering with the anti-tamper device is set by means of the bus.
  • Very fast variations of the system such as an attempt at tampering for example, cause the condition (V_anti-tamper - V_mean anti-tamper) > V_threshold. If said threshold value (V_threshold) is exceeded, the control unit 20 generates an alarm signal.
  • the initialisation phase activated by the bus serves to bring the voltage on the control unit 20 to a value between 2.5V and 3.5V, which coincides with the range of maximum sensitivity of the receiving part 12.
  • Said voltage value is automatically calculated by selecting the current on the emitter 11, by means of one of the resistors R1, R2, R3 and R4 of the pilot circuit 21, so as to obtain the desired voltage value on the analog-to-digital converter 33.
  • the installer can disconnect the anti-tamper device and repeat the initialisation operations.
  • a reflecting mirror can be inserted in the casing 1, preferably in the inner part of the rear wall of the casing, in order to restore the system to optimal working conditions.
  • Infrared emitters matched with the reception frequency of the receivers are preferably used. That is to say, if an emitter emits with a wavelength of 880 nanometers, the receiver also will have the maximum sensitivity at that wavelength.
  • V_anti-tamper V_reflected wave - V_background noise

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Burglar Alarm Systems (AREA)
  • Slot Machines And Peripheral Devices (AREA)
  • Alarm Systems (AREA)
  • Emergency Alarm Devices (AREA)
  • Crushing And Pulverization Processes (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
EP01109800A 2000-07-19 2001-04-20 Dispositif anti-sabotage et méthode pour la détection de sabotage dans un composant Expired - Lifetime EP1174839B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SI200130494T SI1174839T1 (sl) 2000-07-19 2001-04-20 Naprava proti nedovoljenemu odpiranju in relativni postopek za detektiranje nedovoljenega odpiranjaz elementi

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT2000MI001640A IT1318199B1 (it) 2000-07-19 2000-07-19 Dispositivo antimanomissione e relativo metodo per la rilevazionedella manomissione di un componente.
ITMI001640 2000-07-19

Publications (3)

Publication Number Publication Date
EP1174839A2 true EP1174839A2 (fr) 2002-01-23
EP1174839A3 EP1174839A3 (fr) 2003-05-02
EP1174839B1 EP1174839B1 (fr) 2005-11-30

Family

ID=11445511

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01109800A Expired - Lifetime EP1174839B1 (fr) 2000-07-19 2001-04-20 Dispositif anti-sabotage et méthode pour la détection de sabotage dans un composant

Country Status (6)

Country Link
EP (1) EP1174839B1 (fr)
AT (1) ATE311646T1 (fr)
DE (1) DE60115336T2 (fr)
ES (1) ES2253292T3 (fr)
IT (1) IT1318199B1 (fr)
SI (1) SI1174839T1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1494188A1 (fr) * 2003-01-30 2005-01-05 Matsushita Electric Industrial Co., Ltd. Dispositif de detection d'anomalies et appareil d'information utilisant un tel dispositif
WO2007019642A1 (fr) * 2005-08-18 2007-02-22 Bioloop Pty Ltd Agencement et système pour la détection de la falsification
WO2007147323A1 (fr) * 2006-06-16 2007-12-27 Hong Kong Applied Science and Technology Research Institute Co. Ltd Dispositifs de contrôle et dispositifs de surveillance intégrant ces dispositifs de contrôle
CN101916345A (zh) * 2010-08-05 2010-12-15 深圳市莱克科技有限公司 一种数据保护装置
US8810422B2 (en) * 2007-12-20 2014-08-19 Honeywell International, Inc. Surveillance system
GB2577280A (en) * 2018-09-19 2020-03-25 Blueskytec Ltd Electronic anti-tamper device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0748003A2 (fr) * 1995-06-08 1996-12-11 GEWISS S.p.A. Dispositif inviolable applicable aux boîtiers supportant des prises électriques
EP0772171A1 (fr) * 1995-11-03 1997-05-07 Cerberus Ag Détecteur passif d'intrusion et utilisation du détecteur

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0748003A2 (fr) * 1995-06-08 1996-12-11 GEWISS S.p.A. Dispositif inviolable applicable aux boîtiers supportant des prises électriques
EP0772171A1 (fr) * 1995-11-03 1997-05-07 Cerberus Ag Détecteur passif d'intrusion et utilisation du détecteur

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1494188A1 (fr) * 2003-01-30 2005-01-05 Matsushita Electric Industrial Co., Ltd. Dispositif de detection d'anomalies et appareil d'information utilisant un tel dispositif
EP1494188A4 (fr) * 2003-01-30 2005-06-29 Matsushita Electric Ind Co Ltd Dispositif de detection d'anomalies et appareil d'information utilisant un tel dispositif
US7167092B2 (en) 2003-01-30 2007-01-23 Matsushita Electric Industrial Co., Ltd. Abnormality detector and information apparatus using the same
WO2007019642A1 (fr) * 2005-08-18 2007-02-22 Bioloop Pty Ltd Agencement et système pour la détection de la falsification
WO2007147323A1 (fr) * 2006-06-16 2007-12-27 Hong Kong Applied Science and Technology Research Institute Co. Ltd Dispositifs de contrôle et dispositifs de surveillance intégrant ces dispositifs de contrôle
US8810422B2 (en) * 2007-12-20 2014-08-19 Honeywell International, Inc. Surveillance system
CN101916345A (zh) * 2010-08-05 2010-12-15 深圳市莱克科技有限公司 一种数据保护装置
US12067156B2 (en) 2018-09-18 2024-08-20 Blueskytec Ltd. Electronic anti-tamper device
GB2577280A (en) * 2018-09-19 2020-03-25 Blueskytec Ltd Electronic anti-tamper device
GB2577280B (en) * 2018-09-19 2022-11-09 Blueskytec Ltd Electronic anti-tamper device

Also Published As

Publication number Publication date
DE60115336D1 (de) 2006-01-05
EP1174839A3 (fr) 2003-05-02
EP1174839B1 (fr) 2005-11-30
ITMI20001640A0 (it) 2000-07-19
ATE311646T1 (de) 2005-12-15
DE60115336T2 (de) 2006-08-03
ITMI20001640A1 (it) 2002-01-19
ES2253292T3 (es) 2006-06-01
SI1174839T1 (sl) 2006-06-30
IT1318199B1 (it) 2003-07-28

Similar Documents

Publication Publication Date Title
EP0556898B1 (fr) Système d'alarme d'intrusion
US4327362A (en) Meter rotor rotation optical sensor
EP1330801B1 (fr) Microcircuit integre pour alarme et son procede d'utilisation
EP1251473B1 (fr) Système de communication pour détecteurs de risque
EP1290650B1 (fr) Dispositif de detection sans fil base sur un processeur
CN1898551B (zh) 测定散射光信号的方法和实现该方法的散射光检测器
US20160328936A1 (en) Open Scattered Light Smoke Detector And Testing Device For An Open Scattered Light Smoke Detector Of This Type
AU6106099A (en) Rfid detection system
EP1164556A3 (fr) Appareil d'alarme d'intrusion optoélectronique
EP1174839B1 (fr) Dispositif anti-sabotage et méthode pour la détection de sabotage dans un composant
KR100367210B1 (ko) 광 섬유를 이용한 침입 경보 장치
JPH0441395B2 (fr)
AU1472083A (en) Fiber optic acoustic transducer intrusion setection system
JPH09501253A (ja) 赤外線式侵入感知器
EP0681723B1 (fr) Dispositif antibrouillage radio infraudable pour systemes de surveillance d'intrusions
KR0163243B1 (ko) 광파이버를 이용한 침입자 경보장치
JP4917203B2 (ja) 検知ゾーン内にある物体を検知する方法およびシステム
KR20020023577A (ko) 적외선 감지장치
KR100339255B1 (ko) 적외선 감지기 및 그 처리 방법
EP1151423B1 (fr) Appareil detecteur de mouvement et capteur de choc combine
KR200227878Y1 (ko) 적외선 감지장치
JP3144582B2 (ja) 給水制御装置
RU2210117C2 (ru) Дымовой пожарный извещатель
KR20050095441A (ko) 적외선 감지기 및 그 제어방법
JPH0542554Y2 (fr)

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

17P Request for examination filed

Effective date: 20031015

AKX Designation fees paid

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AXX Extension fees paid

Extension state: MK

Payment date: 20031015

Extension state: RO

Payment date: 20031015

Extension state: LV

Payment date: 20031015

Extension state: SI

Payment date: 20031015

Extension state: LT

Payment date: 20031015

Extension state: AL

Payment date: 20031015

17Q First examination report despatched

Effective date: 20040319

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051130

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051130

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051130

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 60115336

Country of ref document: DE

Date of ref document: 20060105

Kind code of ref document: P

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20060228

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20060228

REG Reference to a national code

Ref country code: CH

Ref legal event code: NV

Representative=s name: A. BRAUN, BRAUN, HERITIER, ESCHMANN AG PATENTANWAE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060420

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060430

REG Reference to a national code

Ref country code: GR

Ref legal event code: EP

Ref document number: 20060400703

Country of ref document: GR

LTIE Lt: invalidation of european patent or patent extension

Effective date: 20051130

NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
REG Reference to a national code

Ref country code: ES

Ref legal event code: FG2A

Ref document number: 2253292

Country of ref document: ES

Kind code of ref document: T3

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20060831

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

REG Reference to a national code

Ref country code: CH

Ref legal event code: PFA

Owner name: VIMAR SPA

Free format text: VIMAR SPA#VIALE VICENZA 14#36063 MAROSTICA (VI) (IT) -TRANSFER TO- VIMAR SPA#VIALE VICENZA 14#36063 MAROSTICA (VI) (IT)

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051130

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: PT

Payment date: 20090330

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 20090327

Year of fee payment: 9

Ref country code: GR

Payment date: 20090330

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: ES

Payment date: 20090406

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: AT

Payment date: 20090429

Year of fee payment: 9

Ref country code: DE

Payment date: 20090429

Year of fee payment: 9

Ref country code: FR

Payment date: 20090427

Year of fee payment: 9

Ref country code: LU

Payment date: 20090414

Year of fee payment: 9

Ref country code: TR

Payment date: 20090420

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20090407

Year of fee payment: 9

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20100420

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20101230

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100430

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100420

REG Reference to a national code

Ref country code: SI

Ref legal event code: KO00

Effective date: 20101207

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101020

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100430

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101103

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100430

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101103

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100420

REG Reference to a national code

Ref country code: ES

Ref legal event code: FD2A

Effective date: 20110714

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20110704

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100421

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100420

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100420

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20130412

Year of fee payment: 13

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140420