EP1164455A1 - Process and device for generating a temperature independent current - Google Patents

Process and device for generating a temperature independent current Download PDF

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Publication number
EP1164455A1
EP1164455A1 EP00202059A EP00202059A EP1164455A1 EP 1164455 A1 EP1164455 A1 EP 1164455A1 EP 00202059 A EP00202059 A EP 00202059A EP 00202059 A EP00202059 A EP 00202059A EP 1164455 A1 EP1164455 A1 EP 1164455A1
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Prior art keywords
current
voltage
transistor
transistors
vos
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German (de)
French (fr)
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EP1164455B1 (en
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Arthur Descombes
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EM Microelectronic Marin SA
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EM Microelectronic Marin SA
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Priority to EP00202059A priority Critical patent/EP1164455B1/en
Priority to AT00202059T priority patent/ATE328313T1/en
Priority to DE60028356T priority patent/DE60028356T2/en
Publication of EP1164455A1 publication Critical patent/EP1164455A1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

Definitions

  • the present invention generally relates to the field of circuits current generators. More particularly, the present invention relates to a process for generating a current substantially independent of temperature as well than to a device making it possible to implement this method.
  • FIG. 1 shows an example of a circuit prior art current generator generally identified by the reference digital 10.
  • This current generator circuit 10 constitutes a generator circuit of voltage controlled current.
  • the current generator circuit 10 typically comprises means amplification formed by an operational amplifier or differential amplifier 11, a transistor 12 and a resistor 13.
  • the operational amplifier 11 includes a positive input terminal (non-inverting input) 11 a to which a input voltage referred Vin, a negative input terminal (inverting input) 11b and an exit 11c.
  • This amplification means 11 supplies a voltage at its output 11c in response to a difference between the voltages applied respectively to its first and second input terminals 11a and 11b.
  • the transistor 12 is formed in this example of an n-MOS transistor with effect of field of which the gate 12c is connected to the output 11c of the operational amplifier 11.
  • the source 12a of transistor 12 is connected to the negative input 11b of the operational amplifier 11 as well as to a first terminal of the resistor 13.
  • the other terminal of resistor 13 is connected to a supply potential or reference potential Vss.
  • This reference potential Vss is typically defined as the most negative potential of the circuit or ground of the circuit at 0 volts.
  • Another Vdd supply potential (not illustrated in Figure 1) is also existing.
  • the potentials Vss and Vdd constitute supply voltages of the circuit, and in particular of the operational amplifier 11.
  • the drain-source branch 12a-12b of the MOS transistor 12 is crossed by a current referenced 11.
  • the analysis of this circuit is direct.
  • the operational amplifier 11 modifies the voltage at its output 11c so that the voltage present at its negative input 11b is substantially equal to the voltage present at its positive input 11a, that is to say substantially equal to the voltage of Wine entry.
  • the current I1 generated is thus proportional to the input voltage Vin applied to the positive input 11a of the operational amplifier.
  • the generator circuit 10 of FIG. 1 forms a current receiver or "current sink", that is to say that a current I1 is drained from the drain 12b of the transistor 12 towards the most negative potential Vss.
  • a modification of circuit 10 of the Figure 1 allows to form a current source.
  • Figure 2 illustrates a circuit generator spotted 20 showing such a modification. Numerical references identical are used to indicate the elements already presented, i.e. the operational amplifier 11, the MOS transistor 12 and the resistor 13.
  • the generator circuit 20 of the FIG. 2 typically comprises a current mirror 30 consisting of first and second p-MOS field effect transistors marked 31 and 32 respectively.
  • sources 31a and 32a of transistors 31 and 32 are connected to the potential most positive power supply Vdd.
  • the gate 31c and the drain 31b of the transistor 31 are connected together to the drain 12b of transistor 12 and the gate 32c of transistor 32 is connected to the gate 31c of the transistor 31.
  • the current mirror 30 thus operates so as to "copy” the current 11 and produce a current I2 image of the current I1 in the drain-source branch of the transistor 32.
  • a factor of proportionality can be introduced into the mirror by an adequate choice of ratios width over W / L channel length of the MOS transistors 31, 32 in order to multiply or divide the current 11.
  • the circuit 20 of FIG. 2 can obviously still be modified so that the current mirror include other branches, for example a third field effect MOS transistor 33 as shown in Figure 2 to produce a third stream 13.
  • the current mirror include other branches, for example a third field effect MOS transistor 33 as shown in Figure 2 to produce a third stream 13.
  • a problem with the current generator circuits illustrated in Figures 1 and 2 lies in particular in the temperature dependence of the currents generated.
  • a stable voltage is used as input voltage Vin.
  • temperature such as a bandgap reference voltage equal to approximately 1.2 volts. This bandgap reference voltage has a relatively low dependence on temperature, of the order of 50 ppm / ° C.
  • a general aim of the present invention is therefore to propose a method of generation of a current substantially independent of temperature by means of a current generator circuit of the aforementioned type.
  • Another object of the present invention is to provide a device allowing to implement the above-mentioned method, namely a circuit generating current overcoming the drawbacks encountered with the use of resistors integrated and arranged to produce a substantially independent current in temperature.
  • Yet another object of the present invention is to provide a solution which involves only a few modifications of the current generator circuit and which turns out to be simple and inexpensive consequence to manufacture compared to already existing solutions existing.
  • the present invention has for first object a process for generating a current substantially independent of temperature, of which the features are set out in claim 1.
  • Another subject of the present invention is a current generator circuit, the features are set out in claim 5.
  • the present invention is based on the finding by the inventor of the possibility to compensate for the temperature dependence of the current due to the resistance used by acting on the geometry of the differential pair of transistors of the operational amplifier used, and this in order to voluntarily generate a voltage offset between the input terminals of this operational amplifier, this voltage offset being adjusted to have a temperature dependence compensating for the temperature dependence of the resistance used.
  • the inventor could see that by arranging the operational amplifier so as to create a geometric imbalance between the two transistors of the pair differential of this amplifier, an offset voltage between the input terminals of the amplifier was generated, this offset voltage having a dependence on substantially linear temperature which can be adjusted by varying the geometry of the differential pair transistors, in particular through their ratio dimensional width over length of channel W / L.
  • An advantage of the present invention lies in its simplicity of implementation work as well as in the low cost of modification.
  • the offset voltage of the operational amplifier can be adjusted to present independently a positive or negative temperature coefficient depending on whether one acts on one or the other of the transistors of the differential pair. It is thus possible to compensate for the temperature dependence of resistors having either a positive or negative temperature coefficient.
  • Operational amplifiers or amplifier differentials typically present a pair of transistors mounted according to a differential arrangement and the control electrodes of which are respectively connected to the amplifier input terminals.
  • FIG. 3 schematically shows an example of a operational amplifier which can be used as amplification means 11 of the current generator circuit according to the present invention.
  • the operational amplifier illustrated in FIG. 3, generally identified by the reference numeral 11 in accordance with the illustrations of FIGS. 1 and 2, comprises thus a differential pair of transistors, marked 110, comprising two transistors p-MOS 111 and 112 whose sources 111a and 112a are connected together.
  • the gates 111 c and 112 c of the transistors of the differential pair 110 form respectively the input terminals 11a and 11b of the operational amplifier 11.
  • the sources 111a and 112a of the transistors of the differential pair 110 are connected to the drain 113b of a p-MOS transistor 113 whose source 113a is connected to the supply potential Vdd.
  • the gate 113c of this transistor 113 is controlled by a VBIAS bias voltage.
  • the operational amplifier 11 of FIG. 3, moreover comprises two current mirrors 121 and 124 each comprising two n-MOS transistors 122 and 123, respectively 125 and 126.
  • the sources 122a, 123a, 125a and 126a of these transistors are connected to the supply potential or ground Vss.
  • Grids 122c and 123c transistors 122, 123 and the drain 122b of transistor 122 are connected sets at the drain 111b of the first transistor 111 of the differential pair 110. From same, the gates 125c and 126c of the transistors 125, 126 as well as the drain 125b of the transistor 125 are connected together to the drain 112b of the second transistor 112 of the differential pair 110.
  • the operational amplifier 11 of FIG. 3 also includes a another current mirror 130 comprising two p-MOS transistors 131 and 132.
  • the sources 131a and 132a of these transistors are connected to the supply potential Vdd while the drains 131b and 132b are respectively connected to the drains 126b and 123b of the transistors 126 and 123 of the current mirrors 124 and 121.
  • the gates 131c and 132c of the transistors 131 and 132 as well as the drain 131b of the transistor 131 are connected together.
  • the output 11c of the operational amplifier is formed of the connection node between the drain 132b of the transistor 132 and the drain 123b of the transistor 123.
  • Figure 4 schematically shows another example of an operational amplifier that can be used as a means amplification 11 of the current generator circuit according to the present invention.
  • the operational amplifier illustrated in FIG. 4, generally identified by the reference numeral 11 in accordance with the illustrations of FIGS. 1 and 2, comprises thus a differential pair of transistors, marked 210, comprising two transistors p-MOS 211 and 212 whose sources 211a and 212a are connected together.
  • the gates 211c and 212c of the transistors of the differential pair 210 form respectively the input terminals 11a and 11b of the operational amplifier 11.
  • the sources 211a and 212a of the transistors of the differential pair 210 are connected to the drain 213b of a p-MOS transistor 213 whose source 213a is connected to the supply potential Vdd.
  • the gate 213c of this transistor 213 is controlled by a VBIAS bias voltage.
  • the operational amplifier 11 of FIG. 3, moreover comprises a mirror current 220 comprising two n-MOS transistors 221 and 222.
  • Sources 221a, 222a of these transistors are connected to the supply potential or ground Vss.
  • the gates 221c and 222c of the transistors 221, 222 as well as the drain 222b of the transistor 222 are connected together to the drain 212b of the second transistor 212 of the pair differential 210.
  • the drain 221b of the transistor 221 is connected to the drain 211b of the first transistor 211 of the differential pair 210.
  • the operational amplifier 11 of FIG. 4 also includes a branch connected between the supply potentials Vdd and Vss comprising a p-MOS transistor 231 and an n-MOS transistor 232.
  • the source 231a of transistor 231 is connected to the supply potential Vdd, while the gate 231c of this transistor is connected to the VBIAS bias voltage.
  • Source 232a of transistor 232 is connected to the ground potential Vss while the gate 232c of this transistor is connected to the connection node between the drain 211b of the pair's transistor 211 differential and the drain 221b of the transistor 221 of the current mirror 220.
  • the drains 231b and 232b of the transistors 231 and 232 are connected together and form the output 11c of the operational amplifier.
  • the operational amplifier works at low inversion, that is to say that the transistors of the differential pair of the amplifier operational 11, operate with a gate-source voltage lower than the voltage of threshold of these transistors.
  • the operational amplifier is arranged. 11 so that it has an offset voltage Vos (T) between its first and second input terminals 11a, 11b having a temperature dependence.
  • This tension offset Vos (T) is adjusted according to the present invention to present a temperature dependence to compensate for temperature dependence resistance 13.
  • the factors (W / L) 1 and (W / L) 2 are defined as the width-to-channel length W / L ratios of the transistors forming the differential pair of the operational amplifier 11.
  • the offset voltage Vos (T) is worth, at a temperature of the order of 300 ° K, approximately 72 mV with a temperature coefficient of approximately +0.24 mV / ° K.
  • Vos (T) Vos, o + ⁇ (T - To)
  • Vos, o the value of the offset voltage at a given temperature To, for example 300 ° K
  • ⁇ the temperature coefficient in V / ° K of the offset voltage.
  • a temperature-stable reference voltage such as a bandgap voltage GBV of the adequate factor
  • GBV bandgap voltage
  • R1, R2 resistive divider
  • FIG. 5 thus shows a schematic example of implementation of the present invention constituting a current source.
  • This current source is substantially similar to the conventional current source illustrated in Figure 2.
  • the elements already presented with reference to FIG. 2 will not be described again. know the operational amplifier 11, the MOS transistor 12, the resistor 13 and the current mirror 30 making it possible to generate a second current 12 image of the current I1 traversing the drain-source branch of transistor 12.
  • the circuit of Figure 5 includes a resistive divider comprising two resistors R1 and R2 connected in series between, on the one hand, a reference voltage stable in temperature, such as a bandgap voltage VBG, and, on the other hand, the supply voltage or ground Vss.
  • the positive entry 11a of the operational amplifier 11 is connected between the two resistors R1 and R2 of so that the value of the input voltage Vin applied to this input terminal 11a is determined in a ratio R1 / R2 of the reference voltage VBG.
  • Values resistors R1 and R2 are determined to produce an input voltage adequate Wine allowing to meet the objective widely discussed previously.
  • resistive divider formed by resistors R1, R2 does not affect the temperature stability of the reference voltage VBG in any way.
  • resistors R1, R2 does not affect the temperature stability of the reference voltage VBG in any way.
  • the skilled person can perfectly consider other solutions equivalents for dividing the reference voltage of bandgap VBG for produce an adequate value of input voltage Vin, for example by means of a capacitive divider.

Abstract

A generator produces a first current (11), proportional to first temperature stable input voltage (Vin), through electrodes (12a,12b) of a first transistor (12). A weak inversion amplifier (11) produces a temperature dependent offset voltage (Vos(T)) between its inputs (11a,11b). This offset voltage and the input voltage (Vin) are adjusted to compensate resistance (13) temperature dependence so that the current generated (11) is temperature independent. Method of current (11) generation by means of a current generator circuit (10) connected to first and second supply voltages (Vss, Vdd): (a) an amplifier (11) provides a first control voltage at its output (11c) in response to a difference between the first and second voltages applied to respective inputs (11a,11b); a first transistor (12) having a first current electrode (12a), a control electrode (12c), connected to the amplifier output (11c), and a second current electrode (12b) connected to the voltage (Vdd), and; a resistive component (13) having a terminal connected to the amplifier input (11b) as well as to the transistor current electrode (12a) and a terminal the first voltage (Vss). The resistive component has a resistance value (R(T)) which is temperature dependent

Description

La présente invention concerne généralement le domaine des circuits générateurs de courant. Plus particulièrement, la présente invention se rapporte à un procédé de génération d'un courant sensiblement indépendant de la température ainsi qu'à un dispositif permettant de mettre en oeuvre ce procédé.The present invention generally relates to the field of circuits current generators. More particularly, the present invention relates to a process for generating a current substantially independent of temperature as well than to a device making it possible to implement this method.

Les circuits générateurs de courant, communément connus sous les appellations "sources de courant" ("current sources") ou "récepteurs de courant" ("current sinks") sont des éléments importants dans la conception de nombreux circuits électriques et électroniques. La figure 1 montre un exemple d'un circuit générateur de courant de l'art antérieur repéré globalement par la référence numérique 10. Ce circuit générateur de courant 10 constitue un circuit générateur de courant commandé en tension.Current generator circuits, commonly known as names "current sources" or "current receivers" ("current sinks") are important elements in the design of many electrical and electronic circuits. Figure 1 shows an example of a circuit prior art current generator generally identified by the reference digital 10. This current generator circuit 10 constitutes a generator circuit of voltage controlled current.

Le circuit générateur de courant 10 comprend typiquement un moyen d'amplification formé d'un amplificateur opérationnel ou amplificateur différentiel 11, un transistor 12 et une résistance 13. L'amplificateur opérationnel 11 comporte une borne d'entrée positive (entrée non inverseuse) 11 a sur laquelle est appliquée une tension d'entrée référée Vin, une borne d'entrée négative (entrée inverseuse) 11b et une sortie 11c. Ce moyen d'amplification 11 fournit une tension à sa sortie 11c en réponse à une différence entre les tensions appliquées respectivement à ses première et seconde bornes d'entrée 11a et 11b.The current generator circuit 10 typically comprises means amplification formed by an operational amplifier or differential amplifier 11, a transistor 12 and a resistor 13. The operational amplifier 11 includes a positive input terminal (non-inverting input) 11 a to which a input voltage referred Vin, a negative input terminal (inverting input) 11b and an exit 11c. This amplification means 11 supplies a voltage at its output 11c in response to a difference between the voltages applied respectively to its first and second input terminals 11a and 11b.

Le transistor 12 est formé dans cette exemple d'un transistor n-MOS à effet de champ dont la grille 12c est connectée à la sortie 11c de l'amplificateur opérationnel 11. La source 12a du transistor 12 est connectée à l'entrée négative 11b de l'amplificateur opérationnel 11 ainsi qu'à une première borne de la résistance 13. L'autre borne de la résistance 13 est connectée à un potentiel d'alimentation ou potentiel de référence Vss. Ce potentiel de référence Vss est typiquement défini comme le potentiel le plus négatif du circuit ou masse du circuit à 0 volts. Un autre potentiel d'alimentation Vdd (non illustré dans la figure 1) est également existant. Les potentiels Vss et Vdd constituent des tensions d'alimentation du circuit, et notamment de l'amplificateur opérationnel 11.The transistor 12 is formed in this example of an n-MOS transistor with effect of field of which the gate 12c is connected to the output 11c of the operational amplifier 11. The source 12a of transistor 12 is connected to the negative input 11b of the operational amplifier 11 as well as to a first terminal of the resistor 13. The other terminal of resistor 13 is connected to a supply potential or reference potential Vss. This reference potential Vss is typically defined as the most negative potential of the circuit or ground of the circuit at 0 volts. Another Vdd supply potential (not illustrated in Figure 1) is also existing. The potentials Vss and Vdd constitute supply voltages of the circuit, and in particular of the operational amplifier 11.

Selon le circuit générateur de courant de la figure 1, la branche drain-source 12a-12b du transistor MOS 12 est traversée par un courant référé 11. L'analyse de ce circuit est directe. L'amplificateur opérationnel 11 modifie la tension à sa sortie 11c de sorte que la tension présente à son entrée négative 11b soit sensiblement égale à la tension présente à son entrée positive 11a, c'est-à-dire sensiblement égale à la tension d'entrée Vin. La tension aux bornes de la résistance 13 est ainsi sensiblement égale à la tension d'entrée Vin, de sorte que le courant I1 traversant la branche drain-source du transistor MOS 12 est donné par : I1 = VinR où R est la valeur de la résistance 13. Le courant I1 généré est ainsi proportionnel à la tension d'entrée Vin appliquée sur l'entrée positive 11a de l'amplificateur opérationnel.According to the current generator circuit of FIG. 1, the drain-source branch 12a-12b of the MOS transistor 12 is crossed by a current referenced 11. The analysis of this circuit is direct. The operational amplifier 11 modifies the voltage at its output 11c so that the voltage present at its negative input 11b is substantially equal to the voltage present at its positive input 11a, that is to say substantially equal to the voltage of Wine entry. The voltage across the resistor 13 is thus substantially equal to the input voltage Vin, so that the current I1 passing through the drain-source branch of the MOS transistor 12 is given by: I1 = Wine R where R is the value of the resistance 13. The current I1 generated is thus proportional to the input voltage Vin applied to the positive input 11a of the operational amplifier.

Le circuit générateur 10 de la figure 1 forme un récepteur de courant ou "current sink", c'est-à-dire qu'un courant I1 est drainé à partir du drain 12b du transistor 12 vers le potentiel le plus négatif Vss. Un modification du circuit 10 de la figure 1 permet de former une source de courant. La figure 2 illustre un circuit générateur repéré 20 montrant une telle modification. Des références numériques identiques sont utilisées pour indiquer les éléments déjà présentés, c'est-à-dire l'amplificateur opérationnel 11, le transistor MOS 12 et la résistance 13.The generator circuit 10 of FIG. 1 forms a current receiver or "current sink", that is to say that a current I1 is drained from the drain 12b of the transistor 12 towards the most negative potential Vss. A modification of circuit 10 of the Figure 1 allows to form a current source. Figure 2 illustrates a circuit generator spotted 20 showing such a modification. Numerical references identical are used to indicate the elements already presented, i.e. the operational amplifier 11, the MOS transistor 12 and the resistor 13.

En complément des éléments déjà mentionnés, le circuit générateur 20 de la figure 2 comprend typiquement un miroir de courant 30 constitué de premier et second transistors p-MOS à effet de champ repérés respectivement 31 et 32. Les sources 31a et 32a des transistors 31 et 32 sont connectées au potentiel d'alimentation le plus positif Vdd. La grille 31c et le drain 31b du transistor 31 sont connectés ensembles au drain 12b du transistor 12 et la grille 32c du transistor 32 est connectée à la grille 31c du transistor 31.In addition to the elements already mentioned, the generator circuit 20 of the FIG. 2 typically comprises a current mirror 30 consisting of first and second p-MOS field effect transistors marked 31 and 32 respectively. sources 31a and 32a of transistors 31 and 32 are connected to the potential most positive power supply Vdd. The gate 31c and the drain 31b of the transistor 31 are connected together to the drain 12b of transistor 12 and the gate 32c of transistor 32 is connected to the gate 31c of the transistor 31.

Le miroir de courant 30 fonctionne ainsi de manière à "copier" le courant 11 et produire un courant I2 image du courant I1 dans la branche drain-source du transistor 32. Conformément à ce qui est typiquement connu dans le domaine, un facteur de proportionnalité peut être introduit dans le miroir par un choix adéquat des rapports largeur sur longueur de canal W/L des transistors MOS 31, 32 afin de multiplier ou diviser le courant 11.The current mirror 30 thus operates so as to "copy" the current 11 and produce a current I2 image of the current I1 in the drain-source branch of the transistor 32. In accordance with what is typically known in the art, a factor of proportionality can be introduced into the mirror by an adequate choice of ratios width over W / L channel length of the MOS transistors 31, 32 in order to multiply or divide the current 11.

Le circuit 20 de la figure 2 peut bien évidemment encore être modifié pour que le miroir de courant comprennent d'autres branches, par exemple un troisième transistor MOS à effet de champ 33 comme indiqué dans la figure 2 afin de produire un troisième courant 13.The circuit 20 of FIG. 2 can obviously still be modified so that the current mirror include other branches, for example a third field effect MOS transistor 33 as shown in Figure 2 to produce a third stream 13.

Un problème des circuits générateurs de courant illustrés aux figures 1 et 2 réside notamment dans la dépendance en température des courants générés. Typiquement, on utilise, d'une part, comme tension d'entrée Vin une tension stable en température telle une tension de référence de bandgap égale à environ 1.2 volts. Cette tension de référence de bandgap présente une relative faible dépendance en température, de l'ordre de 50 ppm/°C.A problem with the current generator circuits illustrated in Figures 1 and 2 lies in particular in the temperature dependence of the currents generated. Typically, on the one hand, as input voltage Vin, a stable voltage is used. temperature such as a bandgap reference voltage equal to approximately 1.2 volts. This bandgap reference voltage has a relatively low dependence on temperature, of the order of 50 ppm / ° C.

Afin de réaliser la résistance 13, on cherche d'autre part à utiliser une résistance dont le coefficient de température est relativement peu élevé. Pour des raisons de conception, on cherche également à réaliser la résistance 13 sous forme intégrée et ne pas faire appel à une résistance externe au circuit. Diverses solutions existent en technologie CMOS pour concevoir des résistances intégrées. On peut toutefois constater que le coefficient de température de ces résistances intégrées reste relativement élevé par rapport à la stabilité en température d'une tension de référence de bandgap. A titre d'exemple, une résistance intégrées de type Rpoly, c'est-à-dire une résistance intégrée formée d'une couche de polysilicium, présente typiquement un coefficient de température de l'ordre de + 0.07%/°C, soit un coefficient de température qui reste sensiblement important par rapport à la stabilité d'une tension de référence de bandgap.In order to achieve resistance 13, on the other hand, it is sought to use a resistance with a relatively low temperature coefficient. For some design reasons, we are also trying to achieve resistance 13 in the form integrated and do not use a resistor external to the circuit. Various solutions exist in CMOS technology to design integrated resistors. We can however note that the temperature coefficient of these integrated resistors remains relatively high compared to the temperature stability of a voltage of bandgap reference. For example, an integrated resistance of Rpoly type, that is to say an integrated resistor formed of a layer of polysilicon, present typically a temperature coefficient of the order of + 0.07% / ° C, i.e. temperature coefficient which remains appreciably important compared to the stability of a bandgap reference voltage.

L'homme du métier constate rapidement qu'il ne dispose pas de manière satisfaisante, en technologie CMOS, de résistances intégrées dont les coefficients en température sont suffisamment faibles. Dans l'optique de réaliser un circuit générateur de courant du type susmentionné, le courant produit au moyen d'un tel circuit présentera donc une dépendance en température essentiellement due à la dépendance en température de la résistance intégrée employée.A person skilled in the art quickly realizes that he does not have a way satisfactory, in CMOS technology, of integrated resistors whose coefficients in temperatures are low enough. In order to realize a circuit current generator of the aforementioned type, the current produced by means of such circuit will therefore have a temperature dependence essentially due to the temperature dependence of the integrated resistance used.

Un but général de la présente invention est donc de proposer un procédé de génération d'un courant sensiblement indépendant en température au moyen d'un circuit générateur de courant du type susmentionné.A general aim of the present invention is therefore to propose a method of generation of a current substantially independent of temperature by means of a current generator circuit of the aforementioned type.

Un autre but de la présente invention est de proposer un dispositif permettant de mettre en oeuvre le procédé susmentionné, à savoir un circuit générateur de courant palliant aux inconvénients rencontrés avec l'utilisation de résistances intégrées et agencé pour produire un courant sensiblement indépendant en température.Another object of the present invention is to provide a device allowing to implement the above-mentioned method, namely a circuit generating current overcoming the drawbacks encountered with the use of resistors integrated and arranged to produce a substantially independent current in temperature.

Encore un autre but de la présente invention est de proposer une solution qui n'implique que peu de modifications du circuit générateur de courant et qui s'avère en conséquence simple et peu coûteux à fabriquer par rapport aux solutions déjà existantes.Yet another object of the present invention is to provide a solution which involves only a few modifications of the current generator circuit and which turns out to be simple and inexpensive consequence to manufacture compared to already existing solutions existing.

Afin de répondre à ces buts, la présente invention a pour premier objet un procédé de génération d'un courant sensiblement indépendant en température dont les caractéristiques sont énoncées à la revendication 1. In order to meet these aims, the present invention has for first object a process for generating a current substantially independent of temperature, of which the features are set out in claim 1.

La présente invention a pour autre objet un circuit générateur de courant dont les caractéristiques sont énoncées à la revendication 5.Another subject of the present invention is a current generator circuit, the features are set out in claim 5.

La présente invention repose sur la constatation par l'inventeur de la possibilité de compenser la dépendance en température du courant due à la résistance employée en agissant sur la géométrie de la paire différentielle de transistors de l'amplificateur opérationnel utilisé, et ceci afin de générer volontairement une tension d'offset entre les bornes d'entrées de cet amplificateur opérationnel, cette tension d'offset étant ajustée pour présenter une dépendance en température compensant la dépendance en température de la résistance employée.The present invention is based on the finding by the inventor of the possibility to compensate for the temperature dependence of the current due to the resistance used by acting on the geometry of the differential pair of transistors of the operational amplifier used, and this in order to voluntarily generate a voltage offset between the input terminals of this operational amplifier, this voltage offset being adjusted to have a temperature dependence compensating for the temperature dependence of the resistance used.

En effet, l'inventeur a pu constater qu'en agençant l'amplificateur opérationnel de manière à créer un déséquilibre géométrique entre les deux transistors de la paire différentielle de cet amplificateur, une tension d'offset entre les bornes d'entrées de l'amplificateur était générée, cette tension d'offset présentant une dépendance en température sensiblement linéaire pouvant être ajustée en jouant sur la géométrie des transistors de la paire différentielle, notamment par le biais de leur rapport dimensionnel largeur sur longueur de canal W/L.Indeed, the inventor could see that by arranging the operational amplifier so as to create a geometric imbalance between the two transistors of the pair differential of this amplifier, an offset voltage between the input terminals of the amplifier was generated, this offset voltage having a dependence on substantially linear temperature which can be adjusted by varying the geometry of the differential pair transistors, in particular through their ratio dimensional width over length of channel W / L.

Un avantage de la présente invention réside dans sa simplicité de mise en oeuvre ainsi que dans le faible coût de modification. De plus, la tension d'offset de l'amplificateur opérationnel peut être ajustée de manière à présenter indépendamment un coefficient de température positif ou négatif selon que l'on agit sur l'un ou l'autre des transistors de la paire différentielle. Il est ainsi possible de compenser la dépendance en température de résistances présentant soit un coefficient de température positif ou négatif.An advantage of the present invention lies in its simplicity of implementation work as well as in the low cost of modification. In addition, the offset voltage of the operational amplifier can be adjusted to present independently a positive or negative temperature coefficient depending on whether one acts on one or the other of the transistors of the differential pair. It is thus possible to compensate for the temperature dependence of resistors having either a positive or negative temperature coefficient.

D'autres caractéristiques et avantages de la présente invention apparaítront plus clairement à la lecture de la description détaillée qui suit, faite en référence aux dessins annexés donnés à titre d'exemples non limitatifs et dans lesquels :

  • la figure 1, déjà présentée, montre un exemple schématique d'un circuit générateur de courant de l'art antérieur formant un récepteur de courant ou "current sink";
  • la figure 2, déjà présentée, montre un exemple schématique d'un circuit générateur de courant de l'art antérieur formant une source de courant;
  • la figure 3 présente un premier exemple schématique d'un amplificateur opérationnel ou amplificateur différentiel pouvant être utilisé dans le cadre de la présente invention;
  • la figure 4 présente un autre exemple schématique d'un amplificateur opérationnel ou amplificateur différentiel pouvant également être utilisé dans le cadre de la présente invention; et
  • la figure 5 présente d'un exemple de mise en oeuvre de la présente invention comportant un diviseur résistif sur l'entrée positive de l'amplificateur opérationnel afin de dériver une tension d'entrée adéquate à partir d'une référence de tension stable en température, telle une tension de bandgap.
Other characteristics and advantages of the present invention will appear more clearly on reading the detailed description which follows, given with reference to the appended drawings given by way of nonlimiting examples and in which:
  • Figure 1, already presented, shows a schematic example of a current generator circuit of the prior art forming a current receiver or "current sink";
  • Figure 2, already presented, shows a schematic example of a current generator circuit of the prior art forming a current source;
  • FIG. 3 presents a first schematic example of an operational amplifier or differential amplifier which can be used in the context of the present invention;
  • FIG. 4 shows another schematic example of an operational amplifier or differential amplifier which can also be used in the context of the present invention; and
  • FIG. 5 presents an exemplary implementation of the present invention comprising a resistive divider on the positive input of the operational amplifier in order to derive an adequate input voltage from a voltage stable voltage reference , like a bandgap tension.

Dans le cadre de la présente invention, on fait appel à un circuit générateur de courant conforme aux illustrations des figures 1 et 2. On ne décrira pas à nouveau les éléments constitutifs de ce circuit générateur de courant qui ont déjà été présentés en préambule et on se contentera de se référer aux références des figures 1 et 2 déjà discutées.In the context of the present invention, use is made of a circuit generating current in accordance with the illustrations in FIGS. 1 and 2. We will not again describe the constituent elements of this current generator circuit which have already been presented in preamble and we will just refer to the references of Figures 1 and 2 already discussed.

On définira maintenant ce que l'on entend par "paire différentielle" dans le cadre de la présente invention. Les amplificateurs opérationnels ou amplificateur différentiels présentent typiquement une paire de transistors montés selon un agencement différentiel et dont les électrodes de commande sont respectivement connectées aux bornes d'entrée de l'amplificateur.We will now define what is meant by "differential pair" in the part of the present invention. Operational amplifiers or amplifier differentials typically present a pair of transistors mounted according to a differential arrangement and the control electrodes of which are respectively connected to the amplifier input terminals.

A titre d'illustration, la figure 3 montre schématiquement un exemple d'un amplificateur opérationnel pouvant être utilisé comme moyen d'amplification 11 du circuit générateur de courant selon la présente invention.By way of illustration, FIG. 3 schematically shows an example of a operational amplifier which can be used as amplification means 11 of the current generator circuit according to the present invention.

L'amplificateur opérationnel illustré à la figure 3, repéré globalement par la référence numérique 11 conformément aux illustrations des figures 1 et 2, comporte ainsi une paire différentielle de transistors, repérée 110, comportant deux transistors p-MOS 111 et 112 dont les sources 111a et 112a sont connectées ensembles. Les grilles 111 c et 112c des transistors de la paire différentielle 110 forment respectivement les bornes d'entrée 11a et 11b de l'amplificateur opérationnel 11.The operational amplifier illustrated in FIG. 3, generally identified by the reference numeral 11 in accordance with the illustrations of FIGS. 1 and 2, comprises thus a differential pair of transistors, marked 110, comprising two transistors p-MOS 111 and 112 whose sources 111a and 112a are connected together. The gates 111 c and 112 c of the transistors of the differential pair 110 form respectively the input terminals 11a and 11b of the operational amplifier 11.

Les sources 111a et 112a des transistors de la paire différentielle 110 sont connectées au drain 113b d'un transistor p-MOS 113 dont la source 113a est connectée au potentiel d'alimentation Vdd. La grille 113c de ce transistor 113 est commandée par une tension de polarisation VBIAS.The sources 111a and 112a of the transistors of the differential pair 110 are connected to the drain 113b of a p-MOS transistor 113 whose source 113a is connected to the supply potential Vdd. The gate 113c of this transistor 113 is controlled by a VBIAS bias voltage.

L'amplificateur opérationnel 11 de la figure 3, comporte par ailleurs deux miroirs de courant 121 et 124 comprenant chacun deux transistors n-MOS 122 et 123, respectivement 125 et 126. Les sources 122a, 123a, 125a et 126a de ces transistors sont connectées au potentiel d'alimentation ou masse Vss. Les grilles 122c et 123c des transistors 122, 123 ainsi que le drain 122b du transistor 122 sont connectés ensembles au drain 111b du premier transistor 111 de la paire différentielle 110. De même, les grilles 125c et 126c des transistors 125, 126 ainsi que le drain 125b du transistor 125 sont connectés ensembles au drain 112b du deuxième transistor 112 de la paire différentielle 110.The operational amplifier 11 of FIG. 3, moreover comprises two current mirrors 121 and 124 each comprising two n-MOS transistors 122 and 123, respectively 125 and 126. The sources 122a, 123a, 125a and 126a of these transistors are connected to the supply potential or ground Vss. Grids 122c and 123c transistors 122, 123 and the drain 122b of transistor 122 are connected sets at the drain 111b of the first transistor 111 of the differential pair 110. From same, the gates 125c and 126c of the transistors 125, 126 as well as the drain 125b of the transistor 125 are connected together to the drain 112b of the second transistor 112 of the differential pair 110.

Finalement, l'amplificateur opérationnel 11 de la figure 3 comporte encore un autre miroir de courant 130 comprenant deux transistors p-MOS 131 et 132. Les sources 131a et 132a de ces transistors sont connectées au potentiel d'alimentation Vdd alors que les drains 131b et 132b sont respectivement connectés aux drains 126b et 123b des transistors 126 et 123 des miroirs de courant 124 et 121. De plus, les grilles 131c et 132c des transistors 131 et 132 ainsi que le drain 131b du transistor 131 sont connectés ensemble. La sortie 11c de l'amplificateur opérationnel est formée du noeud de connexion entre le drain 132b du transistor 132 et le drain 123b du transistor 123.Finally, the operational amplifier 11 of FIG. 3 also includes a another current mirror 130 comprising two p-MOS transistors 131 and 132. The sources 131a and 132a of these transistors are connected to the supply potential Vdd while the drains 131b and 132b are respectively connected to the drains 126b and 123b of the transistors 126 and 123 of the current mirrors 124 and 121. In addition, the gates 131c and 132c of the transistors 131 and 132 as well as the drain 131b of the transistor 131 are connected together. The output 11c of the operational amplifier is formed of the connection node between the drain 132b of the transistor 132 and the drain 123b of the transistor 123.

A titre de seconde illustration, la figure 4 montre schématiquement un autre exemple d'un amplificateur opérationnel pouvant être utilisé comme moyen d'amplification 11 du circuit générateur de courant selon la présente invention.As a second illustration, Figure 4 schematically shows another example of an operational amplifier that can be used as a means amplification 11 of the current generator circuit according to the present invention.

L'amplificateur opérationnel illustré à la figure 4, repéré globalement par la référence numérique 11 conformément aux illustrations des figures 1 et 2, comporte ainsi une paire différentielle de transistors, repérée 210, comportant deux transistors p-MOS 211 et 212 dont les sources 211a et 212a sont connectées ensembles. Les grilles 211c et 212c des transistors de la paire différentielle 210 forment respectivement les bornes d'entrée 11a et 11b de l'amplificateur opérationnel 11.The operational amplifier illustrated in FIG. 4, generally identified by the reference numeral 11 in accordance with the illustrations of FIGS. 1 and 2, comprises thus a differential pair of transistors, marked 210, comprising two transistors p-MOS 211 and 212 whose sources 211a and 212a are connected together. The gates 211c and 212c of the transistors of the differential pair 210 form respectively the input terminals 11a and 11b of the operational amplifier 11.

Les sources 211a et 212a des transistors de la paire différentielle 210 sont connectées au drain 213b d'un transistor p-MOS 213 dont la source 213a est connectée au potentiel d'alimentation Vdd. La grille 213c de ce transistor 213 est commandée par une tension de polarisation VBIAS.The sources 211a and 212a of the transistors of the differential pair 210 are connected to the drain 213b of a p-MOS transistor 213 whose source 213a is connected to the supply potential Vdd. The gate 213c of this transistor 213 is controlled by a VBIAS bias voltage.

L'amplificateur opérationnel 11 de la figure 3, comporte par ailleurs un miroir de courant 220 comprenant deux transistors n-MOS 221 et 222. Les sources 221a, 222a de ces transistors sont connectées au potentiel d'alimentation ou masse Vss. Les grilles 221c et 222c des transistors 221, 222 ainsi que le drain 222b du transistor 222 sont connectés ensembles au drain 212b du second transistor 212 de la paire différentielle 210. Le drain 221b du transistor 221 est connecté au drain 211b du premier transistor 211 de la paire différentielle 210.The operational amplifier 11 of FIG. 3, moreover comprises a mirror current 220 comprising two n-MOS transistors 221 and 222. Sources 221a, 222a of these transistors are connected to the supply potential or ground Vss. The gates 221c and 222c of the transistors 221, 222 as well as the drain 222b of the transistor 222 are connected together to the drain 212b of the second transistor 212 of the pair differential 210. The drain 221b of the transistor 221 is connected to the drain 211b of the first transistor 211 of the differential pair 210.

L'amplificateur opérationnel 11 de la figure 4 comporte par ailleurs une branche connectée entre les potentiels d'alimentation Vdd et Vss comportant un transistor p-MOS 231 et un transistor n-MOS 232. La source 231a du transistor 231 est connectée au potentiel d'alimentation Vdd, alors que la grille 231c de ce transistor est connectée à la tension de polarisation VBIAS. La source 232a du transistor 232 est connectée au potentiel de masse Vss alors que la grille 232c de ce transistor est connectée au noeud de connexion entre le drain 211b du transistor 211 de la paire différentielle et le drain 221b du transistor 221 du miroir de courant 220. Les drains 231 b et 232b des transistors 231 et 232 sont connectés ensembles et forment la sortie 11c de l'amplificateur opérationnel.The operational amplifier 11 of FIG. 4 also includes a branch connected between the supply potentials Vdd and Vss comprising a p-MOS transistor 231 and an n-MOS transistor 232. The source 231a of transistor 231 is connected to the supply potential Vdd, while the gate 231c of this transistor is connected to the VBIAS bias voltage. Source 232a of transistor 232 is connected to the ground potential Vss while the gate 232c of this transistor is connected to the connection node between the drain 211b of the pair's transistor 211 differential and the drain 221b of the transistor 221 of the current mirror 220. The drains 231b and 232b of the transistors 231 and 232 are connected together and form the output 11c of the operational amplifier.

Les amplificateurs opérationnels illustrés aux figures 3 et 4 ne sont donnés ici qu'à titre d'exemple non limitatif afin d'illustrer le concept de la présente invention. Il va de soi que d'autres schéma d'amplificateurs opérationnels permettant de répondre aux objectifs de la présente invention peuvent être envisagés par l'homme du métier.The operational amplifiers illustrated in Figures 3 and 4 are not given here as a non-limiting example in order to illustrate the concept of the present invention. he goes self-evident as other operational amplifier schemes to respond the objectives of the present invention can be envisaged by those skilled in the art.

Que l'on choisisse l'un ou l'autre des exemples d'amplificateurs opérationnels des figures 3 et 4, ou un autre amplificateur opérationnel analogue, on s'assure d'une part, selon la présente invention, que l'amplificateur opérationnel travaille en faible inversion, c'est-à-dire que les transistors de la paire différentielle de l'amplificateur opérationnel 11, fonctionnent avec une tension grille-source inférieure à la tension de seuil de ces transistors.Whether we choose one or the other examples of operational amplifiers Figures 3 and 4, or another similar operational amplifier, we ensure that according to the present invention, the operational amplifier works at low inversion, that is to say that the transistors of the differential pair of the amplifier operational 11, operate with a gate-source voltage lower than the voltage of threshold of these transistors.

Afin d'assurer que les amplificateurs opérationnels des figures 3 et 4 fonctionnent en faible inversion, on agit par exemple sur le courant produit par le transistor 113, respectivement 213, de l'amplificateur opérationnel (voir figure 3 ou 4) par le biais de la tension de polarisation VBIAS appliquée sur la grille 113c, respectivement 213c, de ce transistor. En agissant de la sorte afin de faire fonctionner l'amplificateur opérationnel en faible inversion, on assure, comme on le verra plus tard, un comportement thermique sensiblement linéaire de la tension d'offset générée.To ensure that the operational amplifiers in Figures 3 and 4 operate in low inversion, we act for example on the current produced by the transistor 113, respectively 213, of the operational amplifier (see Figure 3 or 4) by means of the bias voltage VBIAS applied to the gate 113c, respectively 213c, of this transistor. By doing this to make it work the operational amplifier in low inversion, we ensure, as we will see more later, a substantially linear thermal behavior of the offset voltage generated.

Selon la présente invention, on agence d'autre part l'amplificateur opérationnel 11 afin qu'il présente une tension d'offset Vos(T) entre ses première et seconde bornes d'entrées 11a, 11b ayant une dépendance en température. Cette tension d'offset Vos(T) est ajustée selon la présente invention pour présenter une dépendance en température permettant de compenser la dépendance en température de la résistance 13.According to the present invention, on the other hand, the operational amplifier is arranged. 11 so that it has an offset voltage Vos (T) between its first and second input terminals 11a, 11b having a temperature dependence. This tension offset Vos (T) is adjusted according to the present invention to present a temperature dependence to compensate for temperature dependence resistance 13.

Pour produire cette tension d'offset Vos(T), on peut agir directement sur le rapport dimensionnel largeur sur longueur de canal W/L de chaque transistor de la paire différentielle. Plus spécifiquement, la tension d'offset Vos(T), en faible inversion, peut être exprimée sous la forme suivante : Vos (T) = kTq In X où X = (W/L)2 (W/L)1    T étant la température absolue en degrés Kelvin.To produce this offset voltage Vos (T), it is possible to act directly on the dimensional width to channel length ratio W / L of each transistor of the differential pair. More specifically, the offset voltage Vos (T), at low inversion, can be expressed in the following form: Your (T) = kT q In X or X = (W / L) 2 (W / L) 1 T being the absolute temperature in degrees Kelvin.

Les facteurs (W/L)1 et (W/L)2 sont définis comme les rapports largeur sur longueur de canal W/L des transistors formant la paire différentielle de l'amplificateur opérationnel 11.The factors (W / L) 1 and (W / L) 2 are defined as the width-to-channel length W / L ratios of the transistors forming the differential pair of the operational amplifier 11.

On constate aisément de l'expression (2) que la tension Vos(T) présente une dépendance sensiblement linéaire en température. De plus, selon que l'on agit sur les rapports dimensionnels W/L de l'un ou l'autre des transistors de la paire différentielle, on comprendra que l'on peut produire une tension d'offset Vos(T) ayant un coefficient de température positif ou négatif.It is easy to see from expression (2) that the tension Vos (T) presents a substantially linear temperature dependence. In addition, depending on whether one acts on the dimensional ratios W / L of one or the other of the transistors of the differential pair, we will understand that we can produce an offset voltage Vos (T) having a coefficient positive or negative temperature.

A titre d'exemple, par un choix tel que le rapport dimensionnel W/L de chaque transistor de la paire différentielle résulte en ce que le rapport X de l'expression (3) vaut sensiblement 16, la tension d'offset Vos(T) vaut, à une température de l'ordre de 300°K, environ 72 mV avec un coefficient de température d'environ +0.24 mV/°K.For example, by a choice such as the dimensional ratio W / L of each transistor of the differential pair results in the ratio X of expression (3) is worth substantially 16, the offset voltage Vos (T) is worth, at a temperature of the order of 300 ° K, approximately 72 mV with a temperature coefficient of approximately +0.24 mV / ° K.

On peut également réécrire l'expression (2) ci-dessus comme suit: Vos(T) = Vos,o + β(T - To) où Vos,o est la valeur de la tension d'offset à une température donnée To, par exemple 300°K, et β est le coefficient de température en V/°K de la tension d'offset.We can also rewrite expression (2) above as follows: Vos (T) = Vos, o + β (T - To) where Vos, o is the value of the offset voltage at a given temperature To, for example 300 ° K, and β is the temperature coefficient in V / ° K of the offset voltage.

De (2) et (4), on voit aisément que : β = kq In X et Vos,o = βTo From (2) and (4), we can easily see that: β = k q In X and Vos, o = βTo

En tenant compte de la présence de la tension d'offset Vos(T), l'expression (1) du courant I1 produit par le circuit générateur de courant devient alors : I1 = Vin + Vos(T)R(T) Taking into account the presence of the offset voltage Vos (T), the expression (1) of the current I1 produced by the current generator circuit then becomes: I1 = Wine + Vos (T) R (T)

La résistance R en fonction de la température peut quant à elle être exprimée comme suit : R(T) = Ro(1 + α(T - To)) où Ro est la valeur de résistance à la température To donnée et α est le coefficient de température en °K-1 de la résistance. Resistance R as a function of temperature can be expressed as follows: R (T) = Ro (1 + α (T - To)) where Ro is the resistance value at the given temperature To and α is the temperature coefficient in ° K -1 of the resistance.

De (4), (7) et (8), on arrive donc à la conclusion que pour produire un courant I1 sensiblement indépendant de la température, il est nécessaire que l'expression suivante soit sensiblement satisfaite : βVin + Vos, o = α From (4), (7) and (8), we therefore come to the conclusion that in order to produce a current I1 substantially independent of temperature, it is necessary that the following expression be substantially satisfied: β Wine + Vos, o = α

A titre d'exemple, pour compenser un coefficient de température de la résistance de l'ordre de + 0.1% °K-1 au moyen d'un amplificateur différentiel dont la paire différentielle présente un rapport X, selon l'expression (3) ci-dessus, valant sensiblement 16, c'est-à-dire avec Vos,o = 72 mV et β = 0.24 mV/°K, une tension Vin valant sensiblement 168 mV permet de satisfaire l'expression (9) ci-dessus.For example, to compensate for a temperature coefficient of resistance of the order of + 0.1% ° K -1 by means of a differential amplifier whose differential pair has an X ratio, according to expression (3) above, being substantially equal to 16, that is to say with Vos, o = 72 mV and β = 0.24 mV / ° K, a voltage Vin being substantially equal to 168 mV makes it possible to satisfy expression (9) above .

Afin de produire, une telle tension d'entrée, il est par exemple possible de diviser une tension de référence stable en température telle une tension de bandgap VBG du facteur adéquat, par exemple par un diviseur résistif R1, R2 comme illustré dans la figure 5. Avantageusement, il convient de pouvoir ajuster le facteur de division de la tension de bandgap VBG, par exemple au moyen d'un ajustement de la valeur de l'une des résistances R1, R2 du diviseur résistif, par exemple au moyen d'une résistance R2 réglable.In order to produce such an input voltage, it is for example possible to divide a temperature-stable reference voltage such as a bandgap voltage GBV of the adequate factor, for example by a resistive divider R1, R2 as illustrated in Figure 5. Advantageously, it should be possible to adjust the division factor of the VBG bandgap voltage, for example by means of an adjustment of the value of one of the resistors R1, R2 of the resistive divider, for example by means of a adjustable R2 resistance.

La figure 5 montre ainsi un exemple schématique de mise en oeuvre de la présente invention constituant une source de courant. Cette source de courant est sensiblement analogue à la source de courant conventionnelle illustrée en figure 2. On ne décrira pas à nouveau les éléments déjà présentés en référence à la figure 2, à savoir l'amplificateur opérationnel 11, le transistor MOS 12, la résistance 13 et le miroir de courant 30 permettant de générer un deuxième courant 12 image du courant I1 parcourant la branche drain-source du transistor 12.FIG. 5 thus shows a schematic example of implementation of the present invention constituting a current source. This current source is substantially similar to the conventional current source illustrated in Figure 2. The elements already presented with reference to FIG. 2 will not be described again. know the operational amplifier 11, the MOS transistor 12, the resistor 13 and the current mirror 30 making it possible to generate a second current 12 image of the current I1 traversing the drain-source branch of transistor 12.

Comme déjà mentionné, le circuit de la figure 5 comporte un diviseur résistif comprenant deux résistances R1 et R2 connectées en série entre, d'une part, une tension de référence stable en température, telle une tension de bandgap VBG, et, d'autre part, la tension d'alimentation ou masse Vss. L'entrée positive 11a de l'amplificateur opérationnel 11 est connectée entre les deux résistances R1 et R2 de sorte que la valeur de la tension d'entrée Vin appliquée sur cette borne d'entrée 11a est déterminée dans un rapport R1/R2 de la tension de référence VBG. Les valeurs des résistances R1 et R2 sont déterminées pour produire une tension d'entrée adéquate Vin permettant de satisfaire l'objectif recherché amplement discuté précédemment.As already mentioned, the circuit of Figure 5 includes a resistive divider comprising two resistors R1 and R2 connected in series between, on the one hand, a reference voltage stable in temperature, such as a bandgap voltage VBG, and, on the other hand, the supply voltage or ground Vss. The positive entry 11a of the operational amplifier 11 is connected between the two resistors R1 and R2 of so that the value of the input voltage Vin applied to this input terminal 11a is determined in a ratio R1 / R2 of the reference voltage VBG. Values resistors R1 and R2 are determined to produce an input voltage adequate Wine allowing to meet the objective widely discussed previously.

On notera bien évidemment que le diviseur résistif formé des résistances R1, R2 n'affecte nullement la stabilité en température de la tension de référence VBG. On notera de plus que l'homme du métier peut parfaitement envisager d'autres solutions équivalentes permettant de diviser la tension de référence de bandgap VBG pour produire une valeur adéquate de tension d'entrée Vin, par exemple au moyen d'un diviseur capacitif.It will of course be noted that the resistive divider formed by resistors R1, R2 does not affect the temperature stability of the reference voltage VBG in any way. We will also note that the skilled person can perfectly consider other solutions equivalents for dividing the reference voltage of bandgap VBG for produce an adequate value of input voltage Vin, for example by means of a capacitive divider.

On comprendra que diverses modifications peuvent être apportées au procédé et au dispositif décrits dans la présente description sans sortir du cadre de l'invention. En particulier, on rappellera notamment que les exemples d'amplificateurs opérationnels des figures 3 et 4 pouvant être utilisés et modifiés selon la présente invention pour répondre au problème posé ne sont nullement limitatif et que tout autre amplificateur opérationnel susceptible de fonctionner en faible inversion peut être utilisé dans le cadre de la présente invention.It will be understood that various modifications can be made to the process. and to the device described in the present description without departing from the scope of the invention. In particular, it will be recalled in particular that the examples of amplifiers Figures 3 and 4 can be used and modified according to this invention to address the problem posed are in no way limiting and that any other operational amplifier capable of operating at low inversion can be used in the context of the present invention.

Claims (13)

Procédé de génération d'un courant (11) au moyen d'un circuit générateur de courant (10) couplé à des première et seconde tensions d'alimentation (Vss, Vdd) comportant : un moyen d'amplification (11) pour fournir une tension de commande à une sortie (11c) dudit moyen d'amplification (11) en réponse à une différence entre des première (Vin) et seconde tensions d'entrée appliquées respectivement à des première (11a) et seconde (11b) bornes d'entrée dudit moyen d'amplification (11); un premier transistor (12) ayant une première électrode de courant (12a), une électrode de commande (12c) connectée à ladite sortie (11c) du moyen d'amplification (11) pour recevoir ladite tension de commande, et une seconde électrode de courant (12b) couplée à ladite seconde tension d'alimentation (Vdd); et un moyen formant résistance (13) ayant une première borne connectée à ladite seconde borne d'entrée (11b) du moyen d'amplification (11) ainsi qu'à ladite première électrode de courant (12a) dudit transistor (12), et une seconde borne connectée à ladite première tension d'alimentation (Vss), ce moyen formant résistance (13) ayant une valeur de résistance (R(T)) présentant une dépendance en température, ce circuit générateur de courant (10) générant un premier courant (11) au travers desdites première et seconde électrodes de courant (12a, 12b) dudit premier transistor (12) sensiblement proportionnel à ladite première tension d'entrée (Vin),
   caractérisé en ce que ladite première tension d'entrée (Vin) est une tension sensiblement stable en température, en ce que l'on fait fonctionner ledit moyen d'amplification (11) en faible inversion, et en ce que l'on agence ledit moyen d'amplification (11) afin qu'il présente une tension d'offset (Vos(T)) entre ses dites première et seconde bornes d'entrées (11a, 11b) ayant une dépendance en température, cette tension d'offset (Vos(T)) ainsi que ladite première tension d'entrée (Vin) étant ajustées pour compenser sensiblement la dépendance en température dudit moyen formant résistance (13) de telle sorte que ledit premier courant généré (I1) est sensiblement indépendant de la température.Method for generating a current (11) by means of a current generator circuit (10) coupled to first and second supply voltages (Vss, Vdd) comprising: amplification means (11) for supplying a control voltage to an output (11c) of said amplification means (11) in response to a difference between first (Vin) and second input voltages respectively applied to first (11a) and second (11b) input terminals of said amplification means (11); a first transistor (12) having a first current electrode (12a), a control electrode (12c) connected to said output (11c) of the amplification means (11) for receiving said control voltage, and a second electrode current (12b) coupled to said second supply voltage (Vdd); and resistor means (13) having a first terminal connected to said second input terminal (11b) of the amplifier means (11) as well as to said first current electrode (12a) of said transistor (12), and a second terminal connected to said first supply voltage (Vss), this resistor means (13) having a resistance value (R (T)) having a temperature dependence, this current generator circuit (10) generating a first current (11) through said first and second current electrodes (12a, 12b) of said first transistor (12) substantially proportional to said first input voltage (Vin),
characterized in that said first input voltage (Vin) is a voltage that is substantially stable in temperature, in that said amplification means (11) are operated in low inversion, and in that said arrangement is arranged amplification means (11) so that it has an offset voltage (Vos (T)) between its said first and second input terminals (11a, 11b) having a temperature dependence, this offset voltage ( Vos (T)) as well as said first input voltage (Vin) being adjusted to substantially compensate for the temperature dependence of said resistor means (13) so that said first generated current (I1) is substantially independent of temperature. Procédé selon la revendication 1, caractérisé en ce que ledit moyen d'amplification (11) est un amplificateur opérationnel comportant une paire différentielle (110; 210) de transistors (111, 112; 211, 212) dont les électrodes de commande (111c, 112c; 211c, 212c) forment respectivement lesdites première et seconde bornes d'entrée (11a, 11b) du moyen d'amplification (11), et en ce que l'on génère ladite tension d'offset (Vos(T)) en agissant sur la géométrie de ladite paire différentielle (110; 210) de transistors (111, 112; 211, 212).Method according to claim 1, characterized in that said amplification means (11) is an operational amplifier comprising a differential pair (110; 210) of transistors (111, 112; 211, 212), the control electrodes (111c, 112c; 211c, 212c) respectively form said first and second input terminals (11a, 11b) of the amplification means (11), and in that one generates said offset voltage (Vos (T)) in acting on the geometry of said differential pair (110; 210) of transistors (111, 112; 211, 212). Procédé selon la revendication 2, caractérisé en ce que l'on génère ladite tension d'offset (Vos(T)) en agissant sur le rapport largeur sur longueur de canal W/L des transistors (111, 112; 211, 212) de ladite paire différentielle (110; 210).Method according to claim 2, characterized in that the said offset voltage (Vos (T)) is generated by acting on the width to channel length ratio W / L of the transistors (111, 112; 211, 212) of said differential pair (110; 210). Procédé selon la revendication 3, caractérisé en ce que ladite tension d'offset (Vos(T)) est donnée par l'expression suivante : Vos (T) = kTq InX où X = (W/L)2 (W/L1) (W/L)1 et (W/L)2 étant définis comme les rapports largeur sur longueur de canal W/L des transistors (111, 112; 211, 212) formant ladite paire différentielle (110; 210), le facteur X et ladite première tension d'entrée (Vin) étant ajustés pour compenser la dépendance en température dudit moyen formant résistance (13) de sorte que ledit premier courant (I1) donné par l'expression suivante : I1 = Vin + Vos(T)R(T) est sensiblement indépendant de la température.Method according to claim 3, characterized in that said offset voltage (Vos (T)) is given by the following expression: Your (T) = kT q InX or X = (W / L) 2 (W / L 1 ) (W / L) 1 and (W / L) 2 being defined as the width to channel length ratios W / L of the transistors (111, 112; 211, 212) forming said differential pair (110; 210), the factor X and said first input voltage (Vin) being adjusted to compensate for the temperature dependence of said resistance means (13) so that said first current (I1) given by the following expression: I1 = Wine + Vos (T) R (T) is substantially independent of temperature. Circuit générateur de courant couplé à des première et seconde tensions d'alimentation (Vss, Vdd) comportant : un moyen d'amplification (11) pour fournir une tension de commande à une sortie (11c) dudit moyen d'amplification (11) en réponse à une différence entre des première (Vin) et seconde tensions d'entrée appliquées respectivement à des première (11a) et seconde (11b) bornes d'entrée dudit moyen d'amplification (11); un premier transistor (12) ayant une première électrode de courant (12a), une électrode de commande (12c) connectée à ladite sortie (11c) du moyen d'amplification (11) pour recevoir ladite tension de commande, et une seconde électrode de courant (12b) couplée à ladite seconde tension d'alimentation (Vdd); et un moyen formant résistance (13) ayant une première borne connectée à ladite seconde borne d'entrée (11b) du moyen d'amplification (11) ainsi qu'à ladite première électrode de courant (12a) dudit transistor (12), et une seconde borne connectée à ladite première tension d'alimentation (Vss), ce moyen formant résistance (13) présentant une dépendance en température, ce circuit générateur de courant (10) générant un premier courant (11) au travers desdites première et seconde électrodes de courant (12a, 12b) dudit premier transistor (12) sensiblement proportionnel à ladite première tension d'entrée (Vin),
   caractérisé en ce que ladite première tension d'entrée (Vin) est une tension sensiblement stable en température, et en ce que ledit moyen d'amplification (11) est agencé pour fonctionner en faible inversion et présente une tension d'offset (Vos(T)) entre ses dites première et seconde bornes d'entrées (11a, 11b) ayant une dépendance en température, cette tension d'offset (Vos(T)) ainsi que ladite première tension d'entrée (Vin) étant ajustées pour compenser la dépendance en température dudit moyen formant résistance (13) de telle sorte que ledit premier courant généré (I1) est sensiblement indépendant de la température.Current generator circuit coupled to first and second supply voltages (Vss, Vdd) comprising: amplification means (11) for supplying a control voltage to an output (11c) of said amplification means (11) in response to a difference between first (Vin) and second input voltages respectively applied to first (11a) and second (11b) input terminals of said amplification means (11); a first transistor (12) having a first current electrode (12a), a control electrode (12c) connected to said output (11c) of the amplification means (11) for receiving said control voltage, and a second electrode current (12b) coupled to said second supply voltage (Vdd); and resistor means (13) having a first terminal connected to said second input terminal (11b) of the amplifier means (11) as well as to said first current electrode (12a) of said transistor (12), and a second terminal connected to said first supply voltage (Vss), this resistance-forming means (13) having a temperature dependence, this current generator circuit (10) generating a first current (11) through said first and second current electrodes (12a, 12b) of said first transistor (12) substantially proportional to said first input voltage (Vin),
characterized in that said first input voltage (Vin) is a voltage that is substantially stable in temperature, and in that said amplification means (11) is arranged to operate at low inversion and has an offset voltage (Vos ( T)) between its said first and second input terminals (11a, 11b) having a temperature dependence, this offset voltage (Vos (T)) as well as said first input voltage (Vin) being adjusted to compensate the temperature dependence of said resistor means (13) so that said first generated current (I1) is substantially independent of temperature. Circuit générateur de courant selon la revendication 5, caractérisé en ce que ledit moyen d'amplification (11) est un amplificateur opérationnel comportant une paire différentielle (110; 210) de transistors (111, 112; 211, 212) dont les électrodes de commande (111c, 112c; 211c, 212c) forment respectivement lesdites première et seconde bornes d'entrée (11a, 11b) du moyen d'amplification (11), et en ce que la géométrie de ladite paire différentielle (110; 210) de transistors (111, 112; 211, 212) est agencée pour produire ladite tension d'offset (Vos(T)).Current generator circuit according to claim 5, characterized in that said amplification means (11) is an operational amplifier comprising a differential pair (110; 210) of transistors (111, 112; 211, 212), the control electrodes of which (111c, 112c; 211c, 212c) respectively form said first and second input terminals (11a, 11b) of the amplification means (11), and in that the geometry of said differential pair (110; 210) of transistors (111, 112; 211, 212) is arranged to produce said offset voltage (Vos (T)). Circuit générateur de courant selon la revendication 6, caractérisé en ce que ladite tension d'offset (Vos(T)) est produite en agissant sur le rapport largeur sur longueur de canal W/L des transistors (111, 112; 211, 212) de ladite paire différentielle (110; 210).Current generator circuit according to claim 6, characterized in that said offset voltage (Vos (T)) is produced by acting on the width to channel length ratio W / L of the transistors (111, 112; 211, 212) of said differential pair (110; 210). Circuit générateur de courant selon la revendication 7, caractérisé en ce que ladite tension d'offset (Vos(T)) est donnée par l'expression suivante : Vos(T) = kTq In X où X = (W/L)2 (W/L)1 (W/L)1 et (W/L)2 étant définis comme les rapports largeur sur longueur de canal W/L des transistors (111, 112; 211, 212) formant ladite paire différentielle (110; 210), le facteur X et ladite première tension d'entrée (Vin) étant ajustés pour compenser la dépendance en température dudit moyen formant résistance (13) de sorte que ledit premier courant (I1) donné par l'expression suivante : I1 = Vin + Vos(T)R(T) est sensiblement indépendant de la température.Current generator circuit according to claim 7, characterized in that said offset voltage (Vos (T)) is given by the following expression: Your (T) = kT q In X or X = (W / L) 2 (W / L) 1 (W / L) 1 and (W / L) 2 being defined as the width to channel length W / L ratios of the transistors (111, 112; 211, 212) forming said differential pair (110; 210), the factor X and said first input voltage (Vin) being adjusted to compensate for the temperature dependence of said resistance means (13) so that said first current (I1) given by the following expression: I1 = Wine + Vos (T) R (T) is substantially independent of temperature. Circuit générateur de courant selon l'une quelconque des revendications 5 à 8, caractérisé en ce que ladite première tension d'entrée (Vin) est dérivée d'une tension de référence de bandgap (VBG). Current generator circuit according to any one of claims 5 to 8, characterized in that said first input voltage (Vin) is derived from a bandgap reference voltage (VBG). Circuit générateur de courant selon l'une quelconque des revendications 5 à 9, caractérisé en ce que ledit transistor (12) est un transistor MOS à effet de champ de type n.Current generator circuit according to any one of claims 5 to 9, characterized in that said transistor (12) is an MOS n-type field effect transistor. Circuit générateur de courant selon l'une quelconque des revendications 5 à 10, caractérisé en ce que ledit circuit comporte en outre un miroir de courant (30) comprenant des second (31) et troisième (32) transistors comportant chacun une électrode de commande (31c, 32c) et des première (31a, 32a) et seconde (31b, 32b) électrodes de courant, lesdites premières électrodes de courant (31a, 32a) des second et troisième transistors (31, 32) étant connectées à ladite seconde tension d'alimentation (Vdd), lesdites électrodes de commande (31 c, 32c) des second et troisième transistors (31, 32) ainsi que ladite seconde électrode de courant (31 b) du deuxième transistor (31) étant connectées à ladite seconde électrode de courant (12b) dudit premier transistor (12), ledit miroir de courant (30) produisant, au travers desdites première et seconde électrodes de courant (32a, 32b) du troisième transistor (32), un second courant (12) image dudit premier courant (I1).Current generator circuit according to any one of Claims 5 to 10, characterized in that the said circuit further comprises a current mirror (30) comprising second (31) and third (32) transistors each comprising a control electrode ( 31c, 32c) and first (31a, 32a) and second (31b, 32b) current electrodes, said first current electrodes (31a, 32a) of the second and third transistors (31, 32) being connected to said second voltage d power supply (Vdd), said control electrodes (31 c, 32c) of the second and third transistors (31, 32) as well as said second current electrode (31 b) of the second transistor (31) being connected to said second electrode current (12b) of said first transistor (12), said current mirror (30) producing, through said first and second current electrodes (32a, 32b) of the third transistor (32), a second current (12) image of said first current (I1). Circuit générateur de courant selon la revendication 10, caractérisé en ce que lesdits second et troisième transistors (31, 32) sont des transistors MOS à effet de champ de type p.Current generator circuit according to claim 10, characterized in that said second and third transistors (31, 32) are p-type field effect MOS transistors. Circuit générateur de courant selon l'une quelconque des revendications 5 à 12, caractérisé en ce que ledit moyen formant résistance (13) est une résistance intégrée.Current generator circuit according to any one of Claims 5 to 12, characterized in that the said resistor means (13) is an integrated resistor.
EP00202059A 2000-06-13 2000-06-13 Process and device for generating a temperature independent current Expired - Lifetime EP1164455B1 (en)

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EP00202059A EP1164455B1 (en) 2000-06-13 2000-06-13 Process and device for generating a temperature independent current
AT00202059T ATE328313T1 (en) 2000-06-13 2000-06-13 METHOD AND DEVICE FOR GENERATING A TEMPERATURE-INDEPENDENT CURRENT
DE60028356T DE60028356T2 (en) 2000-06-13 2000-06-13 Method and device for generating a temperature-independent current

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EP00202059A EP1164455B1 (en) 2000-06-13 2000-06-13 Process and device for generating a temperature independent current

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Citations (4)

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Publication number Priority date Publication date Assignee Title
US5805004A (en) * 1995-03-07 1998-09-08 Robert Bosch Gmbh Integrated circuit arrangement for minimizing the temperature-dependant offset voltage of an amplifier
JPH10284949A (en) * 1997-04-02 1998-10-23 Asahi Kasei Micro Syst Kk Circuit provided with operational amplifier with offset temperature drift compensation function and offset temperature drift compensation method
US5933051A (en) * 1993-06-08 1999-08-03 Kabushiki Kaisha Toshiba Constant-voltage generating device
US5982226A (en) * 1997-04-07 1999-11-09 Texas Instruments Incorporated Optimized frequency shaping circuit topologies for LDOs

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5933051A (en) * 1993-06-08 1999-08-03 Kabushiki Kaisha Toshiba Constant-voltage generating device
US5805004A (en) * 1995-03-07 1998-09-08 Robert Bosch Gmbh Integrated circuit arrangement for minimizing the temperature-dependant offset voltage of an amplifier
JPH10284949A (en) * 1997-04-02 1998-10-23 Asahi Kasei Micro Syst Kk Circuit provided with operational amplifier with offset temperature drift compensation function and offset temperature drift compensation method
US5982226A (en) * 1997-04-07 1999-11-09 Texas Instruments Incorporated Optimized frequency shaping circuit topologies for LDOs

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 01 29 January 1999 (1999-01-29) *

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DE60028356D1 (en) 2006-07-06
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DE60028356T2 (en) 2007-05-31

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