Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Definitions

• the invention relates to a method for generating a random signal and a random signal generator.
• a random signal generator which has a non-deterministic random sequence generator which has a voltage-controlled oscillator whose frequency control input is connected to a noise voltage source.
• the oscillator At its output, the oscillator has an oscillator signal, the frequency of which fluctuates randomly around a center frequency in accordance with the stochastically changing noise voltage present at the frequency control input.
• the random sequence generator has several dynamic flip-flops, each of which is connected with its data input to a ring oscillator assigned to them. A separate ring oscillator is provided for each flip-flop, the frequencies of these ring oscillators differing somewhat from one another and each being greater than the frequency of the voltage-controlled oscillator of the random signal generator.
• the clock inputs of the flip-flops are each connected to the output of the random signal generator, so that a signal value of the individual oscillation signals of the ring oscillators is sampled on a clock edge of the oscillation signal of the voltage-controlled oscillator, which frequency changes randomly, and into that of the ring oscillator in question assigned flip-flop is read.
• the signal values temporarily stored in the individual flip-flops are then each output at an output of the flip-flops and form the random signal to be generated.
• the signals present at the outputs of the flip-flops each represent a binary digit of a random number to be generated which has several digits.
• the binary values of the digit signals present at the output of the flip-flops should be equally distributed, that is to say called Outputs of the flip-flops should each deliver an approximately equal number of logical "ones" and "zeros".
• the known random number generator has the disadvantage that the individual digit signals or the binary digits of the random number assigned to them still have a certain dependency on one another. A correlation of two random numbers can also occur, which are read out from the random signal generator in immediate succession. An observer can therefore deduce the properties of the random signal or random number generator, in particular the properties of the ring oscillators contained therein, by observing the random numbers output by the random number generator for a correspondingly long time. It is also disadvantageous that a defect in the noise voltage source and / or the voltage-controlled oscillator of the random signal generator can result in the voltage-controlled oscillator oscillating at a constant frequency, so that the correlation of the random numbers then increases sharply, i.e.
• the randomness of the random signal or the random numbers represented by this signal decreases without the user of the random number generator noticing.
• a pseudo-random number generator which has several deterministic random sequence generators, each of which has an output for a pseudo-random signal. These outputs are each connected to an input of a combination device, which is an output for a non-linear combination of the pseudo-random signals formed combination signal.
• the combination signal output is connected to the data input of a shift register having a plurality of memory elements, into which the data read out from the combination signal output can be read sequentially.
• the data outputs of the memory elements of the shift register are each connected to an input of a non-linear logic device. This has an output for a signal which is formed by a non-linear combination of the data signals present at the data outputs of the memory elements of the shift register.
• the known pseudo-random number generator has the disadvantage that the signal present at the output of the logic device can be described by a mathematical function despite the comparatively complex combination of several pseudo-random signals to form a random number signal.
• the random numbers generated with the random number generator can therefore be predicted when this mathematical function and the state of the random signal generator are known. It is also unfavorable that the random signal generator still has a comparatively complicated structure.
• a random signal generator is also already known, in which an analog noise signal from a noise source is amplified with a high-frequency amplifier and the signal level of this amplifier is then digitized. The random number to be generated is then read out sequentially at the output of the high-frequency amplifier, the two signal levels defined by the digitization of the amplifier output signal as
• Binary values of a binary number can be interpreted.
• this random signal generator is also relatively expensive, since to avoid correlations between the digital output signal of the random signal generator and the analog one Noise signal a complex shielding of the high frequency amplifier is required.
• the noise source must be shielded from external electromagnetic interference.
• the solution to this problem with regard to the method is that at least two random sequence signals are generated and exclusively-or-linked by means of at least two non-deterministic random sequence generators and that the exclusive-OR output signal forms the random signal or an intermediate signal for further processing.
• the exclusive-or output signal as an intermediate signal is exclusively-or-linked as an intermediate signal with the random sequence signal of at least one further non-deterministic random sequence generator and the exclusive-or output signal of this combination forms the random signal or an intermediate signal for further processing.
• the statistical distribution of the signal levels or Random values of the generated random signal are then even better approximated to a uniform distribution.
• a random signal value is determined from the intermediate signal by supplying this intermediate signal to an exclusive-OR gate and a buffered output signal of the exclusive-OR gate. Random sequence signal values generated at different times are thus exclusively-or-linked to one another, whereby an even greater randomness of the signal levels or random values of the generated random signal is achieved.
• the above-mentioned object can also be achieved in that at least two random sequence signals are generated by means of at least two non-deterministic random sequence generators, a) that a random signal value is determined in each case from each of the random sequence signals of the individual random sequence generators and exclusively with a memory value assigned to another random sequence generator. or-is linked, b) the result of this combination is temporarily stored as a new storage value assigned to the first-mentioned random sequence generator, c) that method steps a) and b) are repeated at least once again as a loop d) and that the individual random sequence generator Ren assigned memory values are output as a random signal.
• a plurality of random sequence signals are thus generated with the aid of different random sequence generators, these random sequence signals being linked to one another by means of exclusive or combinations in accordance with method steps a) to d) be combined.
• a random signal can advantageously be provided which has a greater randomness than the individual random sequence signals from which the random signal was mixed.
• the method therefore makes it possible to determine random numbers or random signals using a plurality of comparatively simple random signal generators which are practically not correlated with one another and whose frequency is distributed almost equally.
• the random sequence generators are each reset to a defined state before processing step a) again. As a result, the correlation of two signal values of the random signal determined immediately one after the other can additionally be reduced.
• a preferred embodiment of the method provides that in order to generate the random sequence signals of the random sequence generators, the frequency of a voltage-controlled oscillator is changed by means of a noise voltage signal, and that the random signal value is determined in each case from the oscillator signal of the oscillator.
• the random signals can thereby be generated in a simple manner with a comparatively good uniform distribution of their random signal values. It is particularly advantageous if a defined period of time, which is equal to or greater than the period of the oscillator signal, is waited for before processing step a) is repeated.
• the waiting time can, for example, be longer than ten times the period. Random signal values or random numbers determined successively or successively from the random signal then have an even lower correlation with one another.
• the random signal generator has at least two non-deterministic random sequence generators and at least one exclusive-OR gate, that the inputs of the exclusive-OR gate are connected to random sequence generators that supply random sequence signals, and that the output of the Exclusive-OR gate is connected directly or indirectly via an intermediate stage for further processing of the exclusive-OR gate output signal to a random signal output of the random signal generator.
• the random signal generated by the random signal generator advantageously has a greater randomness than the individual random sequence signals from which the random signal was mixed. Thus, even when using simply constructed random sequence generators, a good approximation of the statistical distribution of the signal levels or random values of the generated random signal to a uniform distribution can be achieved.
• the intermediate stage has an exclusive-OR gate, one input of which is connected to the output of the exclusive-OR gate connected to the random sequence generators and the other input of which is connected to the random sequence signal output of a further random sequence generator, and if the output of this Exclusive OR gate directly or indirectly via an intermediate stage for further processing of the exclusive-OR gate output signal is connected to the random signal output of the random signal generator.
• the statistical distribution of the signal levels or random values of the random signal generated by means of the random signal generator is then even more closely approximated to a uniform distribution.
• the intermediate stage has an exclusive-OR gate, one input of which is connected directly or indirectly via a further intermediate stage to the output of the exclusive-OR gate connected to the random sequence generators, and that to the A memory element is connected to the output of the first-mentioned exclusive-OR gate, the output of which is connected via a feedback loop to the second input of this exclusive-OR gate.
• the random signal generator has at least two function groups, each of which has a non-deterministic random sequence generator, an exclusive-OR gate and a memory element, the exclusive-OR gate of each functional group each having one its two inputs are connected to a random sequence signal output of the random sequence generator of the functional group and its other input is connected to a data output of the memory element of the functional group, the output of the exclusive-OR gate of each functional group being connected to the data input of the memory element of the functional group, and wherein the storage elements of the functional groups for moving their Memory contents are interconnected via data lines.
• the signal values of the random signal to be generated are thus advantageously formed from the random signal values of a plurality, preferably all, of the random sequence generators, as a result of which the signal values of the random signal are more random than the random signal values determined from the random sequence signals of the random sequence generators.
• the random signal generator therefore enables the determination of random signals with an almost perfectly equally distributed frequency of their signal values, even if the frequency of the random sequence signal values of the individual random sequence generators - as is always the case in practice - deviates from the ideal uniform distribution.
• random signal values determined in succession with the random signal generator have only a very low correlation.
• the individual random sequence generators of the random signal generator can therefore have a comparatively simple structure, which overall results in a simply constructed and inexpensive to produce random signal generator.
• a good even distribution of the frequency of the random signal values and a low correlation between the individual random signal values can still be achieved if one of the random sequence generators should fail or if for other reasons, for example due to environmental influences
• the random signal generator therefore has a high level of operational reliability.
• the random signal generator has at least two function groups, each have a random sequence generator, an exclusive-OR gate and a memory element, the exclusive-OR gate of each function group each having one of its two inputs with a random sequence signal output of the random sequence generator of the function group and with its other input having a data output of the memory element of another Function group is connected, and wherein the output of the exclusive-OR gate is connected to the data input of the memory element of the first-mentioned function group.
• this solution also has the advantage that additional data lines for shifting the memory contents between the memory elements can be omitted.
• One embodiment of the invention provides that the storage element or the storage elements are part of a ring shift register.
• the memory contents of the memory elements can then be shifted cyclically in a simple manner after each exclusive-OR combination of the random signal values with the memory contents in the ring memory. It is even possible for the ring shift register to have buffer elements in addition to the memory elements of the function groups. Additional digits of a random number to be determined can then be buffered in the buffer elements. The number or number of digits of the individual random numbers can then be greater than the number of random sequence generators of the random signal generator.
• the random signal generators have a reset input by means of which the random signals of the random sequence generators can be converted into a defined state.
• the random sequence generators can then each have a defined one before determining a new random number Be brought to the initial state, whereby the correlation between successively determined random numbers is reduced.
• the random sequence generators each have a voltage-controlled oscillator whose frequency control input is connected to a noise voltage source, the oscillator output being connected to the random sequence signal output of the random sequence generator.
• the random sequence signals can thereby be generated in a simple manner and with a comparatively good uniform distribution of the frequency of their random sequence signal values.
• the oscillator output is connected to the input of a flip-flop or similar frequency divider and if the output of the flip-flop is connected to the random sequence signal output of the random sequence generator.
• the flip-flop then inverts its output signal with each clock pulse of the oscillator, as a result of which a better uniform distribution of the random signal values determined from the random signal values present at the output of the random signal generator is achieved.
• the random signal generator can then be produced particularly cost-effectively and can be designed, for example, as a plug-in card which has a bus connection for connection to the system bus of a microcomputer.
• Fig. 1, 2 is a circuit diagram of a random signal generator having a plurality of random sequence generators, of which but only three are shown
• 3, 5 is a circuit diagram of a random signal generator which has a plurality of function groups and a plurality of intermediate storage elements, only three of the functional groups and only one of the intermediate storage elements being shown,
• FIG. 4 shows a modification of the circuit diagram according to FIG. 3, the random signal generator having a serial random signal output instead of the parallel random signal output shown in FIG. 3,
• FIG. 6 shows a modification of the circuit diagram according to FIG. 5, the random signal generator having a serial random signal output instead of the parallel random signal output shown in FIG. 5, and
• Fig. 7 is a block diagram of the random signal generator.
• the random signal generator shown in FIG. 1, generally designated 10, has a plurality of non-deterministic random sequence generators 30a, 30b, 30c and a number of exclusive-OR gates 40a, 40b, 40c.
• the random sequence signal output 70a of the random sequence generator 30a is connected to a first input 60a and the random sequence signal output 70b of the random sequence generator 30b is connected to a second input 60a of the exclusive-OR gate 40a.
• the intermediate signal present at the output 100a of the exclusive-OR gate 40a, formed by mixing the random sequence signals of the two random sequence generators 30a, 30b, has a greater random content than each of the two random sequence signals present at the inputs 60a, 80a.
• the intermediate signal is connected directly or indirectly via at least one intermediate stage, not shown in the drawing, for further processing of the intermediate signal to the first input 60b of the exclusive-OR gate 40b.
• the second input 80b of this exclusive-OR gate 40b is connected to the random sequence signal output 70c of a further random sequence generator 30b.
• the random signal present at the output 100b of the exclusive-OR gate 40b connected to an output terminal of the random signal generator 10 has a greater random content than each of the random sequence signal outputs 70a, 70b, 70c. This results in a good approximation of the distribution of the signal values of the random signal to a uniform distribution.
• At least one intermediate stage can be arranged between the output 100a of the exclusive-OR gate 40a and the input 60b of the exclusive-OR gate 40b, or a plurality of intermediate stages connected in series can be provided.
• the construction of these intermediate stages corresponds in each case to the arrangement formed by the exclusive-OR gate 40b and the random sequence generator 30c, with one input of the exclusive-OR gate of the intermediate stage in each case with the output of the exclusive-OR gate and connected upstream in series the output of the exclusive-OR gate of the intermediate stage is connected to an input of the exclusive-OR gate connected in series in the row.
• the exclusive-OR gate 40b can be followed by an intermediate stage which has a further exclusive-OR gate 40c, the first input 60c of which is connected to the output 100b of the exclusive-OR gate 40b.
• the data input of a memory element 50 is connected to the output of the exclusive-OR gate 40c, whose output is connected to the second input 80c via a feedback loop Exclusive-OR gate 40c is connected. This measure ensures that random sequence values generated by the random sequence generators 30a, 30b, 30c or signals derived therefrom are mixed with one another in time.
• the data output of the memory element 50 is connected to the random signal output of the random signal generator 10.
• a non-deterministic random sequence generator 3a, 3b, 3c an exclusive-OR gate 4a, 4b, 4c and a memory element 5a, 5b, 5c.
• the exclusive-OR gate 4a, 4b, 4c of each function group 2a, 2b, 2c is in each case with one of its two inputs 6a, 6b, 6c with a random signal output 7a, 7b, 7c of the random sequence generator 3a , 3b, 3c of the function group 2a, 2b, 2c and with its other input 8a, 8b, 8c connected to a data output 9a, 9b, 9c of the memory element 5a, 5b, 5c of the function group 2a, 2b, 2c.
• the memory elements 5a, 5b, 5c are part of a ring shift register and that this additionally also has intermediate memory elements 12 which are connected to the memory elements 5a, 5b, 5c of the function groups 2a, 2b, 2c by means of data lines 13 Ring are connected.
• the storage values stored in the storage elements 5a, 5b, 5c can be cyclically shifted in the ring shift register by means of the data lines 13.
• the memory elements 5a, 5b, 5c and the intermediate memories 12 are each preset with a predetermined memory value, for example a logic 0 or a logic 1. From the Random signal of each of the random sequence generators 3a, 3b, 3c, a random sequence signal value is determined in each case, for example by sampling the random sequence signal.
• the signal corresponding to this random sequence signal value and present at the random signal output 7a, 7b, 7c of a function group 2a, 2b, 2c is in each case associated with the memory value stored in the memory element 5a, 5b, 5c of the function group 2a, 2b, 2c
• Data output 9a, 9b, 9c present data signal in the gate 4a, 4b, 4c exclusive-OR-linked.
• the result of this combination is stored by means of the data input 11a, 11b, 11c as a new storage value in the respective storage element 5a, 5b, 5c of the relevant function group 2a, 2b, 2c.
• the memory values in the ring memory formed by the memory elements 5a, 5b, 5c and the intermediate memory elements 12 are then shifted to the right by a number of digits or bits in the ring memory corresponding to the number of random sequence generators 3a, 3b, 3c. Since the number of memory elements 5a, 5b, 5c corresponds to the number of buffer elements 12, the signal values previously stored in memory elements 5a, 5b, 5c are now buffer-stored in the buffer elements.
• the random sequence signals of the random sequence generators 3a, 3b, 3c are each reset to the initial state.
• a defined time is then waited until the random sequence signals of the random sequence generators 3a, 3b, 3c have each assumed a random value.
• a random sequence signal value is then determined in each case from the individual random sequence signals of the function groups 2a, 2b, 2c. This is in the manner described above by means of the exclusive-OR gate 4a, 4b, 4c of the respective function group 2a, 2b, 2c with the one in the memory element 5a, 5b, 5c of this function group 2a, 2b, 2c contain the exclusive-OR link and are stored in the respective memory element 5a, 5b, 5c of the function group 2a, 2b, 2c.
• the data values stored in the ring shift register are cyclically shifted to the right by a number that is greater by 1 than the number of random sequence generators 3a, 3b, 3c in the ring shift register.
• the random sequence signals of the random sequence generators 3a, 3b, 3c are reset to the initial state. A defined time is then waited until the random sequence signals have each taken a random value.
• Memory elements 5a, 5b, 5c and the intermediate memories 12 are preset, possibly repeated one or more times as a loop. In practice, it has proven to be advantageous if, in the case of a random signal generator 1 whose ring shift register has a width of 8 bits, the overall loop defined by the processing steps mentioned
• Random number at the data outputs 9a, 9b, 9c, 9d read out in parallel as a binary number.
• the frequency of the random numbers generated by the random signal generator 1 is almost evenly distributed.
• the individual random numbers are not or not significantly correlated. This is achieved above all by mixing the random signal values generated by means of the different random sequence generators 3a, 3b, 3c.
• the random signal values are uncorrelated with one another.
• FIG. 5 shows a further exemplary embodiment of a random signal or random number generator 1, the structure of which essentially corresponds to that of FIG. 3, but with the difference that the second input 8a, 8b; 8c each of the exclusive-OR gates 4a, 4b, 4c is connected to the data output 9c, 9a, 9b of a memory element 5c, 5a, 5b of another function group 2b, 2c, 2a.
• the random signal generator each has a parallel random signal output. This has a plurality of connections, each of which is connected to a data output 9a, 9b, 9c, 9d of a memory element 5a, 5b, 5c, 5d or an intermediate storage element 12.
• a serial random signal output is provided, which is connected to the output of the intermediate storage element 12.
• the individual random sequence generators 3a, 3b, 3c each have a voltage-controlled oscillator 14a, 14b, 14c, which has a frequency control input 15a, 15b, 15c, which is connected to the output of a noise voltage source 16a, 16b, 16c is.
• the oscillator output of each of the oscillators 14a, 14b, 14c is connected to the input of a flip-flop 17a, 17b, 17c, the output of which forms the random sequence signal output 7a, 7b, 7c.
• the flip-flops 17a, 17b, 17c each have one for resetting the random sequence signal present at the random sequence signal output 7a, 7b, 7c Reset input.
• the reset inputs are connected to one another and to a microprocessor 19 by means of a reset line 18.
• the exclusive-or gates 4a, 4b, 4c, the memory elements 5a, 5b, 5c and the intermediate memory elements 12 are arranged in the microprocessor 19.
• random sequence generators 3a, 3b and / or 3c in the exemplary embodiments according to FIGS. 3 to 6 can also be designed according to FIG. 1 and at least two non-deterministic random sequence generators (30a, 30b) and at least one exclusive-or May have gates (40a).

Landscapes

• Tests Of Electronic Circuits (AREA)
• Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=7900513

Family Applications (1)

Country Status (12)

Families Citing this family (6)

Family Cites Families (7)

• 1999
  • 1999-03-11 DE DE19910729A patent/DE19910729C1/de not_active Expired - Fee Related
• 2000
  • 2000-03-07 TW TW089104022A patent/TW527562B/zh not_active IP Right Cessation
  • 2000-03-08 WO PCT/EP2000/001993 patent/WO2000054406A1/de not_active Application Discontinuation
  • 2000-03-08 US US09/936,313 patent/US6593788B1/en not_active Expired - Fee Related
  • 2000-03-08 KR KR1020017011519A patent/KR20010108344A/ko not_active Application Discontinuation
  • 2000-03-08 CA CA002364450A patent/CA2364450A1/en not_active Abandoned
  • 2000-03-08 CN CN00804877A patent/CN1343389A/zh active Pending
  • 2000-03-08 JP JP2000604523A patent/JP2002539662A/ja active Pending
  • 2000-03-08 AU AU34279/00A patent/AU760029B2/en not_active Ceased
  • 2000-03-08 MX MXPA01009108A patent/MXPA01009108A/es unknown
  • 2000-03-08 EP EP00912564A patent/EP1159782A1/de not_active Withdrawn
• 2001
  • 2001-08-07 ZA ZA200106477A patent/ZA200106477B/xx unknown

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events