EP1147546A1 - Procede de diminution de la vitesse de creusage pendant le processus de planarisation chimico-mecanique de structures a semi-conducteurs metalliques - Google Patents

Procede de diminution de la vitesse de creusage pendant le processus de planarisation chimico-mecanique de structures a semi-conducteurs metalliques

Info

Publication number
EP1147546A1
EP1147546A1 EP99957571A EP99957571A EP1147546A1 EP 1147546 A1 EP1147546 A1 EP 1147546A1 EP 99957571 A EP99957571 A EP 99957571A EP 99957571 A EP99957571 A EP 99957571A EP 1147546 A1 EP1147546 A1 EP 1147546A1
Authority
EP
European Patent Office
Prior art keywords
microns
roughness less
polishing
root
polishing pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99957571A
Other languages
German (de)
English (en)
Inventor
Keith G. Pierce
Elizabeth A. Langlois
David Gettman
Vikas Sachan
Peter A. Burke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rodel Inc
Rohm and Haas Electronic Materials CMP Holdings Inc
Original Assignee
Rodel Inc
Rodel Holdings Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rodel Inc, Rodel Holdings Inc filed Critical Rodel Inc
Publication of EP1147546A1 publication Critical patent/EP1147546A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools

Definitions

  • CMP chemical-mechanical planarization
  • CMP Chemical/Mechanical Planarization
  • a barrier layer (typically composed of Ta, TaN, Ti, or TiN) exists between the metal and dielectric layers to inhibit migration of the metal film into the dielectric.
  • a barrier layer typically composed of Ta, TaN, Ti, or TiN
  • the preferential removal of the metal layer with respect to the barrier or dielectric layer is typically referred to as “dishing” or “recess”.
  • preferential removal of the dielectric layer with respect to it's initial film thickness or the metal layer is typically referred to as “erosion” or "oxide thinning".
  • polishing slurry One characteristic of the polishing process that can contribute to the unequal removal of different films within a semiconductor structure is the polishing slurry. Slurries containing different additives and abrasives, or exhibiting different chemical properties (i.e., pH), polish various films at different rates. For example, if a slurry removes the metal interconnect material faster than the dielectric material, the dishing or recess of the metal structure is possibly increased as a result. Additionally, the polishing process parameters (e.g., wafer downforce, platen rotational speed) can also have a strong influence on the final state of the semiconductor structure. The effect of pad characteristics on the quality of a polishing process has also received a significant amount of attention.
  • polishing slurry Slurries containing different additives and abrasives, or exhibiting different chemical properties (i.e., pH), polish various films at different rates. For example, if a slurry removes the metal interconnect material faster than the dielectric material, the dishing or reces
  • a number of different aspects of a pad have been specified as critical to produce a satisfactory semiconductor structure using CMP.
  • the elastic properties of a pad are known to be important to the planarization efficiency during CMP processes.
  • Breivogel in U.S. Patent 5,212,910 present a composite pad structure made-up of three different materials that improves the ability of the pad to conform to the uneven surface of the film being polished.
  • the chemical composition, structure, and make-up of pads used for polishing have also received much attention.
  • Various pad structures have been specified, including urethane impregnated felts (U.S. Patent 4,927,432), polymeric matrices with impregnated void spaces (U.S. Patent 5,578,362) and solid polymeric materials (U.S. Patent 5,489,233).
  • microtexture is described not in terms of pad roughness, but in terms of the size of small flow channels in the pad, which are preferably "randomly oriented straight lines or grooves of randomly varying widths and depths". Additionally, no relationship to polishing performance is specified.
  • U.S. Patent 5,932,486 describes the roughness of the surface of pads used for chemical-mechanical polishing (CMP). It was determined that some pad surface roughness (about 0.1 microns) is necessary in CMP to obtain sufficient removal rates from the surface of semiconductor wafers.
  • the method comprises a polishing slurry that facilitates removal of at least one film preferentially with respect to the other films in said structure and a polishing pad containing a planarizing surface.
  • the rate of dishing or erosion of the remaining structure is decreased.
  • the pad has a planarizing surface with an average roughness less than 4 microns, and a root-mean square roughness less than 5 microns.
  • the polishing pad has a planarizing surface with an average roughness less than 2 microns, and a root-mean square roughness less than 2 microns.
  • the polishing pad has a planarizing surface with an average roughness less than 1 micron, and a root-mean square roughness less than 1 micron.
  • the method of this invention comprises contacting the substrate, which is comprised of at least two different materials, one of which is preferentially removed with respect to the other, with a polishing pad comprising a planarizing surface having an average roughness less than 6 microns, and a root-mean square roughness less than 7 microns, and effecting movement of the substrate and the planarizing surface relative to each other in the presence of a polishing composition that facilitates the removal of one of the materials at a faster rate than the other material.
  • Another aspect of the present invention is a polishing pad useful in chemical-mechanical polishing comprising a planarizing surface having an average roughness less than 6 microns, and a root-mean square roughness less than 7 microns.
  • a critical attribute of a polishing process used in the planarization of complex semiconductor structures is the surface roughness of the pad.
  • a Cu interconnect structure contains barrier films of Ta or TaN, as well as an underlying dielectric film, typically Si0 2 .
  • barrier films of Ta or TaN as well as an underlying dielectric film, typically Si0 2 .
  • Si0 2 an underlying dielectric film
  • One method to achieve this goal is to polish with slurries that have higher removal rates of Cu films with respect to the removal rates for either the barrier film (Ta or TaN) or the dielectric film (Si0 2 ).
  • the applied polishing load is transmitted to the piece being polished through individual asperities on the pad surface, therefore locally increasing the pressure associated with polishing.
  • the asperities can also extend into the metal feature, inducing dishing by contacting the recessed areas.
  • any suitable technique for measuring surface roughness or the size of surface asperities could be employed: these include, but are not limited to, differential interference contrast microscopy, electron microscopy, atomic force microscopy, scanning tunneling microscopy, and optical interferometry. Also, while average and root mean square roughness are commonly used measures of roughness, any parameter or appropriate surface statistic suitable to indicate the level of surface roughness could be used: these include, but are not limited to, peak-to-valley measurements, ten-point height, root-mean-square slope, parameters associated with surface height distribution functions, such as skewness and kurtosis, surface spatial wavelength, and parameters associated with the power- spectral-density function.
  • one typical semiconductor structure that could be polished using this method is comprised of a metal interconnect layer of copper, a barrier layer of tantalum, and a dielectric layer of silicon dioxide.
  • the method described above could be applied in at least two separate points in the structure.
  • this method can be applied to reduce the rate of dishing of the copper metalization structure (this case is covered in the examples below).
  • this method can also be applied to reduce the rate of dishing of the copper structure.
  • this method is applicable to any semiconductor structure comprised of two or more materials where one is preferentially removed with respect to the other during polishing. Also, it should be noted that this method is applicable in the case of multiple films when one film is preferentially removed with respect to numerous other films, or when numerous films are preferentially removed with respect to at least one other film.
  • this method applies to in situ preferential removal of films in a semiconductor structure.
  • dishing of the metal may also be observed due to other effects in the polishing process (i.e., pattern density effects, galvanic effects, etc.).
  • this method is applicable when any differential film removal is observed on a semiconductor structure, and will decrease the rate of removal of any film that is preferably removed with respect to other films.
  • Cu patterned wafers from SEMATECH (Austin, Texas) were polished on the machine and under the conditions as mentioned above.
  • the Cu patterned wafers contain 8000 A deep features of various widths and configurations.
  • a 500 A layer of Ta functions as a barrier layer between the Cu and underlying Si0 2 dielectric layer.
  • Four different wafers were polished. Each wafer was polished with either an OXP3000 pad or an IC1000 pad (both manufactured by Rodel, Inc., Newark, DE).
  • the pads used for sample 1 and 4 were used without any pre-conditioning (i.e., roughening of the surface using a diamond wheel for abrasion).
  • the dishing/recess on two features were monitored at the center and edge of the wafer (four features total) at 30-45 second polishing intervals. Dishing/recess of the wafers was measured using a Tencor P-l profilometer.
  • the data generated from the four trials described in Table 2 from the 12 micron feature at the wafer center are presented in Figures 1-4.
  • the surface is non-planar, and 5000-6500 A of dishing (also referred to as step height) is present.
  • dishing also referred to as step height
  • the structures are gradually planarized, and after a certain polishing time, no dishing is observed. For a certain amount of time, no dishing is present as the final layers of Cu overburden are removed.
  • the Ta barrier layer is reached, due to the higher removal rate of Cu film vs. Ta, dishing of the Cu features begins to increase. As the wafer is overpolished, the dishing increases at a different rate for each of the trials, as is shown in Table 3.
  • Metal layers for which the process and slurries of this invention might be useful include, but are not limited to, tungsten, aluminum, copper, platinum, palladium, gold, iridium and any combination or alloy thereof.
  • Barrier layers for which the process and slurries of this invention might be useful include, but are not limited to, tantalum, tantalum nitride, titanium, titanium nitride, and any combinations thereof.
  • Insulating or dielectric layers for which the process and slurries of this invention might be useful include, but are not limited to, PSG, BPSG, TEOS, Si0 2 , and any low-K polymeric material.
  • the slurries of this invention may have a pH anywhere in the acidic, neutral, or alkaline range.

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

On décrit un procédé permettant de réduire la vitesse de creusage ou d'érosion de structures à semi-conducteurs composites contenant au moins deux films différents. De manière plus préférée, la structure est formée d'une couche de métal, d'une couche diélectrique et d'une couche barrière. Le procédé consiste à rendre plane une structure de semi-conducteurs composite à l'aide d'une boue de polissage et d'un tampon à polir doté d'une surface planarisante.e fait de réduire la rugosité de la surface planarisante du tampon à polir permet de réduire la vitesse à laquelle augmente le creusage ou l'érosion de la structure existante. Dans la forme de réalisation préférée, la vitesse de creusage d'un film en cuivre est réduite par rapport aux films de tantale et de dioxyde de silicium du fait de l'utilisation de tampons à polir dont les niveaux de rugosité de la surface sont faibles.
EP99957571A 1998-11-18 1999-11-17 Procede de diminution de la vitesse de creusage pendant le processus de planarisation chimico-mecanique de structures a semi-conducteurs metalliques Withdrawn EP1147546A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10893698P 1998-11-18 1998-11-18
US108936P 1998-11-18
PCT/US1999/027225 WO2000030159A1 (fr) 1998-11-18 1999-11-17 Procede de diminution de la vitesse de creusage pendant le processus de planarisation chimico-mecanique de structures a semi-conducteurs metalliques

Publications (1)

Publication Number Publication Date
EP1147546A1 true EP1147546A1 (fr) 2001-10-24

Family

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Family Applications (1)

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EP99957571A Withdrawn EP1147546A1 (fr) 1998-11-18 1999-11-17 Procede de diminution de la vitesse de creusage pendant le processus de planarisation chimico-mecanique de structures a semi-conducteurs metalliques

Country Status (4)

Country Link
EP (1) EP1147546A1 (fr)
JP (1) JP2002530861A (fr)
KR (1) KR20010093086A (fr)
WO (1) WO2000030159A1 (fr)

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US6245690B1 (en) 1998-11-04 2001-06-12 Applied Materials, Inc. Method of improving moisture resistance of low dielectric constant films
US6432826B1 (en) 1999-11-29 2002-08-13 Applied Materials, Inc. Planarized Cu cleaning for reduced defects
US6638143B2 (en) 1999-12-22 2003-10-28 Applied Materials, Inc. Ion exchange materials for chemical mechanical polishing
US6451697B1 (en) 2000-04-06 2002-09-17 Applied Materials, Inc. Method for abrasive-free metal CMP in passivation domain
US6858540B2 (en) 2000-05-11 2005-02-22 Applied Materials, Inc. Selective removal of tantalum-containing barrier layer during metal CMP
US6653242B1 (en) 2000-06-30 2003-11-25 Applied Materials, Inc. Solution to metal re-deposition during substrate planarization
US7220322B1 (en) 2000-08-24 2007-05-22 Applied Materials, Inc. Cu CMP polishing pad cleaning
US6569349B1 (en) 2000-10-23 2003-05-27 Applied Materials Inc. Additives to CMP slurry to polish dielectric films
US6524167B1 (en) 2000-10-27 2003-02-25 Applied Materials, Inc. Method and composition for the selective removal of residual materials and barrier materials during substrate planarization
US20020068454A1 (en) 2000-12-01 2002-06-06 Applied Materials, Inc. Method and composition for the removal of residual materials during substrate planarization
US7012025B2 (en) 2001-01-05 2006-03-14 Applied Materials Inc. Tantalum removal during chemical mechanical polishing
US7008554B2 (en) 2001-07-13 2006-03-07 Applied Materials, Inc. Dual reduced agents for barrier removal in chemical mechanical polishing
US7104869B2 (en) 2001-07-13 2006-09-12 Applied Materials, Inc. Barrier removal at low polish pressure
US6592742B2 (en) 2001-07-13 2003-07-15 Applied Materials Inc. Electrochemically assisted chemical polish
US6811470B2 (en) 2001-07-16 2004-11-02 Applied Materials Inc. Methods and compositions for chemical mechanical polishing shallow trench isolation substrates
US6821881B2 (en) 2001-07-25 2004-11-23 Applied Materials, Inc. Method for chemical mechanical polishing of semiconductor substrates
US6677239B2 (en) 2001-08-24 2004-01-13 Applied Materials Inc. Methods and compositions for chemical mechanical polishing
US7199056B2 (en) 2002-02-08 2007-04-03 Applied Materials, Inc. Low cost and low dishing slurry for polysilicon CMP
TWI295950B (en) 2002-10-03 2008-04-21 Applied Materials Inc Method for reducing delamination during chemical mechanical polishing
US7063597B2 (en) 2002-10-25 2006-06-20 Applied Materials Polishing processes for shallow trench isolation substrates
US6899612B2 (en) 2003-02-25 2005-05-31 Rohm And Haas Electronic Materials Cmp Holdings, Inc. Polishing pad apparatus and methods
US6899602B2 (en) * 2003-07-30 2005-05-31 Rohm And Haas Electronic Materials Cmp Holdings, Nc Porous polyurethane polishing pads
US7210988B2 (en) 2004-08-24 2007-05-01 Applied Materials, Inc. Method and apparatus for reduced wear polishing pad conditioning
TW200720493A (en) 2005-10-31 2007-06-01 Applied Materials Inc Electrochemical method for ecmp polishing pad conditioning

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Also Published As

Publication number Publication date
KR20010093086A (ko) 2001-10-27
WO2000030159A1 (fr) 2000-05-25
JP2002530861A (ja) 2002-09-17

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