EP1143309A1 - Elektronisches uhrwerk, verfahren zum kontrollieren eines elektronisches uhrwerks, regelverfahren und regelvorrichtung für elektronisches uhrwerk - Google Patents

Elektronisches uhrwerk, verfahren zum kontrollieren eines elektronisches uhrwerks, regelverfahren und regelvorrichtung für elektronisches uhrwerk Download PDF

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Publication number
EP1143309A1
EP1143309A1 EP00961056A EP00961056A EP1143309A1 EP 1143309 A1 EP1143309 A1 EP 1143309A1 EP 00961056 A EP00961056 A EP 00961056A EP 00961056 A EP00961056 A EP 00961056A EP 1143309 A1 EP1143309 A1 EP 1143309A1
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EP
European Patent Office
Prior art keywords
data
receive
mode
signal
electronic timepiece
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP00961056A
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English (en)
French (fr)
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EP1143309B1 (de
EP1143309A4 (de
Inventor
Teruhiko Seiko Epson Corporation FUJISAWA
Takashi Seiko Epson Corporation Kawaguchi
Fumiaki Seiko Epson Corporation Miyahara
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Seiko Epson Corp
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Seiko Epson Corp
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Publication of EP1143309A4 publication Critical patent/EP1143309A4/de
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04R—RADIO-CONTROLLED TIME-PIECES
    • G04R60/00—Constructional details
    • G04R60/02—Antennas also serving as components of clocks or watches, e.g. motor coils
    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C3/00—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
    • G04C3/14—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor
    • G—PHYSICS
    • G04—HOROLOGY
    • G04R—RADIO-CONTROLLED TIME-PIECES
    • G04R40/00—Correcting the clock frequency
    • G04R40/06—Correcting the clock frequency by computing the time value implied by the radio signal

Definitions

  • the present invention relates to an electronic timepiece and a control method for the electrical timepiece, and in particular to an analog electronic timepiece with a motor for drive and a control method therefor.
  • an object of the present invention is to provide, in an electrical timepiece in a finished product state of assembled in a case, an electronic timepiece, a control method for electronic timepiece, a regulating system for electronic timepiece, and a regulating method for electronic timepiece which are able to write data easily and do not have complicated structure.
  • a first aspect of the present invention is characterized in that an electronic timepiece with a coil comprises:
  • a second aspect of the present invention is characterized in that, in the first aspect of the present invention, the coil is a motor coil.
  • a third aspect of the present invention is characterized in that, in the first aspect of the present invention, the mode setting unit shifts, when a signal input via the signal input unit is a prescribed signal determined in advance, the operation mode to the data receive mode.
  • a fourth aspect of the present invention is characterized in that, in the third aspect of the present invention, the signal input unit comprises an external operation unit for performing various operations and the prescribed signal is output to the mode setting unit, when operating condition of the external operation unit is in a prescribed operating condition determined in advance.
  • a fifth aspect of the present invention is characterized in that, in the third aspect of the present invention, the coil is a motor coil, and further comprises a motor pulse output prohibit unit for, when the operation mode is in the data receive mode, prohibiting of output of a motor pulse to the motor coil.
  • a sixth aspect of the present invention is characterized in that, in the third aspect of the present invention, the mode setting unit shifts, when, after the operation mode is sifted to the data receive mode, the external synchronization signal is not input within a prescribed time period determined in advance, the operation mode from the data receive mode to the normal operation mode in which a normal operation is carried out.
  • a seventh aspect of the present invention is characterized in that, in the third aspect of the present invention, the mode setting unit shifts, when a data with a predetermined amount of bits is received after the operation mode is shifted to the data receive mode, the operation mode from the data receive mode to the normal operation mode in which the normal operation is carried out.
  • An eighth aspect of the present invention is characterized in that, in the first aspect of the present invention, the coil is a motor coil, the motor coil is a coil to which a motor pulse is output at regular intervals, and the mode setting unit sets the operation mode to the data receive mode only during a prescribed time period determined in advance of a non-output time period of the motor pulse.
  • a ninth aspect of the present invention is characterized by, in the first aspect of the present invention, further comprising, a receive data storing unit for storing the receive data, and a data storage control unit for, when a prescribed number, which number is determined in advance, of the identical receive data is received, storing the receive data into the receive data storing unit.
  • a tenth aspect of the present invention is characterized in that, in the ninth aspect of the present invention, the receive data storing unit comprises a non-volatile memory unit for non-volatilely storing the receive data, and a data writing unit for writing the receive data in the non-volatile memory unit.
  • An eleventh aspect of the present invention is characterized by, in the first aspect of the present invention, further comprising a comparator for, by comparing voltage of the data voltage signal and a prescribed reference voltage determined in advance, generating and outputting the receive data.
  • a twelfth aspect of the present invention is characterized by, in the eleventh aspect of the present invention, further comprising a comparator operation controller unit for, only during a prescribed time period including during the data receive mode, making the comparator into an operation enabled state.
  • a thirteenth aspect of the present invention is characterized by, in the eleventh aspect of the present invention, further comprising a power supply controller unit for, only during a prescribed time period including during the data receive mode, supplying operating power to the comparator.
  • a fourteenth aspect of the present invention is characterized by, in the first aspect of the present invention, further comprising an inverter for, by comparing voltage of the data voltage signal with a prescribed reference voltage determined in advance, generating and outputting the receive data.
  • a fifteenth aspect of the present invention is characterized in that a regulating system for an electronic timepiece comprises an electrical timepiece and an external device, the electrical timepiece comprises;
  • a sixteenth aspect of the present invention is characterized in that, in the fifteenth aspect of the present invention, the coil of the electronic timepiece is a motor coil.
  • a seventeenth aspect of the present invention is characterized in that a control method for an electronic timepiece with a coil comprises a mode setting step for shifting an operation mode of the electrical timepiece between a data receive mode in which data is received and a normal operation mode, and a receive data generating step for, when the operation mode is in the receive mode, establishing synchronization with the external transmitter device based on an external synchronization signal input from an external transmitter device that transmits a data signal, being in the data receive mode, and generating a receive data, based on the synchronization signal and a data voltage signal that is a voltage signal induced around the coil by the data signal input from the external transmitter device.
  • An eighteenth aspect of the present invention is characterized in that, in the seventeenth aspect of the present invention, the mode setting step shifts, when signal input via the signal input unit is a prescribed signal determined in advance, the operation mode to the data receive mode.
  • a nineteenth aspect of the present invention is characterized in that, in the eighteenth aspect of the present invention, the electrical timepiece comprises an external operating member for performing various operations, and the mode setting step shifts, when operating condition of the external operating member is in prescribed operating condition determined in advance, the operation mode to the data receive mode.
  • a twentieth aspect of the present invention is characterized in that, in the eighteenth aspect of the present invention, the coil is a motor coil and the method further comprises a motor pulse output prohibit step for prohibiting of output of motor pulse to the motor coil, when the operation mode is the data receive mode,
  • a twenty-first aspect of the present invention is characterized in that, in the eighteenth aspect of the present invention, the mode setting step shifts, when the external synchronization signal is not input during a prescribed time period determined in advance after shifting of the operation mode to the data receive mode, the operation mode from the data receive mode to the normal operation mode in which normal operation is carried out.
  • a twenty-second aspect of the present invention is characterized in that, in the eighteenth aspect of the present invention, the mode setting step shifts, when a data with a predetermined amount of bits is received after the operation mode is shifted to the data receive mode, the operation mode from the data receive mode to the normal operation mode in which the normal operation is carried out.
  • a twenty-third aspect of the present invention is characterized in that, in the seventeenth aspect of the present invention, the coil is a motor coil, motor pulse is output at a constant intervals to the motor coil, and the mode setting step sets the operation mode to the data receive mode only during a prescribed time period determined in advance of a non-output time period of the motor pulse.
  • a twenty-fourth aspect of the present invention is characterized by, in the seventeenth aspect of the present invention, further comprising a receive data storing step for storing the receive data, and a data storage control step for, when a prescribed number, which number is determined in advance, of the identical receive data is received, storing the receive data during the receive data storing step.
  • a twenty-fifth aspect of the present invention is characterized in that, in the twenty-fourth aspect of the present invention, the receive data storing step comprises a data writing step for writing the receive data in a non-volatile memory of the electrical timepiece.
  • a twenty-sixth aspect of the present invention is characterized in that, in the seventeenth aspect of the present invention, the electrical timepiece comprises a comparator for, by comparing voltage of the data voltage signal with a prescribed reference voltage determined in advance, generating and outputting the receive data, and the control method further comprises a comparator operation control step for, only during a prescribed time period including during the data receive mode, making the comparator into an operation enabled state.
  • a twenty-seventh aspect of the present invention is characterized by, in the twenty-sixth aspect of the present invention, further comprising a power supply control step for, only during a prescribed time period including during the data receive mode, supplying operating power to the comparator.
  • a twenty-eighth aspect of the present invention is characterized in that a regulating method for an electronic timepiece:
  • Fig. 1 shows a schematic configuration block diagram of a data transmission system.
  • An analog electrical timepiece 103 of a data transmission system 100 has a motor coil 101 and an external operating member 102 such as a crown or a button.
  • An external data transmission device 105 transmits a data signal STR to the analog electrical timepiece 103 via a transmission coil 104.
  • data transmitted as the data signal STR may be a pace regulation data, a correction data for various sensors, or data for specification changes.
  • FIG. 2 is a schematic configuration block diagram of an analog electronic timepiece.
  • An oscillating circuit 11 of the analog electronic timepiece 103 has a quartz crystal oscillator 11C and generates a reference pulse signal having a prescribed reference frequency from a reference oscillation signal generated by the quartz crystal oscillator 11C.
  • a divider circuit 12 divides the reference pulse signal output by the oscillating circuit 11, thereby outputs various pulse signals.
  • a controller circuit 13 has a counter 13A and, based on the various pulses output from the divider circuit 12 and stored data in a data storage circuit 17 which is described later, controls all parts of the analog electronic timepiece 103.
  • the counter 13A measures elapsed time t which is time from negative edge of timing signal (which is later described), and determines whether or not the elapsed time t reaches a predetermined data detection stand-by time Ta.
  • a detection circuit 14 detects the data signal STR input via the motor coil 101 to output as a detection data DDS to the control circuit 13.
  • a drive pulse generator circuit 15 based on pulse signals output from the divider circuit 12, generates drive pulses.
  • a drive circuit 16 based on the drive pulses, feeds driving current to the motor coil to drive a drive motor.
  • a data conversion circuit 18 serial-parallel-converts the detection data DDS output from the detection circuit 14 via the control circuit 13 to output a parallel detection data DDP to the data storage circuit 17.
  • the data storage circuit 17 is equipped with a data writing circuit 17C.
  • the data writing circuit 17C has an EEPROM 17A and a booster circuit 17B.
  • the EEPROM 17A stores the parallel detection data DDP so as not to be volatile.
  • the booster circuit 17B boosts power supply voltage to generate voltage for writing.
  • the analog electronic timepiece 103 is in its case as shown in Fig. 14 and receives data.
  • FIG. 3 shows a schematic configuration block diagram of an external data transmission device.
  • An oscillating circuit 21 of the external data transmission device 105 comprises a quartz crystal oscillator or a ceramic oscillator (both are not shown) and, based on a reference oscillating signal generated by these oscillators, generates a reference pulse signal having a predetermined reference frequency.
  • a divider circuit 22 by dividing the reference pulse signal that is output from the oscillating circuit 21, outputs various pulse signals.
  • the control circuit 23 may be configured with a CPU, a ROM, and a RAM, and operates by the CPU based on a control program stored in the ROM.
  • the control circuit 23 also may be configured with logic circuits.
  • the data storing circuit 24, under control of the control circuit 23, stores various data and outputs various stored data.
  • a PSK modulator circuit 25 under control of the control circuit 23, based on transmission data read from the data storage circuit 24, implements phase shift keying modulation on pulse signals output from the divider circuit.
  • An amplifier circuit 26 amplifies the output of the PSK modulator circuit 25 to output as data signal STR via the transmission coil 104.
  • the PSK modulator circuit 25 performs modulation by inverting the phase of a reference signal. For example, when signal level of the signal to be transmitted has the "H” level the phase is put to 0 degree, and when signal level of the signal to be transmitted has the "L” level the phase is put to 180 degree.
  • a hand drive unit 19 with a drive circuit 16 and the motor coil 101 is provided.
  • the drive unit 16 comprises a p-channel MOS transistor P1 and an n-channel MOS transistor N1, both transistors being connected in series between the higher electric potential side power supply Vdd and the lower electric potential side power supply VSS.
  • the drive unit 16 also comprises a p-channel MOS transistor P2 and an n-channel MOS transistor N2, both transistors being connected in series between the higher electric potential side power supply Vdd and the lower electric potential side power supply VSS, and connected in parallel with the p-channel MOS transistor P1 and the n-channel MOS transistor N1.
  • p-channel MOS transistor P1, n-channel MOS transistor N1, p-channel MOS transistor P2, and n-channel MOS transistor N2 based on the control signal input from the drive pulse generator circuit 15 to the gate terminals, the p-channel MOS transistor P1 and the n-channel MOS transistor N2 simultaneously are turned ON/OFF. Or, based on the control signal, the p-channel MOS transistor P2 and the n-channel MOS transistor N1 simultaneously are turned ON/OFF.
  • the drive current flows from the higher electric potential side power supply Vdd to the p-channel MOS transistor P1 to the motor coil 101 to the n-channel MOS transistor N2 to the lower electrical potential side power supply VSS.
  • the p-channel MOS transistor P2 and the n-channel MOS transistor N1 when the p-channel MOS transistor P2 and the n-channel MOS transistor N1 is in the ON state, the p-channel MOS transistor P1 and the n-channel MOS transistor N2 become the OFF state.
  • the drive current (drive pulse) flows from the higher electric potential side power supply Vdd to the p-channel MOS transistor P2 to the motor coil 101 to the n-channel MOS transistor N1 to the lower electrical potential side power supply VSS.
  • the motor coil 101 of the hand drive unit 19 is composing a part of a stepping motor 110.
  • a stator 112 of the hand drive unit 19 is magnetized by the motor coil 101.
  • a rotor 113 rotates by the induced magnetic field in the stator 112.
  • the configuration of the stepping motor 110 is a PM-type (permanent magnet rotation type), in which the rotor 113 is configured by disk-shaped two-pole permanent magnet.
  • the stator 112 has a magnetic saturation section 117 where electromotive force induced around the motor coil 101 produces unlike poles at poles 115 and 116.
  • the poles 115 and 116 are located around the rotor 113.
  • a notch 118 is provided to regulate direction of rotation.
  • cogging torque is produced to stop the rotor 113 at a suitable place.
  • the gear train 120 has a fifth wheel 121 engaged with the rotor 113, a fourth wheel 122, a third wheel 123, a second wheel 124, a minute wheel 125, and an hour wheel 126.
  • On a shaft of the fourth wheel 122 is put a second hand 131.
  • On a shaft of the second wheel 124 is put a minute hand 132.
  • On a shaft of the hour wheel 126 is put an hour hand 133.
  • These hands display time by the rotation of the rotor 113.
  • the gear train 120 may be further equipped with other transmission system for displaying date.
  • the detection circuit 14 comprises a reference voltage generator circuit 31, a comparator 32, and an n-channel MOS transistor N3.
  • the reference voltage generator circuit 31 of the detection circuit 14 generates reference voltage VREF.
  • the comparator 32 compares the reference voltage VREF and voltage V02 on an output terminal 02 of the drive circuit 16, and outputs the detection data DDS.
  • FIG. 5 shows a timing chart of the first embodiment.
  • FIG. 6 shows a processing flow chart of the first embodiment.
  • amount of bit to be received is X bits (X is a natural number).
  • the external operating member 102 is operated (refer to part A of Fig. 5) to shift the analog electronic timepiece 103 to the receive mode (step S1).
  • the operation of the external operating member has to be complicated to some extent.
  • step S2 When the operation to shift to the data receive mode is carried out, irregular hand movement is started to notify the user that the operation mode of the analog electronic timepiece is the data receive mode (step S2).
  • the data receive mode for example, a five-second interval hand movement is used.
  • data receiving operation cannot be carried out.
  • the output terminal O2 of the drive circuit 16 becomes high-impedance state and electrically floating state.
  • the output terminal O2 of the drive circuit 16 becomes high-impedance state.
  • the sampling drive signal SSP is put to the "H" level (refer to part B of Fig. 5).
  • the n-channel MOS transistor N3 is also put to ON state.
  • the comparator 32 is supplied with operating power and becomes operating state.
  • the control circuit 13 determines whether or not a timing signal STM (refer to part C of Fig. 5) is received as the data signal STR via the motor coil 101 and the detection circuit 14 (step S3).
  • a timing signal STM (refer to part C of Fig. 5) is received as the data signal STR via the motor coil 101 and the detection circuit 14 (step S3).
  • the timing signal STM it is preferable that the timing signal STM have rectangular wave that makes receive level high from the viewpoint of receive level.
  • step S3 when the timing signal STM is not received (step S3; NO), a determination is made whether or not an elapsed time t' which is a time from the shift to the receive mode exceeds a predetermined stand-by time TC (step S9).
  • step S9 when the elapsed time t' does not exceed the predetermined stand-by time TC, that is, when (step S9; NO), t' TC the process of the flowchart returns to step S3, and the same processes is carried out.
  • step S9 when the elapsed time t' exceeds the stand-by time TC, in order to lower power consumption due to unnecessary operation by the comparator 32, the receive operation is stopped to return to the normal operation. Or it is assumed that the user by mistake shifts to the receive operation. Therefore, the receive operation is stopped to return to normal operation (step S8).
  • step S3 when the timing signal shown in part C of Fig. 5 is received (step S3; YES), the control circuit 13 starts counting operation of the counter 13A. Then, at a negative edge of the timing signal as shown at t1 of Fig. 5, the counter 13A is reset. In addition, synchronization of the analog electronic timepiece and the external transmission device 105 is established.
  • the analog electronic timepiece is in data receive standby state.
  • control circuit 13 based on the counted value of the counter 13A, judges whether or not the elapsed time t that is a time from negative edge of the timing signal exceeds a predetermined data detection standby time Ta (step S4).
  • step S4 t >Ta
  • step S4 when the elapsed time t does not exceed the data detection standby time Ta, step S4 operation is repeated, so the standby state is retained.
  • the PSK modulator circuit 25 under control of the control circuit 23, based on transmission data read from the data storage circuit 24, implements phase shift keying modulation on pulse signals output from the divider circuit to output to the amplifying circuit 26.
  • the amplifier circuit 26 amplifies the output of the PSK modulator circuit 25 to output as data signal STR via the transmission coil 104.
  • the data signal STR is a PSK-modulated sinusoidal wave.
  • the phase of the data signal STR is inverted 180 degree based on the signal level ("H" or "L").
  • the analog electronic timepiece 103 puts a data read timing signal SRD to the "H" level (see part J of Fig. 5, t2).
  • the analog electronic timepiece 103 also determines the signal level of the detection data DDS (refer to part I of Fig. 5), and reads data having one bit (step S5).
  • level of the detection data DDS becomes the "H", and the data of one bit becomes "1".
  • step S7 a judgement is made whether or not the number of bits of the received data reaches X bits.
  • step S7 when the number of bits of the received data is less than X bits, that is when the following inequality is satisfied (step s7; NO), N ⁇ X a judgement is made whether or not an elapsed time t" which is a time from a preceding detection point of signal level of detection data DDS (at t2) exceeds a prescribed data detection standby time Tb. Namely, whether or not a following inequality is satisfied is judged (step S10). t" > Tb
  • step S10 when the elapsed time t" does not exceeds the data detection standby time Tb, that is the following inequality is satisfied (step S10; NO), t" Tb the process of step S10 is repeated, and the standby state is retained.
  • the data read timing signal SRD is put to the "H" level as shown at t3 in part C of Fig. 5. Further, the signal level of the detection data DDS is detected, and data having one bit is read (step S5).
  • induced voltage VO2 on the output terminal O2 is compared with the reference voltage VREF by the comparator 32 to output the data signal DDS.
  • voltage level of induced voltage VO2 is determined by the comparator 32 at intervals of data detection standby time Tb which is in synchronization with the frequency of the data signal STR.
  • the data conversion circuit 18 serial-parallel-converts the detection data DDS to generate the parallel detection data DDP.
  • the parallel detection data DDP is stored in the data storage circuit 17.
  • PSK modulation is used.
  • ASK amplitude shift keying
  • time Ta may be set equal to Tb.
  • sharing counters for measuring time Ta, and Tb becomes possible, therefore it is possible to simplify circuit.
  • the pace regulating circuit 19 based on the parallel detection data DDP stored in the data storage circuit 17, controls the division ratio of the divider 12 to regulate a predetermined value. Therefore, time keeping accuracy of the analog electronic timepiece is enhanced.
  • data receiving is performed via a motor coil that is a component part of the analog electronic timepiece 103, therefore changes of the device configuration can be reduced to the minimum.
  • the input terminal of the comparator 32 is connected to the output terminal 02 which is one output terminal of the drive circuit 16.
  • the output terminal 02 which is one output terminal of the drive circuit 16.
  • a more suitable voltage is selected from voltage on the output terminal O1 and voltage on the output terminal 02.
  • FIG. 7 shows a schematic configuration block diagram of the first modification.
  • This first modification is different from the above embodiment in that, instead of the detection circuit 14 in Fig. 4, a detection circuit 14-1 is provided.
  • Fig. 7 the same or identical constituents as or to those in Fig. 4 are shown with the same references.
  • the reference voltage generator circuit 31 of the detection circuit 14-1 generates reference voltage VREF.
  • a comparator 41 compares the reference voltage VREF and voltage VO1 on the output terminal O1 of the drive circuit 16 and outputs a detection data DDS1.
  • a comparator 32 compares the reference voltage VREF and voltage VO2 on the output terminal 02 of the drive circuit 16 and outputs a detection data DDS2.
  • the n-channel MOS transistor N4 based on a sampling drive signal SSP1 from the control circuit 13, supplies the comparator 41 with power.
  • a latch circuit 42 constructed by D-flipflap circuits, latches the detection data DDS1.
  • a latch circuit 43 constructed by D-flipflap circuits, latches the detection data DDS2.
  • a selector circuit 44 selects either the detection data DDS1 or the detection data DDS2 and outputs it as the detection data DDS.
  • the sampling drive signal SSP1 is put to the "H" level.
  • the n-channel MOS transistor N4 becomes the ON state, and the comparator 41 is provided with power and becomes operating state.
  • the comparator 41 compares voltage VO1 on the output terminal 01 of the drive circuit 16 with reference voltage VREF and outputs the detection data DDS 1 to the latch circuit 42.
  • the sampling drive signal SSP2 is put to the "H" level.
  • the n-channel MOS transistor N3 becomes the ON state, and the comparator 32 is provided with power and becomes operating state.
  • the comparator 32 compares the reference voltage VREF and voltage VO2 on the output terminal O2 of the drive circuit 16 and outputs the detection data DDS2 to the latch circuit 43.
  • the latch circuit 42 holds the detection data DDS1
  • the latch circuit 43 holds the detection data DDS2.
  • the selector circuit 44 selects a latch circuit in a pre-decided way to select either the detection data DDS1 or the detection data DDS2. Then the selector circuit 44 outputs a detection data corresponding to the selected latch circuit as the detection data DDS.
  • the comparator 32 is used to detect the detection data DDS.
  • an inverter circuit may be used instead of the comparator 32.
  • FIG. 8 is a schematic configuration block diagram of this second modification.
  • This second modification is different from the above embodiment in that, instead of the detection circuit 14-1 in Fig. 7, a detection circuit 14-2 is provided.
  • Fig. 7 the same or identical constituents as or to those in Fig. 8 are shown with the same references.
  • An inverter circuit 51 of the detection circuit 14-2 compares voltage VO1 on the output terminal O1 of the drive circuit 16 with reference voltage VREF1 and outputs the detection data DDS1.
  • An inverter circuit 52 compares voltage VO2 on the output terminal O2 of the drive circuit 16 with reference voltage VREF1 and outputs the detection data DDS2.
  • a latch circuit 42 constructed by D-flipflap circuits, latches the detection data DDS1.
  • a latch circuit 43 constructed by D-flipflap circuits, latches the detection data DDS2.
  • a selector circuit 44 selects either the detection data DDS1 or the detection data DDS2 and outputs it as the detection data DDS.
  • PSK modulation is used.
  • ASK amplitude shift keying
  • time Ta may be set equal to Tb.
  • Tb time Ta is set equal to Tb, sharing counters for measuring time Ta, and Tb becomes possible, therefore it is possible to simplify circuit.
  • the inverter circuit 51 outputs a detection data DDS1 that indicates whether voltage VO1 on the output terminal O1 of the drive circuit 16 exceeds the threshold voltage VREF1 for the inverter circuit 51 to the latch circuit 42.
  • the inverter circuit 52 outputs a detection data DDS2 that indicates whether voltage VO2 on the output terminal O2 of the drive circuit 16 exceeds the threshold voltage VREF2 for the inverter circuit 51 to the latch circuit 43.
  • the threshold voltages VREF1 and VREF2 becomes almost same.
  • the latch circuit 42 holds the detection data DDS1
  • the latch circuit 43 holds the detection data DDS2.
  • the selector circuit 44 selects a latch circuit in a pre-decided way to select either the detection data DDS1 or the detection data DDS2. Then the selector circuit 44 outputs a detection data corresponding to the selected latch circuit as the detection data DDS.
  • either voltage of output terminals O1 or 02 can be the detection data DDS. As a result, it becomes possible to make a suitable detection for each analog electronic timepiece regardless its size and structure.
  • shift to the data receive mode is conducted based on the operating state of the external operating member 102.
  • shift to the data receive mode is automatically conducted in a motor pulse non-outputting period.
  • the motor pulse non-outputting period is a period between two consecutive motor pulses.
  • FIG. 9 shows a timing chart of the third modification.
  • Motor pulses are output at intervals of one second (refer to part A of Fig. 9).
  • the sampling drive signal SSP is put to the "H" level (refer to part B of Fig. 9).
  • the analog electronic timepiece is shifted to the data receive mode, and only the p-channel MOS transistor P1 is put to ON state (refer to part D of Fig.9).
  • output of the drive pulses is stopped.
  • the p-channel MOS transistor P2, the n-channel MOS transistor N1, and the n-channel MOS transistor N2 are put to the OFF state (refer to parts E, F, and G of Fig. 9).
  • the output terminal O2 of the drive circuit 16 becomes high-impedance state, or floating state as shown in part H of Fig. 9.
  • the sampling drive signal SSP is put to the "H" level (refer to part B of Fig. 5).
  • the n-channel MOS transistor N3 is also put to ON state.
  • the comparator 32 is supplied with operating power and becomes operating state.
  • control circuit 13 determines whether or not a timing signal STM (refer to part C of Fig. 9) is received as the data signal STR via the motor coil 101 and the detection circuit 14.
  • the control circuit 13 When a timing signal as shown in part C of Fig. 9 is received, the control circuit 13 starts counting operation. In addition, as shown time t1 in Fig. 9, at a falling edge of the timing signal, the counter 13 is reset. A synchronization is established between the analog electronic timepiece and the external data transmission device 105, and the analog electronic timepiece is put to the data receive standby state.
  • control circuit 13 based on the counted value of the counter 13A, judges whether or not an elapsed time t that is a time from negative edge of the timing signal exceeds a predetermined data detection standby time Ta.
  • the PSK modulator circuit 25 under control of the control circuit 23, based on transmission data read from the data storage circuit 24, implements phase shift keying modulation on pulse signals output from the divider circuit to output to the amplifying circuit 26.
  • the amplifier circuit 26 amplifies the output of the PSK modulator circuit 25 to output as data signal STR via the transmission coil 104.
  • the data signal STR is a PSK-modulated sinusoidal wave.
  • the phase of the data signal STR is inverted 180 degree based on the signal level ("H" or "L").
  • the analog electronic timepiece 103 puts a data read timing signal SRD to the "H" level (see part J of Fig. 9, t2).
  • the analog electronic timepiece 103 also determines the signal level of the detection data DDS (refer to part I of Fig. 9), and reads data having one bit (step S5).
  • the detection data DDS having the "H" level is output.
  • the detection data becomes the "H” level, and one bit data has "1".
  • the data read timing signal SRD is put to the "H" level as shown at t3 in part J of Fig. 9. Further, the signal level of the detection data DDS is detected, and data having one bit is read.
  • induced voltage VO2 on the output terminal O2 is compared with the reference voltage VREF by the comparator 32 to output the data signal DDS.
  • voltage level of induced voltage O2 is determined by the comparator 32 at intervals of data detection standby time Tb which is in synchronization with the frequency of the data signal STR.
  • the data conversion circuit 18 serial-parallel-converts the detection data DDS to generate a parallel detection data DDP.
  • the parallel detection data DDP is stored in the data storage circuit 17.
  • the data receive mode when a prescribed amount of data is received, the data receive mode is terminated. However, the data receive mode may be terminated, when a prescribed termination order is received.
  • FIG. 10 shows a processing flow chart of a fourth modification.
  • the processing in processing flow chart shown in Fig. 10 is as a general similar to the processing in processing flow chart of Fig. 6.
  • Difference from the processing flow chart of Fig. 6 is that, after data receive operation, when the received data is a termination order code, the receive mode is terminated and the normal mode is resumed.
  • a termination order code for example as shown if Fig. 11, may be configured to have a data command queue with an order code section having four bits and a data section having eight bits.
  • a termination order code has "0101" in its order code section and dummy data in its data section.
  • the order code section When data A is transmitted, the order code section has "1001" and the data section has data for data A.
  • the order code section When data B is transmitted, the order code section has "1010" and the data section has data for data B.
  • the order code section When data C is transmitted, the order code section has "1011" and the data section has data for data C.
  • the analog electronic timepiece which received the termination order code shifts its operation mode to the normal operation mode, and normal hand movement is resumed.
  • the external data transmission device transmits data to the analog electronic timepiece.
  • the external data transmission device and the analog electronic timepiece can transmit and receive in two-way.
  • FIG. 12 shows a schematic configuration block diagram of a data transmission system of the second embodiment.
  • the data transmission system 100A essentially includes a control unit 61, a transmission/receive unit block 62, and a switching unit 63.
  • a plurality of analog electronic timepieces 103 (not shown) are put in a way shown in Fig. 14, each facing to one transmission/receive unit block 62.
  • the control unit 61 controls all parts of the data transmission system.
  • Each of the transmission/receive unit block 62 transmits and receives data between the analog electronic timepiece 103.
  • the transmission/receive unit block 62 comprises a plurality of (in Fig. 12, 10 units of) transmission/receive units 65-1 to 65-10 which are simultaneously driven. Therefore, one transmission/receive unit block performs data transmission and receive operation between ten analog electronic timepieces simultaneously.
  • the switching unit 63 under control of the control unit 61, switches to the transmission/receive unit block 62 which is to be controlled.
  • FIG. 13 shows a schematic configuration block diagram of a control unit and a transmission/receive unit. Since all transmission/receive units 65-1 to 65-10 have the same configuration, in the following explanation, only the transmission/receive unit 65-1 will be described as an example.
  • a reference clock signal generator circuit 71 generates a reference clock signal CREF.
  • a divider circuit 72 divides the reference clock signal CREF, thereby outputs a divided clock signal CREFD.
  • a data computing circuit 73 based on a measurement data (for example, a pace measurement data), calculates and outputs a correction data DC.
  • a phase shift keying (PSK) modulator circuit 74 based on the correction data DC and the divided clock signal CREFD, implements PSK modulation and outputs a modulating signal SEN to the switching unit.
  • the control circuit 75 controls all parts of the control unit 61 and, by a switch control signal SSW, the switching unit 63.
  • An amplifying circuit of the transmit/receive unit 65-1 amplifies the modulating signal SEN which is input via the switching unit 63.
  • the changing-over switch 82 switches between transmission and receiving.
  • a transmission/receive coil 83 transmits and receives data with its corresponding analog electronic timepiece.
  • An amplifying circuit 84 amplifies a receive signal SRC which is received from the analog electronic timepiece via the transmission/receive coil 83.
  • a data detection circuit 85 extracts transmitted data from the output signal of the amplifying circuit 84, and outputs it to the control unit 61 via the switching unit 63.
  • the analog electronic timepiece 103 is, as shown in Fig. 14, in a finished product state of assembled in a case and placed near the transmission/receive coil 83, and performs data transmission and receive by using magnetic field signal.
  • control unit 61 transmits data to the analog electronic timepiece 103.
  • the reference clock signal generator circuit 71 of the control unit 61 generates a reference clock signal CREF and outputs it to the divider circuit 72.
  • the divider circuit 72 divides the reference clock signal CREF and outputs a divided clock signal CREFD to the PSK modulator circuit 74.
  • a data computing circuit 73 under control of control circuit 75, based on a measurement data, calculates a correction data DC and outputs the result to the PSK modulator circuit 74.
  • the PSK modulator circuit 74 based on the correction data DC and the divided clock signal CREFD, implements PSK modulation and outputs a modulating signal SEN to the switching unit 63.
  • the switching unit 63 connects the control unit 61 to the transmit/receive unit 65-1 on which the analog electronic timepiece 103 which is to receive the modulating signal SEN is placed.
  • the amplifying circuit 81 of the transmit/receive unit 65-1 amplifies the modulating signal SEN which is input via the switching unit 63, then outputs it to the transmission/receive coil 83 via the changing-over switch 82.
  • the receive signal SRC is input to the amplifying circuit 84 via the transmission/receive coil 83.
  • the amplifying circuit 84 amplifies the receive signal and outputs it to the data detection circuit 85.
  • a motor coil is used for data transferring as an example.
  • the present invention may be applied to other timepiece such as a digital timepiece, if an electrical timepiece has a coil that is not limited to a motor coil and can be used for non-contact communication.
  • the present invention may be applied to a digital timepiece that carries out digital displaying and to an analog electrical timepiece with a digital display, which analog electrical timepiece may display on its liquid crystal display a result of measurement by sensors for various measurement.
  • the intention of the present invention may be applied to a handheld electrical device with a motor coil other than an analog electrical timepiece, such as a portable CD player, a portable mini disc (MD) player or recorder, a portable cassette player or recorder.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Electromechanical Clocks (AREA)
  • Electric Clocks (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
EP00961056A 1999-09-17 2000-09-18 Elektronische uhr, und verfahren zum kontrollieren einer elektronischen uhr Expired - Lifetime EP1143309B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP26447299 1999-09-17
JP26447299 1999-09-17
PCT/JP2000/006354 WO2001022175A1 (fr) 1999-09-17 2000-09-18 Compteur de temps electronique; technique de commande et methode de reglage dudit compteur de temps

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EP1143309A1 true EP1143309A1 (de) 2001-10-10
EP1143309A4 EP1143309A4 (de) 2005-03-16
EP1143309B1 EP1143309B1 (de) 2008-09-17

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EP (1) EP1143309B1 (de)
CN (1) CN1258698C (de)
DE (1) DE60040267D1 (de)
HK (1) HK1037744A1 (de)
WO (1) WO2001022175A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1455247A1 (de) * 2002-06-12 2004-09-08 Seiko Epson Corporation Taktsystem und verfahren zur steuerung des taktsystems

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003016568A (ja) * 2001-06-28 2003-01-17 Tokyo Gas Co Ltd メータ制御器

Citations (1)

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Publication number Priority date Publication date Assignee Title
WO1998055902A1 (fr) * 1997-06-05 1998-12-10 Citizen Watch Co., Ltd. Systeme d'emission-reception pour montres electroniques

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0635771B1 (de) * 1993-01-08 1997-07-30 Citizen Watch Co. Ltd. Datenübertragungsempfangsystem für elektronische Uhr
JPH06258464A (ja) * 1993-03-09 1994-09-16 Citizen Watch Co Ltd データ送信機能付電子時計
JP4083844B2 (ja) * 1997-09-03 2008-04-30 シチズンホールディングス株式会社 電子時計および電子時計の送受信システム

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998055902A1 (fr) * 1997-06-05 1998-12-10 Citizen Watch Co., Ltd. Systeme d'emission-reception pour montres electroniques

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO0122175A1 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1455247A1 (de) * 2002-06-12 2004-09-08 Seiko Epson Corporation Taktsystem und verfahren zur steuerung des taktsystems
EP1455247A4 (de) * 2002-06-12 2005-07-27 Seiko Epson Corp Taktsystem und verfahren zur steuerung des taktsystems
US7027363B2 (en) 2002-06-12 2006-04-11 Seiko Epson Corporation Time measurement system and method of controlling the same

Also Published As

Publication number Publication date
HK1037744A1 (en) 2002-02-15
EP1143309B1 (de) 2008-09-17
DE60040267D1 (de) 2008-10-30
WO2001022175A1 (fr) 2001-03-29
EP1143309A4 (de) 2005-03-16
CN1337015A (zh) 2002-02-20
CN1258698C (zh) 2006-06-07

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