WO2001022175A1 - Compteur de temps electronique; technique de commande et methode de reglage dudit compteur de temps - Google Patents
Compteur de temps electronique; technique de commande et methode de reglage dudit compteur de temps Download PDFInfo
- Publication number
- WO2001022175A1 WO2001022175A1 PCT/JP2000/006354 JP0006354W WO0122175A1 WO 2001022175 A1 WO2001022175 A1 WO 2001022175A1 JP 0006354 W JP0006354 W JP 0006354W WO 0122175 A1 WO0122175 A1 WO 0122175A1
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- WIPO (PCT)
- Prior art keywords
- data
- electronic timepiece
- mode
- signal
- reception
- Prior art date
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Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R60/00—Constructional details
- G04R60/02—Antennas also serving as components of clocks or watches, e.g. motor coils
-
- G—PHYSICS
- G04—HOROLOGY
- G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
- G04C3/00—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
- G04C3/14—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor
-
- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R40/00—Correcting the clock frequency
- G04R40/06—Correcting the clock frequency by computing the time value implied by the radio signal
Definitions
- the present invention relates to an electronic timepiece and a method for controlling the electronic timepiece, and more particularly to an analog electronic timepiece having a driving motor and a control method therefor.
- Some conventional analog electronic timepieces include a data storage circuit for storing various control data and the like.
- data is written to a data storage circuit by contacting a terminal of an externally provided external data writing device to a circuit board and electrically contacting the data. It was done by writing.
- an object of the present invention is to provide an electronic timepiece and an electronic timepiece that can easily write data in a completed electronic timepiece incorporated in a case and that does not complicate the structure.
- a first aspect of the present invention is directed to an electronic timepiece having a coil for inputting a signal.
- Signal input section a mode setting section that switches the operation mode between a data reception mode for receiving data and a normal operation mode, and an external transmission for transmitting a data signal when the operation mode is the reception mode.
- a synchronization signal generator for generating a synchronization signal synchronized with the operation of the external transmission device based on the external synchronization signal input from the device, an operation mode of the data reception mode, and an input from the external transmission device;
- a reception data generation unit that generates and outputs reception data based on a data voltage signal and a synchronization signal that are voltage signals induced in the coil by the generated data signal.
- the coil is a single-mode coil.
- the mode setting unit activates the operation mode when a signal input via the signal input unit is a predetermined signal. It is characterized in that the mode is shifted to a data reception mode.
- the signal input unit includes an external operation unit for performing various operations, and the operation state of the external operation unit is a predetermined operation. In the state, a predetermined signal is output to the mode setting unit.
- the coil is a motor coil, and when the operation mode is the data receiving mode, the output of the motor pulse to the motor coil is performed. It is characterized by having a motor pulse output prohibition unit that prohibits the operation.
- the mode setting unit is configured to output the external synchronization signal within a predetermined time after the operation mode shifts to the data reception mode.
- the operation mode shifts from the overnight reception mode to the normal operation mode in which normal operation is performed.
- the operation mode when the mode setting unit receives data of a predetermined number of bits after the operation mode has shifted to the data reception mode, the operation mode It is characterized in that one node is shifted from the data reception mode to the normal operation mode in which normal operation is performed.
- the coil is a motor coil, and the motor coil outputs a motor pulse at regular intervals.
- the operation mode is set to the data reception mode only during a predetermined period during a non-output period of the motor pulse.
- the received data when a predetermined number of identical pieces of received data are received, the received data is stored in a received data storage unit that stores the received data. And a storage control unit for storing data in the storage unit.
- a tenth aspect of the present invention is the ninth aspect of the present invention.
- the reception data storage unit includes a nonvolatile memory unit that stores the reception data in a nonvolatile manner, and a data writing unit that writes the reception data to the nonvolatile memory unit.
- a comparator for generating and outputting received data by comparing the voltage of the data voltage signal with a predetermined reference voltage. It is characterized by that.
- a comparator operation control unit that makes the comparison operation operable only during a predetermined period including a data reception mode. It is characterized by:
- a thirteenth aspect of the present invention is a power supply control unit for supplying operating power to the comparator only during a predetermined period including a data receiving mode in the fl clock according to claim 11. It is characterized by having.
- an amplifier for generating and outputting the reception data by comparing the voltage of the data voltage signal with a predetermined reference voltage. It is characterized by having an overnight.
- a fifteenth aspect of the present invention is directed to a coil, a signal input unit for inputting a signal, and a mode for switching an operation mode between a data reception mode for receiving data and a normal operation mode.
- a data voltage signal which is a voltage signal induced in the coil by a manually input data signal, comprising: a setting unit; and a synchronizing signal based on the synchronizing timing signal when the operation mode is the reception mode.
- An electronic timepiece that generates received data, a receiving unit that receives a signal transmitted through a coil of the electronic timepiece as a received signal, and an adjustment data signal that is generated based on the received signal.
- a transmitting unit for transmitting, and an external device having:
- the coil of the electronic timepiece is a motor coil.
- a mode for switching an operation mode of the electronic timepiece between a data reception mode for receiving data and a normal operation mode is provided.
- the operation mode is synchronized with the operation of the external transmission device based on the external synchronization signal input from the external transmission device that transmits the data signal, and the operation mode is data reception.
- a receiving data generating process for generating and outputting received data based on a synchronizing signal and a synchronizing signal which is a mode and a voltage signal induced in the coil by a data signal inputted from an external transmitting device is characterized by the following.
- the eighteenth aspect of the present invention is characterized in that, in the seventeenth aspect of the present invention, in the mode setting step, the operation is performed when a signal input through the signal input unit is a predetermined signal. It is characterized in that the mode is shifted to the overnight reception mode.
- the fl timepiece is provided with an external operation unit for performing each rare operation, and the operation state of the external operation unit is a predetermined operation state. In the operation state, the mode setting step is characterized by switching the operation mode to the overnight reception mode.
- the coil is a mobile coil, and when the operation mode is the data receiving mode, a power pulse for the mobile coil is provided. It is characterized by having a motor pulse output prohibition process for prohibiting the output of.
- the external synchronization signal is set within a predetermined time after the operation mode shifts to the data reception mode. If no is input, the operation mode shifts from the data reception mode to the normal operation mode in which normal operation is performed.
- the mode setting step is performed when data of a predetermined number of bits is received after the operation mode shifts to the data reception mode.
- the operation mode is characterized in that the operation mode is shifted from the overnight reception mode to the normal operation mode in which the normal operation is performed.
- the coil is a motor coil, and the motor coil outputs a motor pulse at regular intervals.
- the mode setting process is characterized in that the operation mode is set to the data reception mode only during a predetermined period during the non-output period of the motor pulse.
- the received data storing step of storing the received data and the step of receiving the same received data in a predetermined number are performed.
- a data storage control step of storing received data in a received data overnight storage step is performed.
- the receiving data overnight storing step includes a data writing step of writing received data to a nonvolatile memory of the electronic timepiece.
- the electronic timepiece in the seventeenth aspect of the present invention, generates reception data by comparing the voltage of the data voltage signal with a predetermined reference voltage. And a comparator operation control process that enables the comparator to operate only during a predetermined period including the data reception mode.
- a twenty-eighth aspect of the present invention is directed to a coil, a signal input unit for manually inputting a signal, and a mode for switching an operation mode between a data reception mode for receiving data and a normal operation mode.
- a setting unit for adjusting an electronic timepiece having an electronic timepiece comprising: when an operation mode of the electronic timepiece is a reception mode, generating a synchronization signal based on a synchronization timing signal; and inputting a data signal. Based on the data signal and the synchronization signal, the voltage signal induced in the coil by the And causing an external device to receive a signal transmitted through the coil of the electronic watch as a received signal, generate an adjustment data signal based on the received signal, and adjust the electronic clock to the adjustment data. Transmitting a signal.
- Figure 1 is a schematic block diagram of the data transmission system.
- Figure 2 is a schematic block diagram of the analog electronic timepiece.
- FIG. 3 is a schematic configuration block diagram of the external data transmission device.
- FIG. 4 is a schematic configuration block diagram around the detection circuit.
- FIG. 5 is a timing chart of the first embodiment.
- FIG. 6 is a processing flowchart of the first embodiment.
- FIG. 7 is a schematic configuration block diagram of a first modified example.
- FIG. 8 is a schematic configuration block diagram of a second modified example.
- FIG. 9 is a timing chart of the third modification.
- FIG. 10 is a processing flowchart of the fourth modification.
- FIG. 11 is an explanatory diagram of the command.
- FIG. 12 is a schematic block diagram of a data transmission system according to the second embodiment.
- FIG. 13 is a schematic block diagram of a control unit and a transmission / reception unit according to the second embodiment. .
- FIG. 14 is an explanatory diagram of a specific mode when data is actually transmitted and received.
- BEST MODE FOR CARRYING OUT THE INVENTION Next, a preferred embodiment of the present invention will be described with reference to the drawings.
- an analog electronic timepiece having an analog pointer and a data transmission system having an external data writing device for transmitting data to the analog electronic timepiece will be described as an example.
- the present invention can be applied to a watch.
- Figure 1 shows a schematic block diagram of the data transmission system.
- the analog electronic timepiece 103 of the data transmission system 100 is provided with a motor coil 101 and an external operation member 102 such as a crown or a button. Further, the external data transmission device 105 transmits a data signal STR to the analog electronic timepiece 103 via the transmission coil 104.
- examples of the data transmitted as the data overnight signal STR include rate adjustment data, correction data of various sensors, data for switching specifications, and the like.
- Figure 2 shows a schematic block diagram of the analog electronic timepiece.
- the oscillation circuit 11 of the analog electronic timepiece 103 has a crystal oscillator 11 C, and generates a reference pulse signal having a predetermined reference frequency from a reference oscillation signal generated by the crystal oscillator 11 C. .
- the frequency dividing circuit 12 outputs various pulse signals by dividing the frequency of the reference pulse signal output from the oscillation circuit 11.
- the control circuit 13 has a counter 13 A, and an analog electronic clock based on various pulse signals output from the frequency dividing circuit 12 and a storage data of a data storage circuit 17 described later. 10 3 Performs overall control operation.
- the counter 13A detects the elapsed time t from the falling timing of the evening signal described later, and determines whether or not the elapsed time t has reached the predetermined data detection standby time Ta. To detect.
- the detection circuit 14 detects the data signal STR input through the motor coil 101 under the control of the control circuit 13, and outputs the detection data DDS as serial data to the control circuit 13. Output to
- Driving pulse generating circuit 15 generates a driving pulse based on a pulse signal output from frequency dividing circuit 12.
- the drive circuit 16 supplies a drive current to the motor coil 101 based on the drive pulse, and drives the drive motor.
- the data conversion circuit 18 converts the detection data DDS output from the detection circuit 14 via the control circuit 13 from serial to parallel, and outputs it as a parallel detection data DDP to the data storage circuit 17.
- the rate adjusting circuit 19 adjusts the rate to a predetermined value by controlling the frequency division ratio in the frequency dividing circuit 12 based on the parallel detection data DDP stored in the data storage circuit # 1.
- the data storage circuit 17 includes a data writing circuit 17C.
- the data writing circuit 17C includes an EEPROM 17A and a booster circuit 17B.
- the EPROM 17 A stores the parallel detection data DDP in a nonvolatile manner.
- the booster circuit 17B boosts the power supply voltage to generate the write voltage.
- the analog electronic timepiece 103 receives data overnight while being incorporated in the casing as shown in FIG.
- Figure 3 shows a schematic configuration diagram of the external data transmission device.
- the oscillating circuit 21 of the external data transmitting device 105 includes a not-shown oscillator such as a quartz oscillator or a ceramic oscillator, and a reference having a predetermined reference frequency from a reference oscillation signal generated by the oscillator. Generate a pulse signal.
- the frequency dividing circuit 22 outputs various pulse signals by dividing the frequency of the reference pulse signal output from the oscillation circuit 21.
- the control circuit 23 controls the entire external data transmitting apparatus 105 based on the pulse signal output from the frequency dividing circuit 22.
- the configuration of the control circuit 23 may be a microprocessor having a CPU, a ROM, a RAM, and the like, and may be operated by the CPU based on a control program stored in the ROM. Further, the configuration of the control circuit 23 can be configured by a mouth logic circuit instead of the microprocessor configuration.
- the data storage circuit 24 stores various data under the control of the control circuit 23 and outputs the stored various data.
- the PSK modulation circuit 25 shifts the phase of the pulse signal output from the frequency dividing circuit based on the transmission data read from the data storage circuit 24. Performs keying modulation (PSK modulation; Phase Shift Keying modulation).
- the amplification circuit 26 amplifies the output of the PSK modulation circuit 25 and outputs it as a data signal STR via the transmission coil 104.
- the PSK modulation circuit 25 performs modulation by inverting the phase of the reference signal. For example, if the signal level to be transmitted is "H” level, set the phase to 0]. If it is "L” level, set the phase to 180 [:. ].
- a pointer driving unit 19 including a driving circuit 16 and a motor coil 101 is provided around the detection circuit 14.
- the drive circuit 16 includes a P-channel MOS transistor P 1 and an n-channel M ⁇ S transistor N 1 connected in series between the high-potential power supply Vdd and the low-potential power supply VSS. Furthermore, the p-channel M ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ S transistor PI and the n-channel MOS transistor N1 are connected in parallel with a p-channel M ⁇ S transistor connected in series between the high-potential power supply Vdd and the low-potential power supply VSS. It is configured with P2 and n-channel MOS transistor N2.
- the p-channel MOS transistor P1, the n-channel MOS transistor N1, the p-channel MOS transistor P2, and the n-channel MOS transistor N2 are connected to the gate terminal from the drive pulse generation circuit 15 by human input. With the control signal supplied, the p-channel MOS transistor P1 and the n-channel MOS transistor N2 are turned on / off in pairs. Alternatively, the p-channel MOS transistor P2 and the n-channel MOS transistor N1 are turned on / off in pairs by a control signal.
- the drive current flows in the order of the high-potential-side power supply V dd ⁇ p-channel MOS transistor P 1 mode coil 10 l ⁇ n-channel MOS transistor N 2 low-potential side power supply VSS Become.
- the p-channel MOS transistor P2 and the n-channel MOS transistor N1 are on, the p-channel M-S transistor P1 and the n-channel MOS transistor N2 are off.
- the drive current flows in the order of the high-potential power supply Vdd p-channel MOS transistor P 2 mode coil 10 1 ⁇ > n-channel MOS transistor N 1 ⁇ low-potential power supply V SS .
- the motor coil 101 of the pointer driving unit 19 forms a part of the stepping motor 110. Then, the stay 1 1 1 2 of the pointer driving unit 19 is excited by the motor coil 101. Also, the mouth 1 13 is rotated by a magnetic field excited inside the stay 1 1 2.
- the stepping motor 110 is constituted by a PM type (permanent magnet rotating type) in which the mouth 113 is constituted by a disk-shaped two-pole permanent magnet.
- stage 1 1 2 different magnetic poles are generated in the respective phases (poles) 1 1 5 and 1 1 6 around the mouth 1 1 3 due to the magnetic force generated by the coil 1 1
- a magnetic saturation portion 117 is provided to perform the operation.
- an inner notch 118 is provided at an appropriate position on the inner periphery of the stay 112 in order to regulate the rotation direction of the rotor 113.
- the inner notch 118 generates a cogging torque so that the mouth 113 stops at an appropriate position.
- the second hand 1 3 1 is connected to the center wheel of the fourth wheel 1 2 2, the minute hand 1 3 2 is connected to the second wheel 1 2 4, and the hour hand 1 3 3 is connected to the hour wheel 1 2 6 Have been.
- the time is displayed by each of these hands in conjunction with the rotation of the roe 1 1 3. It is of course possible to connect a transmission system (not shown) for displaying the date and time to the train wheel 120.
- the detection circuit 14 is composed of the reference voltage generation circuit 31, the comparator 32, and the ⁇ channel.
- the MOS transistor N3 is provided.
- the reference voltage generation circuit 31 of the detection circuit 14 generates the reference voltage VREF.
- the comparator 32 compares the voltage V02 of the output terminal 02 of the drive circuit 16 with the reference voltage VR EF and outputs a detection data DDS.
- the n-channel MOS transistor N 3 supplies power to the comparator 32 based on the sampling drive signal SSP from the control circuit 13.
- FIG. 5 shows an evening chart of the embodiment
- FIG. 6 shows a processing flowchart of the embodiment.
- the number of data bits to be read in one reception mode transition is X bits (X: natural number).
- the external operation member 102 is operated (see FIG. 5A), and at time t0, the analog electronic timepiece 103 is shifted to the reception mode (step S1).
- the operation of the external operation member needs to be somewhat complicated in order to prevent the user from shifting to the unintended data reception mode.
- step S2 When an operation for shifting to the overnight reception mode is performed, irregular hand movement is started to notify the user that the operation mode of the electronic analog clock is the overnight reception mode (step S2). .
- an irregular hand operation such as, for example, a 5-second hand movement that moves the second hand at 5-second intervals is performed.
- a 5-second hand movement that moves the second hand at 5-second intervals.
- the output terminal 02 of the drive circuit 16 becomes high as shown in FIG. It becomes an impedance state and becomes an electrically floating state.
- the output terminal 02 of the drive circuit 16 enters a high impedance state.
- the sampling drive signal SSP is set to the “H” level (see FIG. 5 (b)), and the c-channel MOS transistor N3 is also turned on.
- the operating power is supplied to the comparator 32, and the comparator 32 enters an operating state.
- the control circuit 13 determines whether or not the timing signal STM (see FIG. 5 (c)) has been received as the data signal STR via the motor coil 101 and the detection circuit 14 (step S). 3)
- the timing signal STM is preferably a rectangular wave having a higher reception level from the viewpoint of the reception level.
- step S3 if the timing signal STM has not been received (step S3; No), it is determined whether or not the elapsed time t after the transition to the reception mode has exceeded the predetermined standby time TC. Is determined (step S9).
- step S9 if the elapsed time t ′ does not exceed the standby time TC, that is,
- Step S9 In the case of (Step S9; No), the processing shifts to Step S3 again, and the same processing is performed thereafter.
- the reception mode is ended to reduce power consumption due to unnecessary operation of the comparator 32, and the mode is returned to the normal mode. I do.
- the reception mode is terminated, and the mode is returned to the normal mode (step S8).
- step S3 when a timing signal as shown in FIG. 5 (c) is received (step S; Yes), the control circuit 13 counts the counter 13A. Start operation. Then, as shown at time t1 in FIG. 5, the counter 13A is reset at the falling timing of the timing signal. Further, synchronization between the analog electronic timepiece and the external data transmission device 105 is established.
- the analog electronic timepiece is in a data waiting state.
- control circuit 13 determines whether or not the elapsed time t from the falling timing of the timing signal exceeds a predetermined data detection standby time Ta based on the count state of the counter 13A. (Step S4).
- step S4 If it is determined in step S4 that the elapsed time t has not exceeded the data detection standby time Ta, the process in step S4 is repeated, and the standby state is maintained.
- Step S4 In the case of (Step S4; No), the process of Step S4 is repeated, and the standby state is maintained as it is.
- step S4 if the elapsed time t exceeds the data detection waiting time Ta, data transmission is started.
- 3 1 ⁇ Modulation circuit 25 performs phase shift keying modulation of the pulse signal output from the frequency divider circuit based on the transmission data read from data storage circuit 24 under the control of control circuit 23, Output to amplifier circuit 26.
- the amplification circuit 26 amplifies the output of the PSK modulation circuit 25 and outputs it as the data signal STR via the transmission coil 104.
- the data signal STR at this time is a sine wave modulated by PSK, and its phase is inverted by 180] depending on the signal level ("H" or "L”) of the data transmission.
- the analog electronic timepiece 103 sets the data read evening signal S RD (see FIG. 5 (j)) to the “H” level as shown at time t2. Furthermore, it detects the signal level of the detection data D DS (see Figure 5 (i)) and reads 1-bit data. Data reading is performed (step S5).
- the detection signal DDS at the "H" level is output.
- control circuit 13 adds 1 to the value of the data bit count N, that is,
- Step S6 This means that the N-bit data has already been received.
- step S7 it is determined whether or not the number of received data bits has become equal to X bits.
- step S7 if the number of bits of the received data is less than X bits,
- Step S7 the time t "elapsed from the detection timing (time t2) of the previous detection data DDS signal level is equal to the predetermined data detection standby time Tb. Whether it was exceeded,
- step S10 It is determined whether or not the condition is satisfied.
- step S10 if the elapsed time t "does not exceed the overnight detection standby time Tb,
- Step S10 In the case of (Step S10; No), the process of Step S10 is repeated, and the standby state is kept as it is.
- step S10 when the elapsed time t "exceeds the data detection standby time Tb, the data read timing signal SRD is output as shown at time t3 in FIG. 5 (c). The level is set to “H.” Further, the signal level of the DDS is detected, and data reading for reading 1-bit data is performed (step S5). At this time, the induced voltage V02 induced at the output terminal 02 is compared with the reference voltage VREF by the comparator 32, and the data signal DDS is output.
- the voltage level of the induced voltage VO2 is detected by the comparator 32 at every data detection standby time Tb synchronized with the frequency of the data signal STR. Then, the data converter 18 performs a serial / parallel conversion of the detection data DDS to generate parallel detection data DDP.
- the generated parallel detection data DDP is stored in the data storage circuit 17.
- modulation is PSK modulation
- ASK (Amplitude Shift Keying) modulation with synchronized timing may be used so that the amplitude becomes a peak in the data capture timing signal SRD.
- the counter for measuring the times Ta and Tb can be shared, and the circuit can be simplified.
- step S7 If it is determined in step S7 that the number of bits of the received data is X,
- the reception mode is terminated and the mode is returned to the normal mode (step S8).
- the rate adjusting circuit 19 controls the dividing ratio in the frequency dividing circuit 12 based on the parallel detection data DDP stored in the data storage circuit 17 to adjust the rate to a predetermined value, and This will improve the timekeeping accuracy.
- the input terminal of comparator 32 is one output terminal Output terminal 02 was connected to the 2 side.
- the voltage of the output terminal 01 and the voltage of the output terminal 02 is suitable for detection for each analog electronic timepiece due to a difference in a structure or an assembled state. is there.
- FIG. 7 shows a schematic block diagram of the first modification.
- the first modified example is different from the above-described embodiment in that a detection circuit 14-1 is provided instead of the detection circuit 14 in FIG.
- the same parts as those in FIG. 4 are denoted by the same reference numerals.
- the reference voltage generation circuit 31 of the detection circuit 14-1 generates the reference voltage VREF.
- the comparator 41 compares the voltage V01 of the output terminal 01 of the drive circuit 16 with the reference voltage VREF and outputs a detection signal DDS1.
- the comparator 32 compares the voltage V02 of the output terminal 02 of the drive circuit 16 with the reference voltage VREF and outputs a detection signal DDS2.
- the n-channel M ⁇ S transistor N 3 supplies power to the comparator 32 based on the sampling drive signal S SP2 from the control circuit 13.
- the n-channel M ⁇ S transistor N 4 supplies power to the comparator 41 based on the sampling drive signal S SP1 from the control circuit 13.
- the latch circuit 42 is configured by a D-flip-flop circuit or the like, and latches the detection data DDS1.
- the latch circuit 43 is constituted by a D-flip-flop circuit or the like, and latches the detected data DDS2.
- the selection circuit 44 selects either the detection data D DS1 or the detection data D DS2 and outputs it as the detection data D DS.
- the selection circuit 44 selects the detection data DDS1 or the detection data DDS2 is determined in advance according to the target analog electronic clock. Shall be kept. However, it is also possible to adopt a configuration in which the voltage is dynamically selected according to the magnitude relationship between the voltage V01 of the output terminal 01 and the voltage V02 of the output terminal 02. Next, the outline operation of the detection circuit 14-1 will be described.
- the sampling drive signal SSP1 is set to the “H” level. Further, the n-channel MOS transistor N4 is also turned on, and the operating power is supplied to the comparator 41, so that the comparator 41 is turned on.
- the comparator 41 compares the voltage V01 of the output terminal 01 of the drive circuit 16 with the reference voltage VREF and outputs the detected data DDS1 to the latch circuit 42.
- sampling drive signal SSP2 is set to the “H” level in parallel with the output terminal 02 of the drive circuit 16 entering the high impedance state. Further, the n-channel MOS transistor N3 is also turned on. Accordingly, the operation power is supplied to the comparator 32, and the comparator 32 is brought into an operation state.
- the comparator 32 compares the voltage V02 of the output terminal 02 of the drive circuit 16 with the reference voltage VREF and outputs the detection data DDS2 to the latch circuit 43.
- the latch circuit 42 holds the detection data DDS1 and the latch circuit 43 holds the detection data DDS2.
- the selection circuit 44 selects the latch circuit in a manner determined in advance as to which of the detection data DDS1 and the detection data DDS2 is to be selected. Then, the detection and data corresponding to the selected latch circuit are output as the detected data DDS.
- the comparator 32 is used to detect the detection data DDS.
- an inverter circuit may be used instead of the comparator 32.
- VREF1 (Vdd- VSS) / 2
- the degree of freedom in setting the detection level is lost.
- FIG. 8 shows a schematic block diagram of the second modified example.
- the second modification is different from the second modification in that a detection circuit 14-2 is provided instead of the detection circuit 14-1 in FIG.
- a detection circuit 14-2 is provided instead of the detection circuit 14-1 in FIG.
- FIG. 7 the same parts as those in FIG. 8 are denoted by the same reference numerals.
- the sensing circuit 14-2 of the detection circuit 14-2 compares the voltage V01 of the output terminal 01 of the drive circuit 16 with the reference voltage VREF1 and outputs the detection data DDS1.
- the inverter circuit 52 compares the voltage V02 of the output terminal ⁇ 2 of the drive circuit 16 with the reference voltage VREF1, and outputs detection data DDS2.
- the latch circuit 42 is constituted by a D flip-flop circuit or the like, and latches the detection data DDS1.
- the latch circuit 43 is configured by a D-flip-flop circuit or the like, and latches the detection data DDS2.
- the selection circuit 44 selects either the detection data DDS1 or the detection data DDS2 and outputs it as the detection data DDS.
- whether the selection circuit 44 selects the detection data D DS1 or the detection data D DS2 is determined in advance in accordance with the target analog electronic clock. Shall be kept.
- the voltage is dynamically selected according to the magnitude relationship between the voltage V01 of the output terminal 01 and the voltage V02 of the output terminal 02.
- the modulation is PSK modulation, ASK (Amplitude Shift Keying) modulation in which the evening timing is adjusted so that the amplitude peaks at the timing corresponding to the de-synchronization capturing evening signal SRD. Absent.
- the counter for measuring the time Ta and Tb can be shared, and the circuit can be simplified.
- the inverter circuit 51 outputs detection data DDS1 indicating whether the voltage V01 of the output terminal 01 of the drive circuit 16 has exceeded the threshold voltage VREF1 of the inverter circuit 51. Output to switch circuit 42.
- the inverter circuit 52 outputs a detection signal indicating whether the voltage V 02 of the output terminal ⁇ 2 of the drive circuit 16 has exceeded the threshold voltage VREF2 of the receiver circuit 52.
- DDS2 is output to the latch circuit 43.
- the threshold voltages VREF1 and VREF2 of each of the inverter circuits 51 and 52 are almost the same when they are configured as an integrated circuit.
- the latch circuit 42 holds the detection data D DS1
- the latch circuit 43 holds the detection data D DS2.
- the selection circuit 44 selects a latch circuit as to determine which of the detection data DDS1 and the detection data DDS2 is to be selected in advance. Then, the detection data corresponding to the selected latch circuit is output as the detection data DDS.
- both the voltages of the output terminals # 1 and # 2 can be subjected to the detection data DDS.
- the third modification is a modification in which the mode automatically shifts to the data reception mode during the non-monitoring pulse output period between a certain motor pulse output timing and the next motor pulse output timing. It is an example.
- FIG. 9 shows a timing chart of the third modification.
- a motor pulse for driving the second hand is output every second (see FIG. 9 (a)). C Then, a time t 0 when a predetermined time T d elapses from the output completion timing of each motor pulse. , The sampling drive signal S SP is set to the “H” level (see FIG. 9 (b)).
- the output terminal 02 of the drive circuit 16 becomes a high impedance state and becomes electrically floating.
- the sampling drive signal SSP is set to the “H” level (see FIG. 9 (b)). Therefore, the n-channel MOS transistor N3 is also turned on, and the operating power is supplied to the comparator 32 to be in the operating state.
- control circuit 13 determines whether or not the timing signal STM (see FIG. 9 (c)) has been received as the data signal STR via the motor coil 101 and the detection circuit 14.
- the control circuit 13 starts the count operation of the counter 13A. Further, as shown at time t1 in FIG. 9, the counter 13A is reset at the falling edge of the timing signal. Further, the synchronization between the analog electronic timepiece and the external data transmission device 105 is established, and the analog electronic timepiece is in a standby state overnight.
- control circuit 13 determines whether or not the elapsed time t from the falling timing of the timing signal exceeds the predetermined data detection standby time Ta based on the count state of the counter 13A. Is determined. That is,
- the PSK modulation circuit 25 performs a phase shift of the pulse signal output from the frequency dividing circuit based on the transmission data read out from the data storage circuit 24. Modulation is performed and output to the amplification circuit 26.
- the amplification circuit 26 amplifies the output of the PSK modulation circuit 25 and outputs it as a data signal STR via the transmission coil 104.
- the data signal STR at this time is a PSK modulated sine wave, and the phase is inverted by 180 [°] depending on the signal level ("H" or "L”) of the transmission data.
- the analog electronic timepiece 103 sets the overnight reading evening signal SRD (see FIG. 9 (j)) to the "H" level. Then, the signal level of the detection data DDS (see Fig. 9 (i)) is detected, and data reading for reading 1-bit data is performed.
- the level of the detection data DDS becomes "H” and the 1-bit data becomes "1".
- control circuit 13 adds 1 to the value of the data bit number counter N, that is,
- time t 2 It is determined whether or not the time t "elapsed since the last detection of the DDS signal level (time t 2) has exceeded the predetermined data detection standby time Tb. That is,
- the data read timing signal SRD is set to the" H "level as shown at time t3 in FIG. 9 (j). Then, the signal level of the detection data DDS is detected, and data reading is performed to read 1-bit data.
- the induced voltage V02 induced at the output terminal # 2 is compared with the reference voltage VREF by the comparator 32, and the data signal DDS is output.
- the voltage level of the induced voltage VO2 is detected by the comparator 32 every data detection standby time Tb synchronized with the frequency of the data signal STR. Then, in the data conversion circuit 18, the detection data DDS is subjected to serial / parallel conversion and is stored in the data storage circuit 17 as parallel detection data DDP.
- the data reception mode is ended.
- FIG. 10 shows a processing flowchart of the fourth modification.
- the difference from the processing flowchart of FIG. 6 is that after the data reading process, the receiving mode is terminated and the mode is returned to the normal mode if the read data is an end instruction code. is there.
- a set of data command strings is composed of an instruction code part of 4 bits and a data part of 8 bits.
- the end instruction code for terminating the reception mode is the instruction code part 2 “0 101”, and the data part is set to dummy data.
- the instruction code part 2 is set to “1001”, and the data constituting data A is set in the data part.
- the instruction code part is set to “101 1”, and the data constituting data C is set in the data part.
- the analog electronic timepiece that has received the end instruction code shifts the operation mode to the normal operation mode, and resumes normal hand operation.
- the external data transmission device in the data transmission system, can only transmit data to the analog electronic timepiece, but the data transmission system of the second embodiment is You can send and receive.
- FIG. 12 shows a schematic block diagram of a data transmission system according to the second embodiment.
- the data transmission system 10 OA is roughly divided into a control unit 61, a transmission / reception unit block 62, and a switching unit 63, and a plurality of analog electronic clocks (not shown) corresponding to the transmission / reception unit block 62. 103 are arranged in a manner as shown in FIG.
- the control unit 61 controls the entire data transmission system.
- Each transmission / reception block 62 transmits and receives data to and from the corresponding analog slave clock 103.
- the transmission / reception unit block 62 includes a plurality (10 sets in FIG. 12) of transmission / reception units 65_1 to 65-10 that are simultaneously driven. Therefore, one transmission / reception unit block 62 can transmit and receive data simultaneously with 10 analog electronic watches simultaneously.
- the switching unit 63 switches the transmission / reception unit block 62 actually controlled under the control of the control unit 61.
- Figure 13 shows a schematic block diagram of the control unit and the transmission / reception unit.
- the transmission / reception units 65-1 to 65-10 have the same configuration, the transmission / reception unit 65-1 will be described as an example.
- the reference clock signal generation circuit 71 of the control unit 61 receives the reference clock signal CR. Generates EF.
- the divider 72 divides the reference clock signal C REF and outputs a divided clock signal C REFD.
- the data calculation circuit 73 calculates and outputs the correction data DC based on the measurement data (for example, the rate measurement data).
- the PSK modulation circuit 74 performs PSK (Phase Shift Keying) modulation based on the correction data DC and the frequency-divided clock signal C REFD, and outputs a modulation signal SEN to the switching unit.
- PSK Phase Shift Keying
- the control circuit 75 controls the switching unit 63 with the entire control unit 61 and the switching control signal SSW.
- the amplifying circuit 81 of the transmission / reception unit 65-1 amplifies the modulation signal SEN input manually via the switching unit 63.
- the switch 82 switches between transmission and reception.
- the transmission / reception coil 83 transmits / receives data to / from a corresponding analog electronic timepiece.
- the amplification circuit 84 amplifies the reception signal SRC received from the analog electronic timepiece via the transmission / reception coil 83.
- the data detection circuit 85 detects the transmitted data from the output signal of the amplification circuit 84 and outputs the data to the control unit 61 via the switching unit 63.
- the analog electronic timepiece 103 is connected to the transmitting and receiving coil 83 in the state of a completed product built in the casing as shown in FIG. They are located close together and transmit and receive data using magnetic field signals.
- the reference clock signal generation circuit 71 of the control unit 61 generates a reference clock signal C REF and outputs it to the frequency dividing circuit 72.
- the dividing circuit 72 divides the reference clock signal C REF by dividing the frequency of the reference clock signal C REF. Is output to the PSK modulation circuit 74.
- the data calculation circuit 73 calculates the correction data DC based on the measurement data under the control of the control circuit 75, and outputs it to the PSK modulation circuit 74.
- 31 ⁇ modulation circuit 74 performs PSK modulation based on correction data DC and frequency-divided clock signal CREFD. Then, the PSK modulation circuit 74 outputs the modulation signal SEN to the switching unit 63.
- the switching unit 63 connects the control unit 61 to the transmission / reception unit 65-1 on which the analog electronic clock 103 to which the modulation signal SEN is to be sent is mounted.
- the amplifier circuit 81 of the transmission / reception unit 65-1 amplifies the modulation signal SEN input via the switching unit 63. Then, the amplification circuit 81 outputs to the transmission / reception month j coil 83 via the switching switch 82.
- the data is transmitted to the analog electronic timepiece 103 via the transmission / reception coil 83.
- the analog electronic timepiece 103 transmits data from the motor coil to the control unit 61 by a motor pulse or the like, the received signal SRC is input to the amplifier circuit 84 via the transmission / reception coil 83.
- the amplification circuit 84 amplifies the received signal and outputs it to the data detection [Ql path 85].
- the present invention is applicable not only to the watch coil, but also to other watches such as a digital clock as long as the watch has a coil capable of contactless communication.
- the analog electronic timepiece having only the analog pointer has been described.
- the present invention can also be applied to a digital clock that performs digital display and a digital electronic clock with digital display that performs digital display of the measurement results of various measurement sensors on a liquid crystal display device.
- the gist of the present invention may be applied to portable electronic devices using motor coils other than analog electronic watches, for example, portable CD players, portable MD (Mini Disc) players (recorders), portable cassette players (recorders), and the like. .
- a configuration is adopted in which the mode shifts to the data reception mode in accordance with the operation state of the external operation member 102 or the non-output period of the motor pulse.
- a conduction terminal in a place where it does not stand, and to input a signal by applying a probe to the conduction terminal.
- a light receiving element and to shift to the data receiving mode by inputting an optical signal of a predetermined pattern to the light receiving element.
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Electromechanical Clocks (AREA)
- Electric Clocks (AREA)
- Measurement Of Unknown Time Intervals (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00961056A EP1143309B1 (en) | 1999-09-17 | 2000-09-18 | Electronic timepieceand method of controlling and electronic timepiece |
DE60040267T DE60040267D1 (de) | 1999-09-17 | 2000-09-18 | Elektronische uhr, und verfahren zum kontrollieren einer elektronischen uhr |
HK01108016.2A HK1037744A1 (en) | 1999-09-17 | 2001-11-14 | Electronic timepiece and method of controlling and electronic timepiece |
US10/959,684 US7095679B2 (en) | 1999-09-17 | 2004-10-06 | Electronic timepiece, control method for electronic timepiece, regulating system for electronic timepiece, and regulating method for electronic timepiece |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26447299 | 1999-09-17 | ||
JP11/264472 | 1999-09-17 |
Related Child Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09856187 A-371-Of-International | 2000-09-18 | ||
US85618701A A-371-Of-International | 1999-09-17 | 2001-05-16 | |
US10/288,064 Continuation-In-Part US6850468B2 (en) | 1999-09-17 | 2002-11-05 | Electronic timepiece, control method for electronic timepiece, regulating system for electronic timepiece, and regulating method for electronic timepiece |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001022175A1 true WO2001022175A1 (fr) | 2001-03-29 |
Family
ID=17403708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2000/006354 WO2001022175A1 (fr) | 1999-09-17 | 2000-09-18 | Compteur de temps electronique; technique de commande et methode de reglage dudit compteur de temps |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1143309B1 (ja) |
CN (1) | CN1258698C (ja) |
DE (1) | DE60040267D1 (ja) |
HK (1) | HK1037744A1 (ja) |
WO (1) | WO2001022175A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003016568A (ja) * | 2001-06-28 | 2003-01-17 | Tokyo Gas Co Ltd | メータ制御器 |
JP2004020218A (ja) * | 2002-06-12 | 2004-01-22 | Seiko Epson Corp | 時計システムおよび時計システムの制御方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4398049A1 (fr) * | 2022-12-19 | 2024-07-10 | ETA SA Manufacture Horlogère Suisse | Montre électromécanique capable de communiquer sans contact avec un dispositif de communication |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06258464A (ja) * | 1993-03-09 | 1994-09-16 | Citizen Watch Co Ltd | データ送信機能付電子時計 |
EP0635771A1 (en) * | 1993-01-08 | 1995-01-25 | Citizen Watch Co. Ltd. | Data transmission/reception system of electronic timepiece |
JPH1184028A (ja) * | 1997-09-03 | 1999-03-26 | Citizen Watch Co Ltd | 電子時計の送受信システム |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100338537C (zh) * | 1997-06-05 | 2007-09-19 | 西铁城钟表株式会社 | 电子表发送/接收系统 |
-
2000
- 2000-09-18 CN CNB008028605A patent/CN1258698C/zh not_active Expired - Fee Related
- 2000-09-18 EP EP00961056A patent/EP1143309B1/en not_active Expired - Lifetime
- 2000-09-18 WO PCT/JP2000/006354 patent/WO2001022175A1/ja active IP Right Grant
- 2000-09-18 DE DE60040267T patent/DE60040267D1/de not_active Expired - Lifetime
-
2001
- 2001-11-14 HK HK01108016.2A patent/HK1037744A1/xx not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0635771A1 (en) * | 1993-01-08 | 1995-01-25 | Citizen Watch Co. Ltd. | Data transmission/reception system of electronic timepiece |
JPH06258464A (ja) * | 1993-03-09 | 1994-09-16 | Citizen Watch Co Ltd | データ送信機能付電子時計 |
JPH1184028A (ja) * | 1997-09-03 | 1999-03-26 | Citizen Watch Co Ltd | 電子時計の送受信システム |
Non-Patent Citations (1)
Title |
---|
See also references of EP1143309A4 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003016568A (ja) * | 2001-06-28 | 2003-01-17 | Tokyo Gas Co Ltd | メータ制御器 |
JP2004020218A (ja) * | 2002-06-12 | 2004-01-22 | Seiko Epson Corp | 時計システムおよび時計システムの制御方法 |
Also Published As
Publication number | Publication date |
---|---|
HK1037744A1 (en) | 2002-02-15 |
EP1143309A1 (en) | 2001-10-10 |
EP1143309B1 (en) | 2008-09-17 |
CN1337015A (zh) | 2002-02-20 |
CN1258698C (zh) | 2006-06-07 |
EP1143309A4 (en) | 2005-03-16 |
DE60040267D1 (de) | 2008-10-30 |
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