EP1133852A2 - Procede et appareil d'acheminement dans un reseau a commutation de circuits - Google Patents

Procede et appareil d'acheminement dans un reseau a commutation de circuits

Info

Publication number
EP1133852A2
EP1133852A2 EP99970232A EP99970232A EP1133852A2 EP 1133852 A2 EP1133852 A2 EP 1133852A2 EP 99970232 A EP99970232 A EP 99970232A EP 99970232 A EP99970232 A EP 99970232A EP 1133852 A2 EP1133852 A2 EP 1133852A2
Authority
EP
European Patent Office
Prior art keywords
data packet
channel
channels
bitstream
isochronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99970232A
Other languages
German (de)
English (en)
Inventor
Per Lindgren
Christer Bohm
Bengt J. Olsson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Net Insight AB
Original Assignee
Net Insight AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Net Insight AB filed Critical Net Insight AB
Publication of EP1133852A2 publication Critical patent/EP1133852A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4637—Interconnected ring systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/201—Multicast operation; Broadcast operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags

Definitions

  • the present invention refers to a method and an apparatus for providing routing of asynchronous traffic in a circuit switched synchronous time division multi- plexed network, more specifically in a DTM network.
  • DTM Dynamic synchronous Transfer Mode
  • DTM DTM Gigabit Network
  • Christer Bohm Christer Bohm
  • Per Lindgren Lars Ramfelt
  • Peter Sj ⁇ din Journal of High Speed Networks, 3 (2) : 109-126, 1994
  • Multi-gigabit networking based on DTM Lars Gauffin, Lars Hakansson, and Bj ⁇ rn Pehrson, Computer networks and ISDN Systems, 24 (2) :119-139, April 1992.
  • the basic topology of a DTM network is preferably a bus with two unidirectional, multi-access, multi-channel optical fibers connecting a number of nodes.
  • the topology may just as well be any other kind of structures e.g. a ring structure or a hub structure.
  • each wavelength on the bus i.e. each bitstream on each fiber
  • the bandwidth of each wavelength on the bus is divided into recurrent fixed length frames, which in turn are divided into fixed size time slots.
  • the number of slots in a frame thus depends on the network's bit-rate.
  • the time slots are divided into two groups, control slots and data slots.
  • Control slots are typically used for transferring of signaling messages between said nodes for the network's internal operation.
  • the data slots are typically used for the transfer of data between end users connected to the different nodes.
  • Each node is arranged to dynamically establish, terminate, and modify DTM channels by dynamically allocating time slots thereto.
  • DTM channels When DTM channels are used for transferring asynchronous traffic, such as TCP/IP packets, a mechanism for providing routing of said packets through the DTM network is needed.
  • current available routing solutions are typically developed for use in other kinds of network architectures and therefore suggest mechanism that results in poor use of the advantageous aspects of a network of the DTM kind.
  • a multi-channel multi-access bitstream carrying isochronous channels is accessed, said isochronous channel being used for the transfer of asynchronous traffic, and a data packet from a node connected to said bitstream is received in an isochronous channel thereof. Then, it is determined if said data packet is to be transmitted to another node connected to said bitstream using another channel of said isochronous channels. If so, said data packet is transmitted to said another node using said another channel of said isochronous channels on said bitstream.
  • the invention thus provides routing of data packets among isochronous channels of one and the same multichannel multi-access bitstream.
  • a router is provided to interconnect two or more separate networks or, network sections, and to provide routing of data packets between such network sections.
  • the routing solution according to the invention differs from this conventional approach in that routing is provided among the channels of a single multi-channel multi-access bitstream. Consequently, a routing mechanism according to the invention, providing routing among channels of a single bitstream, need not be provided at an exit point of the bitstream, i.e. at the point of inter- connection to another bitstream. Note, however, that this does not mean that a routing mechanism according to the invention is limited to routing with respect to channels of one single bitstream only, as one may use conventional routing from said bitstream to another bitstream as well without departing from the scope of the invention.
  • the routing mechanism provides the network designer with a greater freedom of architecture when designing networks. An example thereof will be described below with reference to Fig. 5.
  • channels of said bitstream that are not to be routed by said routing mechanism are not accessed by said routing mechanism. Instead, such channels are bypassed, typically at the interface of an apparatus providing said routing mecha- nism. Consequently, the traffic in said bypassed channels will be unattended and unaffected by said routing mechanism.
  • this requires the provision of means for separating channels of said isochronous channels that are to be received and channels that are not to be received.
  • a channel which carries asynchronous traffic that is to be routed by the routing apparatus but however also extends beyond the routing apparatus, i.e. a mulicasted channel that isn't set to terminate at the routing apparatus, further propagation of said data packet to other nodes connected to said bitstream using the isochronous channel from which said data packet was received is uninhibited.
  • a channel may be a multicast channel wherein a data packet will reach a set of receivers, but wherein said data packet will at the same time be routed to another channel of said bitstream, for example to reach another set of receivers.
  • a preferred use of the invention is in a network operating according to a Dynamic synchronous Transfer Mode (DTM) protocol, i.e. a so called DTM network, said isochronous channels then being DTM channels in said DTM network.
  • DTM Dynamic synchronous Transfer Mode
  • a DTM network is a circuit switched time division multiplexed network of the kind wherein information is transferred between nodes of the network on bitstreams.
  • Each bit- stream is divided into regularly recurrent, essentially fixed size frames, so called DTM frames, each comprising a number of fixed size time slots, said time slots being separated into control slots and data slots.
  • Control slots are used for control signaling between nodes of the network
  • data slots are used for the transfer of user data (sometimes often referred to as payload data) .
  • write access to the time slots of a DTM frame is distributed among nodes being attached to the bitstream carrying said DTM frame, each node typically having write access to a respective at least one control slot and a respective dynamically adjustable set of data slots within each recurrent frame.
  • having write access to a time slot position in a frame means having write access to said time slot position within each recurrent frame.
  • a node In a DTM network, a node will use the data slots it has write access to for establishing so called DTM channels by allocating one or more of said data slots to each respective DTM channel.
  • a DTM channel is defined by one or more time slots occupying the same time slot position within each DTM frame of the bitstream upon which said DTM channel is carried.
  • the channel may of course be defined by a different set of time slot positions on the two bit- streams.
  • a DTM channel may be either a control channel or a data channel, depending on whether control or data slots that is allocated to said channel.
  • a DTM channel may be uni-, multi- or broadcast.
  • DTM channels may be dynamically established, terminated, or modified, the latter by changing the number of time slots allocated to a DTM channel. Also, the distribution of write access to time slot among different nodes may be dynamically modified as different nodes develop different needs for control signaling and data transfer.
  • a routing mechanism is performed in relation to a memory that provides temporary storing of data packets at memory locations thereof, said memory locations being temporarily allocated for storing respective data packets.
  • This memory is then accessed for storing/transmission of data packets irrespective of which channel a data packet is received upon/- transmitted into, and is thus used as a shared memory shared by all channels.
  • FIG. 1 shows en example of the structure of a bit- stream in a DTM network
  • Fig. 2 illustrates transfer of asynchronous traffic in one of the isochronous channels carried by the bitstream shown in Fig. 1;
  • Fig. 3 shows an exemplifying embodiment of an apparatus according to the invention
  • Fig. 4 shows another exemplifying embodiment of an apparatus according to the invention
  • Fig. 5 shows a network comprising the apparatus shown in Fig 4.
  • a multi-channel multi-access bitstream B in a circuit switched time division multiplexed network operating according to a DTM protocol will now be described with reference to Fig. 1.
  • the bitstream B is divided into recurrent, essentially fixed sized frames, wherein the start of each frame is defined by a frame synchronization time slot F and each frame ends with one or more guard band time slots G.
  • Each frame is further divided into a plurality of fixed sized, typically 64 bit, time slots.
  • a nominal frame duration of 125 ⁇ s, a time slot size of 64 bits, and a bit rate of 2Gbps the total number of time slots within each frame will be approximately 3900.
  • the time slots are divided into control slots Cl, C2, C3, and C4, and data slots Dl, D2, D3, and D4.
  • Write access to the control and data slots are distributed among the nodes connected to the bitstream.
  • a node Nl (connected to the bitstream B) will have access to a control slot Cl and a set of data slots Dl within each frame of the bitstream
  • a node N2 (also connected to the bitstream) will have access to a control slot C2 and a set of data slots D2 within each frame of the bitstream, and so on.
  • the set of slots allo- cated to a node as control slot(s) and/or data slot(s) occupy the same slot position within each frame of the bitstream.
  • the control slot Cl belonging to node Nl will occupy the second time slot within each frame of the bitstream.
  • each node may increase or decrease its access to control and/or data slots, thereby re-distributing the access to control slots and/or data slots among the nodes. For example, a node having a low transfer capacity demand may give away its access to data slots to a node having a higher transfer capacity demand.
  • the slots allocated to a node need not be consecutive slots, but may reside anywhere within the frame.
  • node N2 having access to its control slot C2 and its range of data slots D2 has established four channels CHI, CH2, CH3, and CH4 on the bitstream. As shown, each channel is allocated a respective set of slots.
  • the transfer capacity of channel CHI is larger than the transfer capacity of channel 2, since the number of time slots allocated to channel CHI is larger than the number of time slots allocated to channel CH2.
  • the time slots allocated to a channel occupy the same time slot positions within each recurrent frame of the bitstream.
  • channel CH3 comprises seven time slots within each frame on bitstream B
  • the first seven time slots transmitted in the channel CH3 i.e. the first seven time slots in Fig. 2
  • Fig. 2 shows three packets transmitted in channel CH3.
  • Each packet is encapsulated according to a predefined encapsulation protocol.
  • each packet shall be divided into 64 bit data blocks (the size of a time slot) , that a start_of_packet slot S is to be added to the start of each packet, and that an end_of_packet slot E is to be added to the end of each packet, thereby forming encapsulated packets PI, P2, and P3.
  • the bitstream is provided with so called idle slots, identifying said gaps as not providing valid data.
  • the apparatus 110 comprises a port 111, which in turn comprises an incoming channel interface 113 and an outgoing channel interface 114 providing read and write access, respectively, to a bitstream B, which for example may be the bitstream B shown in Fig. 1.
  • the in- coming and outgoing channel interface will provide for synchronization of the operation of the apparatus in relation to the frame and slot rate on the bitstream B.
  • the incoming channel interface and the outgoing channel interface are connected to an incoming channel manager 115 and an outgoing channel manager 116, respectively.
  • the incoming channel manager 115 and the outgoing channel manager 116 are both connected to a routing processor 117, a shared memory 119, a buffer manager 120, and a control unit 121.
  • the routing processor 117 is in turn connected to a routing memory 118.
  • the incoming channel interface 113 will receive (arrow 1) data packets from the channels monitored by said interface, such as the encapsulated TCP/IP packets on channel CH3 as shown in Fig. 2.
  • the incoming channel interface 113 will then forward, with preserved sequential order, each received data block forming said packet to the incoming channel manager 115 (arrow 2) .
  • Each block forwarded to the incoming channel manager 115 is accompanied by a channel identifier, designating the channel from which it was received.
  • the incoming channel manager Having received sufficiently many data blocks at the head end of a packet to be able to derive information designating the size of the packet, the incoming channel manager will send a request (arrow 3) , containing the size of the packet, to the buffer manager 120. The request will thereby inform the buffer manager 120 that the incoming channel manager 115 needs to store a packet of the designated size in the shared memory 119.
  • the buffer manager 120 will then allocate an address space of the shared memory 119 to said packet.
  • the buffer manager 120 will answer the request by returning (arrow 4) a start address corresponding to the start of said address space to the incoming channel manager 115.
  • the incoming channel manager Having received said start address from the buffer manager 120, the incoming channel manager will start writing the data blocks forming the associated packet into the shared memory 119 (arrow 5) , starting at the start address received from the buffer manager 120 and incrementing the address one step for each data block written into the shared memory 119.
  • the incoming channel manager 115 sends the start address received from the buffer manager 120, along with the IP address designated in the header of the packet, to the routing processor 117 (arrow 6) .
  • the routing processor will, based upon the destination address recei- ved from the incoming channel interface 115, determine whether or not the associated packet is to be transmitted from the outgoing channel interface 114 and, if so, which outgoing channel that is to be used when transmitting said packet. Having determined an outgoing channel for the data packet, the routing processor 117 will transmit a signal to the outgoing channel manager 116 (arrow 8), containing a channel identifier and the start address received from the incoming channel manager. The channel identifier identifies the outgoing channel to be used when transmitting the associated packet address, and the start address designates where to read the associated packet from in the shared memory 120.
  • the outgoing channel manager 116 Having received the outgoing channel identifier and the start address from the routing processor 117, the outgoing channel manager 116 will access the shared memory (arrow 9) and start reading (arrow 10) data blocks forming the associated packet from the shared memory 119, beginning at the start address received from the routing processor 117 and incrementing the address one step for each data block read from the shared memory 119. At the same time, the outgoing channel manager 116 will continuously receive requests (arrow 11) for data blocks for respective outgoing channels from the outgoing channel interface 114, said request being sent from the outgoing channel interface at the rate as time slots allocated to the respective channel passes on the outgoing bitstream accessed via the outgoing channel interface 114.
  • the outgoing channel manager 116 will forward (arrow 12) , with preserved sequential order, each data block of the associated data packet, as read from the shared memory 119 starting at the designated start address, to the outgoing channel interface 114.
  • the outgoing channel interface 114 will then, in turn, forward (arrow 13) the received data blocks to the respective channels on the outgoing bitstream.
  • the outgoing channel manager 120 Having read the last data block of a packet from the shared memory 119, the outgoing channel manager 120 will return (arrow 14) the associated start address, which was received from the routing processor 117, to the buffer manager 120. This will inform the buffer manager that the processing of the packet stored at the address space associated with said start address is complete and that the buffer manager is now free to allocate said address space to a new data packet received via the incoming channel interface.
  • control unit 121 will determine which channels that are to be received by the incoming channel interface 113, which will typically be those channels use for transmission of data packets that need routing by the routing processor 117. Channels that are not to be directed to the routing processor 117, as determined by the control unit 121, are bypassed at the incoming/outgoing channel interface 113, 114 and are consequently not processed by the routing processor.
  • FIG. 4 Another embodiment of an apparatus according to the invention will now be described with reference to Fig. 4.
  • the incoming channel manager 115 is provided with a cache memory 122.
  • the cache memory 122 contains a list of destination addresses for which no routing is needed by the routing processor 117, as previously determined by the routing processor. A received packet referring to an address among said list of destination addresses shall not be directed to the routing processor 117.
  • the routing processor will continuously update the content of the cache memory 122.
  • the incoming channel manager 115 will compare the destination address of the packet against the destination addresses contained in the cache memory 122. If a match is found, the packet will be discarded at the incoming channel manager and will hence not be directed to the routing processor 117, thereby decreasing the processing load on the routing processor 117. Note, however, that if the channel from which said data packet was received does not terminate at the apparatus 110 but instead continuos to one or more other downstream nodes, e.g. if the channel is a multicast or broadcast channel, the packet may be forwarded to downstream nodes in the same channel as it was received irrespective of whether or not it is discarded at the incoming channel manager. Whether or not this bypassing is done at the incoming/outgoing channel interfaces 113, 114 or at the incoming/outgoing channel managers 115, 116 will typically be determined by the control unit 121.
  • an multichannel multi-access bitstream B which for example may be the bitstream B shown in the previous figures, forms a closed loop link connecting a plurality of access nodes A using circuit switched time division multiplexing according to a DTM protocol.
  • a switch node S connected to the link provides connectivity between said link and another link that also uses circuit switched time division multiplexing according to said DTM protocol.
  • a router R provides access to a packet switched network, such as the Internet.
  • an apparatus 110 according to the invention e.g. the apparatus des- cribed with reference to Fig. 3 or Fig. 4, is connected to the bitstream B.
  • the node apparatus 110 will typically have established an isochronous channel to the router R via the switch S.
  • an end user attached to an access node A on the bitstream B wants to send a packet, it may establish a channel to the appropriate destination on its own decision, for example a channel to another access node on the bitstream B or a channel to the router R via the switch S.
  • it may also use a channel to the node apparatus 110, which will then, having received the packet, see to that the packet is forwarded to the appro- priate destination, for example via a channel to the router R.
  • multicast channels are established from each node connected to the bitstream B to all other nodes connected to the bitstream B. If an end user attached to an access node A on the bitstream B wants to send a packet to any destination, it will then simply multicast the packet using said multicast channel. As the multicasted packet is read at the nodes receiving said multicast channel, if it turns out that the destination address of the packet refers to an end user connected to another access node on said bit- stream, said another node will see to that the packet is forwarded to said end user.
  • the node apparatus 110 will see to that the packet is forwarded to the appropriate destination, for example via a point-to-point channel to the router R.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

L'invention porte sur l'accès à un flux binaire (B) à canaux et accès multiples comportant des canaux isochrones servant au transfert de trafic asynchrone tandis qu'un paquet de données provenant d'un noeud relié audit flux binaire est reçu dans l'un de ses canaux isochrones. On détermine alors si ledit paquet de données doit ou non être transféré sur un deuxième noeud relié audit flux binaire par l'intermédiaire d'un autre desdits canaux isochrones. Si c'est le cas, ledit paquet de données est transféré sur le deuxième noeud par l'intermédiaire du second desdits canaux isochrones.
EP99970232A 1998-10-07 1999-10-07 Procede et appareil d'acheminement dans un reseau a commutation de circuits Withdrawn EP1133852A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9803418 1998-10-07
SE9803418A SE513516C2 (sv) 1998-10-07 1998-10-07 Förfarande och anordning för routing i ett kretskopplat nät
PCT/SE1999/001799 WO2000021256A2 (fr) 1998-10-07 1999-10-07 Procede et appareil d'acheminement dans un reseau a commutation de circuits

Publications (1)

Publication Number Publication Date
EP1133852A2 true EP1133852A2 (fr) 2001-09-19

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP99970232A Withdrawn EP1133852A2 (fr) 1998-10-07 1999-10-07 Procede et appareil d'acheminement dans un reseau a commutation de circuits

Country Status (5)

Country Link
EP (1) EP1133852A2 (fr)
JP (1) JP2002527947A (fr)
AU (1) AU1195700A (fr)
SE (1) SE513516C2 (fr)
WO (1) WO2000021256A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101030827B (zh) * 2006-03-03 2011-04-20 华为技术有限公司 Dtm映射到otn的方法和装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE501373C2 (sv) * 1992-12-17 1995-01-30 Televerket Anordning vid kommunikationsnät
MX9308193A (es) * 1993-01-29 1995-01-31 Ericsson Telefon Ab L M Conmutador atm de acceso controlado.
US5862136A (en) * 1995-07-07 1999-01-19 Northern Telecom Limited Telecommunications apparatus and method
SE508889C2 (sv) * 1996-03-25 1998-11-16 Net Insight Ab Metod och anordning för dataöverföring med parallella bitströmmar

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0021256A2 *

Also Published As

Publication number Publication date
SE9803418L (sv) 2000-04-08
SE9803418D0 (sv) 1998-10-07
AU1195700A (en) 2000-04-26
SE513516C2 (sv) 2000-09-25
JP2002527947A (ja) 2002-08-27
WO2000021256A2 (fr) 2000-04-13
WO2000021256A3 (fr) 2000-07-13

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