EP1093044A1 - Régulateur linéaire à faible chute de tension série - Google Patents
Régulateur linéaire à faible chute de tension série Download PDFInfo
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- EP1093044A1 EP1093044A1 EP00410123A EP00410123A EP1093044A1 EP 1093044 A1 EP1093044 A1 EP 1093044A1 EP 00410123 A EP00410123 A EP 00410123A EP 00410123 A EP00410123 A EP 00410123A EP 1093044 A1 EP1093044 A1 EP 1093044A1
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- transistor
- regulator
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- mos
- resistance
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- 238000000034 method Methods 0.000 claims description 6
- 230000033228 biological regulation Effects 0.000 claims description 4
- 230000000750 progressive effect Effects 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 13
- 230000001276 controlling effect Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 230000001052 transient effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S323/00—Electricity: power supply or regulation systems
- Y10S323/901—Starting circuits
Definitions
- the present invention relates to the field of regulators of linear voltages which are intended to supply a voltage regulated from a reference voltage and a voltage power supply not stabilized.
- the invention relates, more particularly, regulators with one power element connected in series with the load to be supplied and which are designed to introduce a low series voltage drop (LDO), so to be able to operate with a minimum supply voltage.
- LDO low series voltage drop
- FIG. 1 shows a classic example of a regulator linear to which the present invention applies.
- Such regulator is intended to supply a load (Q) 2.
- the regulator basically consists of a power MOS transistor 1 intended to be connected in series with the load 2. This serial association is connected between an application terminal 3 of a more positive potential Vbat and an application terminal 4 more negative potential (for example, mass). Voltage Vbat is, for example, supplied by a battery (not shown).
- Transistor 1 is controlled by a regulation circuit 5, generally based on a differential amplifier.
- a first inverting input of circuit 5 receives a voltage of Vref reference and a second non-inverting input receives the output voltage Vout, taken at the midpoint of the association in series of transistor 1 with load 2. This midpoint constitutes the regulator output terminal 6.
- a capacitor C is generally connected between terminal 6 and ground to filter and stabilize the output voltage Vout.
- linear regulators An example of application of linear regulators is the field of mobile phones.
- the phone battery is used to power one or more regulators linear which must, downstream, provide the power supplies necessary for different polarization and control circuits and digital and analog processing.
- the voltage Vout delivered by the regulator should generally be very precise. Through example, in a telephony application, we want a accuracy of plus or minus 3%.
- the power transistor 1 is generally bulky insofar as the regulator must operate over the entire operating range in current of the circuits which it supplies downstream.
- the surface necessary to produce the power transistor is of the order of 1 mm 2 .
- the importance of the surface area required is also linked to the fact that, in order to respect the constraint of a low voltage drop in series, the resistance of transistor 1 must be, in the on state (RdsON), the lowest possible.
- a consequence of the large size of the transistor of power is that its grid capacity is generally relatively large. For example, for a transistor of the type from that indicated above by way of example, one obtains a grid capacity of the order of 100 picofarads.
- transistor 1 When the circuit is energized or, more precisely, when the regulator is switched on by a specific signal, transistor 1 then supplies a large current to capacitor C which charges. As long as the voltage Vout does not reach not the desired voltage Vref at output, amplifier 5 remains imbalance. When the voltages Vout and Vref become equal, the output terminal of amplifier 5 switches to stop the large current supply in transistor 1. However, due to the high gate capacity of the transistor 1, it is not loaded immediately and one results delay in circuit reaction. Output voltage exceeds then the desired value and there is an overvoltage.
- the output stage (not shown in Figure 1) of the amplifier 5 generally consists of a MOS transistor with channel N (more precisely, of the type of channel opposite to that of power transistor) in series with a current source.
- the current source is itself in parallel with a resistor, called grid, whose role is, precisely, to charge the gate capacitance of power transistor 1 when the output of the amplifier switches.
- the grid resistor also serves to set the gain of the amplifier and conditions the stability of the circuit. Another role of this resistance is to polarize amplifier output stage 5. Therefore, the value of this resistance also conditions consumption of the circuit.
- the present invention aims to propose a new solution which overcomes the problems of overvoltage when starting up classic linear regulators.
- the present invention aims, in particular, to propose a solution that is compatible with low consumption of circuit in steady state.
- the invention also aims to propose a solution which is easily configurable to adjust the response time of the starting circuit.
- a first solution would be to modify the reference amplifier voltage during start-up.
- this solution is not desirable in practice since where the same voltage reference is generally used for several linear regulators. Therefore, by modifying this reference, there is a risk of impairing the functioning of other regulators who would be in an established regime.
- the present invention aims to propose a solution which is compatible with individualized operation of several regulators using the same voltage reference.
- the present invention provides a linear regulator of the type comprising a MOS transistor of a first type of channel, controlled by an amplifier one output stage of which comprises, between two application terminals of a supply voltage, a first resistance and a first MOS control transistor of a second type of channel, the regulator comprising a starting circuit having a resistor switchable in parallel on said first resistor.
- the starting circuit comprises, in series between the source and the gate of the power MOS transistor, said resistor switchable and first and second MOS transistors for controlling the first type of channel.
- the two MOS transistors for controlling the starting circuit are passers-by on switching on the regulator, blocking of the first transistor being progressive by means of a control ramp.
- the second transistor of the starting circuit is blocked at the end of the blocking ramp of the first transistor.
- the duration of the blocking ramp of the first transistor is chosen to be significantly greater than the time required, at the exit of the linear regulator, to reach a desired voltage.
- the starting circuit includes a ramp generator for controlling the first control transistor and a logic circuit of latch to suddenly open the second transistor of control at the end of the control ramp of the first transistor.
- the resistance of the starting circuit is at least ten times lower to the resistance of the output stage of the amplifier ordered.
- the power transistor has a P channel to form a regulator of positive voltage.
- the power transistor is N-channel to constitute a regulator of negative voltage.
- the invention also provides a control method a linear regulator consisting of a power MOS transistor and a control amplifier including an output stage comprises, in series between two supply terminals, a resistor and a control MOS transistor, of opposite channel type with respect to the power transistor, the process of decrease said resistance when starting the regulator.
- the method consists in switching a resistance in parallel with the resistance of the amplifier output stage.
- a feature of the present invention is provide, between the gate of the power transistor (for example, P channel) and the terminal (opposite the load) for applying the supply voltage to which this transistor is connected in direct, switchable resistance.
- this resistor is controlled to be inserted into the circuit only when starting the regulator, and is of lower value to that of the resistance of the amplifier output stage of regulation.
- FIG. 2 shows, very schematically, a regulator 10 according to one embodiment of the present invention.
- the regulator includes an amplifier 5, connected between an application terminal 3 of a positive voltage Vbat and the mass 4, and which is responsible for control a MOS transistor of power 1, connected between the terminal 3 and an output terminal 6 to which a load is connected 2.
- a linear regulator using a P-channel power MOS transistor and delivering a positive tension. Note however that the invention applies also in the case of a negative voltage regulator or a regulator whose power MOS transistor is N channel.
- the conventional amplifier 5 essentially consists a differential stage 11 receiving, on an inverting terminal, the reference voltage Vref setting the value of the voltage desired output and, on a non-inverting terminal, the output voltage Vout of the regulator taken from drain 6 of the transistor 1. If necessary, a resistive divider bridge can be introduced, between terminal 6 and the non-inverting input of the amplifier 5, to obtain a voltage Vout greater than the voltage Vref.
- the differential stage 11 is supplied by a source of current 12 connected to terminal 3. Output 13 of the differential stage is sent to an output stage 14 constituted, in series between terminals 3 and 4, a current source 15 and a transistor MOS (here, at channel N) 16 whose grid is connected to the terminal 13.
- the midpoint 17 of the serial association of the current source 15 and transistor 16 constitutes the terminal of output of amplifier 5, connected to the gate of the transistor 1.
- a resistance Rg, having the role of fixing the gain of amplifier 5, to ensure its stability and to charge the gate of transistor 1, is connected in parallel on the source current 15.
- one connects in parallel on the resistance Rg, a starting circuit 20 constituted, so functional, of a switch 21 in series with a resistor 22.
- the value of resistance 22 is chosen to be low (preferably, in a ratio of 10 to 100) compared to the resistance value Rg. So, for a resistance Rg of the order of a hundred k ⁇ , we will preferably choose a resistance 22 between 1 and 10 k ⁇ .
- control of the starting circuit that is to say the switching of the switch 21 must respect certain constraints. In particular, care will be taken not to reproduce, on the switching of this switch, the delay at switching detrimental to the operation of the regulators classics.
- Another feature of this invention is to associate, in series with the resistor 22 of the starting circuit, two switches (preferably two MOS transistors) controlled in a special way as we will see later.
- FIG. 3 partially shows a mode of realization of a starting circuit according to the invention, comprising a switch 21 in series with a resistor 22.
- the switch 21 is formed here, between terminal 3 and a first resistor 22 terminal whose second terminal is connected to terminal 17, of a first P-channel MOS MR transistor in series with a second MOS ML transistor, P channel.
- the MR transistor is controlled by a STARTUP signal while the ML transistor is controlled by a LOCK signal.
- the STARTUP signal has the form of a ramp whose role is to control the MR transistor in linear to, following ignition, increase its series resistance (RdsON) which is added to the resistor 22, the transistor ML being in a normally closed state when the circuit is switched on.
- the STARTUP signal is normally low so that when starting of the regulator, the MR transistor is closed with a resistor minimum series (RdsON).
- the gradual increase in MR transistor series resistance gradually increases the resistance in parallel on the resistance Rg and, by way of consequence, causes a progressive switching upon opening of the starting circuit of the invention.
- the control ramp at the opening of the MR transistor must be slow enough for the start to finish at the end of the ramp. In other words, we have to make sure that the capacitor C has reached the desired voltage level before the end of the opening ramp of the MR transistor.
- the role of the ML transistor is to lock the opening of the starting circuit to prevent possible disturbance of the battery voltage Vbat does not turn on again the MR transistor under the effect of a parasitic conduction of the generator ramp as we will see later.
- the ML transistor is controlled by an edge, which is not annoying insofar as, when one causes its opening, the starting circuit is already, in practice, opened by the MR transistor.
- FIG. 4 represents a preferred embodiment a starting circuit 20 according to the present invention.
- the Figure 4 does not only represent the serial association of MR and ML transistors constituting switch 21 with the resistor 22, but also the circuit for generating respective STARTUP and LOCK signals for controlling the MR transistors and ML.
- Circuit 20 is based on a ramp generator 31 delivering the STARTUP signal, associated with a logic locking circuit 32 intended to generate the LOCK signal when the signal STARTUP has reached its high state.
- stages 33, 34 delivering signals BP and BN for biasing the MOS transistors respectively P channel and N channel.
- the circuit 20 of the invention is intended to be controlled exclusively by the regulator activation signal linear.
- This signal consists of a logic signal PD and its reverse PDN.
- PD logic signal
- PDN reverse PDN
- the bias circuit 33 is, for example, constituted, in series between terminals 3 and 4, of a MOS transistor MP1, with channel P, and from a current source 35.
- the transistor MP1 is mounted as a diode, its source being connected to terminal 3 and its drain being connected to a first terminal of the current source 35 of which the other terminal is connected to ground 4.
- the transistor drain MP1 is also connected to its gate and to the drain of the transistor MP5, and constitutes the output terminal of circuit 33 delivering the BP signal.
- the current source 35 is, for example, formed of a resistor or an MOS transistor, with N channel, correctly polarized.
- the bias circuit 34 is, for example, constituted, in series between terminal 3 and terminal 4, from a source of current 36 and a MOS transistor MN1, with N channel.
- the transistor MN1 is mounted on a diode, its source being connected to terminal 4 and its drain being connected to a first terminal of the current source 36, the other terminal of which is connected to terminal 3.
- the drain of transistor MN1 is also connected to its gate and to the gate of transistor MN5, and constitutes the output terminal of the circuit 34 delivering the signal BN.
- the current source 36 is, for example, formed by a resistor or a MOS transistor, channel P, correctly polarized.
- the BP and BN signals are, respectively, substantially at potentials Vbat-Vtp (Vtp represents the threshold voltage of a transistor P channel MOS) and Vtn (Vtn represents the threshold voltage of a N-channel MOS transistor).
- the ramp generator 31 is based on the use, in series between terminals 3 and 4, of a MOS transistor MP3, P-channel, associated with a C1 capacitor and, for locking as will be seen later, of a MOS transistor MN3, N channel.
- the source of the MP3 transistor is connected to the terminal 3. Its drain is connected to a first terminal of the capacitor C1 which fixes the time constant of the ramp.
- the other terminal of capacitor C1 is connected to the drain of transistor MN3 whose source is connected to ground.
- the transistor gate MP3 is connected, via an MP4 MOS transistor, to channel P, at terminal 3.
- the transistor MP4 is controlled by the PDN signal and its drain is also connected to the transistor gate MP3, connected to the source of an MP5 MOS transistor, channel P, whose drain receives the signal BP and whose gate receives the PD signal.
- the drain of the MP3 transistor which constitutes the terminal 37 of the ramp generator 31 is further connected, by via an MN4 MOS transistor, N-channel, controlled by the PD signal at terminal 4.
- the role of the transistor MP4 is to force, by passing, blocking of the MP3 transistor when the PDN signal is at low state, i.e. when the regulator is off.
- the role of the transistor MP5 is, conversely, to force turning on the MP3 transistor while conducting when PD signal is low, i.e. when the regulator is on.
- transistor MN4 The role of transistor MN4 is to short-circuit the capacitor C1 and transistor MN3 when signal PD is at high state, i.e. when the regulator is off.
- the STARTUP signal delivered by the output terminal 37 of the ramp generator 31, is sent directly to the grid of the transistor MR and at the input of the locking circuit 32.
- the circuit 32 comprises, in series between the terminals 3 and 4, one MP6 MOS transistor, P channel, and two MN5 MOS transistors and MN6, N channel.
- the source of transistor MP6 is connected to the terminal 3. Its gate receives the STARTUP signal. Its drain is connected to the drain of transistor MN6 whose gate receives the PDN signal.
- the source of transistor MN6 is connected to the drain of transistor MN5 whose source is connected to terminal 4 and whose the gate receives the signal BN.
- the common drain of the transistors MP6 and MN6 is also connected to the input of an inverter 38 whose output is sent to a flip-flop 39 constituted, by example, of two doors 40 and 41, of the NOR type (NOR).
- inverter 38 The exit of inverter 38 is sent to a first door input 40 whose output is sent to a first door entry 41.
- the exit from door 41 constitutes the exit from the scale 39, sent to the second entrance to door 40.
- the second entrance to gate 41 receives the PD signal.
- the exit from the seesaw 39 outputs the LOCK signal.
- the output of flip-flop 39 is also, preferably, sent, via a inverter 42, on the gate of transistor MN3.
- transistor MN3 The role of transistor MN3 is to avoid consumption permanent, outside start-up periods, by isolating the generator ramp when the LOCK signal goes high.
- the role of the transistor MP6 is to open the input branch from circuit 32 when the regulator is off and delete thus the consumption in this circuit 32.
- FIGS. 5A to 5F represent, in the form of chronograms, an example of the appearance of characteristic signals of a regulator according to the invention.
- Figure 5A shows the pace of the PDN signal.
- Figure 5B shows the shape of the signal PD.
- FIG. 5C shows the shape of the STARTUP signal.
- the figure 5D represents the shape of the LOCK signal.
- Figure 5E shows the appearance of the gate signal V17 of the power transistor 1 of the regulator.
- FIG. 5F represents the shape of the voltage Vout at the output of the regulator.
- the PDN and PD signals are respectively low and high.
- Point 37 is grounded by the transistor MN4 is on and the STARTUP signal is therefore low.
- the MR transistor is therefore conducting.
- the MP6 transistor is rendered passing through the low state of node 37 while the transistor MN6 is blocked by the low state of the PDN signal. This results in one high level at the input of the inverter 38 and, consequently, a low state at the output of flip-flop 39, that is to say at the input of the inverter 42.
- the transistor ML is therefore good, the signal LOCK being in the low state.
- the transistor MN3 is also passerby.
- the ramp generator 31 is therefore ready to operate.
- the MP4 transistor On the ramp generator side, the MP4 transistor is blocked by setting the PDN signal to high. In addition, the transistor MP5 is made passing by setting the PD signal low. he As a result, the MP3 transistor turns on, the current in the MP3 transistor being fixed by the current in the transistor MP1, therefore by the signal BP. As the transistor MN4 is located blocked at time t0 by setting the PD signal to a low state, the capacitor C1 is charged by the MP3 transistor. As long as the MP3 transistor is saturated, it provides a constant current of the capacitor C1. Circuit 33 and, more particularly, the sizes of the transistors MP1 and MP5, are chosen from adequately so that the MP3 transistor is saturated. The charging the capacitor C1 under constant current does indeed cause a increasing voltage ramp on the gate of the MR transistor (FIG. 5C), therefore a gradual opening of this transistor by increase in its series resistance (RdsON).
- the output of flip-flop 39 switches. Indeed, the transistor MP6 is blocked.
- the input of the inverter 38 switches to the low state. Its output switches to the high state and the output of the gate 40 then switches to the low state.
- the output of door 41 switches to the high state and, by looping back onto the input of door 40, the state then obtained is stable.
- the high state output of flip-flop 39 (LOCK signal) blocks transistor ML. This blocking of the transistor ML occurs when the transistor MR is itself already completely blocked by the ramp of the STARTUP signal.
- the transistor MN3 is blocked by the passage to the high state of the output of the flip-flop 39, inverted by the inverter 42, so that the ramp generator 31 is disconnected.
- flip-flop 39 The role of flip-flop 39 is actually to memorize the state of the STARTUP signal the first time after switching on of the regulator, we approach the voltage Vbat on the signal STARTUP.
- the potential of node 37 can no longer vary once the LOCK signal is gone high, as long as the PD signal does not quote, i.e. as long as it is not a question of rekindling.
- the transistor MN4 discharges the capacitor C1 of the ramp generator, in order to replace it in a correct operating position for the next ignition.
- FIG. 5E illustrates the shape of the voltage V17 on the gate of the transistor 1. It can be seen that, at the instant t 0 , the voltage V17 drops to make the transistor 1 on. The capacitor C therefore charges under a large current and there results an increase in the voltage Vout.
- the amplifier 5 (FIG. 2) switches and the transistor 1 is blocked. As it is located at the start of the ramp of the STARTUP signal, the resistor 22 is then fully in parallel with the resistor Rg, which considerably accelerates the blocking of the transistor 1 compared to the conventional circuit.
- the time ⁇ required to block transistor 1 is equal to Cg * RgR22 / (Rg + R22), where R22 and Rg are the respective values of resistors 22 and Rg, and where Cg denotes the gate capacitance of transistor 1.
- the value of the resistance 22 is chosen to be at least ten times greater than the resistance Rg of the output stage of the control amplifier, in order to minimize the time ⁇ .
- An advantage of the present invention is that it allows avoid overvoltages when starting a linear regulator.
- Another advantage of the present invention is that it does not require other control signals than those available usually for controlling a regulator. Indeed, as shown in figure 4, the only necessary signals for the operation of the starting circuit are the signals PD and PDN which are used to switch the regulator on / off.
- Another advantage of the present invention is that it does not entail any additional consumption in the regulator in established regime.
- the present invention is capable of various variants and modifications which will appear to the man of art.
- the dimensioning of the various components of the circuit of the invention may be chosen by man of the profession depending on the application and, in particular, function of the desired currents and the desired ramp time for the starting circuit.
- circuit adaptation start of the invention with a regulator using a transistor N-channel power MOS is within the reach of those skilled in the art to from the functional indications given above.
- the adaptation of the starting circuit and the regulator to deliver a negative voltage is within the reach of the skilled person.
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Abstract
Description
Claims (11)
- Régulateur linéaire du type comprenant un transistor MOS de puissance (1) d'un premier type de canal (P), commandé par un amplificateur (5) dont un étage de sortie comprend, entre deux bornes (3, 4) d'application d'une tension d'alimentation (Vbat), une première résistance (Rg) et un premier transistor MOS de commande (16) d'un deuxième type de canal (N), caractérisé en ce qu'il comprend un circuit de démarrage (20) comprenant une résistance commutable (22) en parallèle sur ladite première résistance.
- Régulateur selon la revendication 1, caractérisé en ce que le circuit de démarrage (20) comporte, en série entre la source et la grille du transistor MOS de puissance (1), ladite résistance commutable (22) et des premier (MR) et deuxième (ML) transistors MOS de commande du premier type de canal (P).
- Régulateur selon la revendication 2, caractérisé en ce que les deux transistors MOS de commande du circuit de démarrage (20) sont passants à l'allumage du régulateur, le blocage du premier transistor (MR) étant progressif au moyen d'une rampe de commande (STARTUP) .
- Régulateur selon la revendication 3, caractérisé en ce que le deuxième transistor (ML) du circuit de démarrage (20) est bloqué à la fin de la rampe (STARTUP) de blocage du premier transistor (MR).
- Régulateur selon la revendication 3 ou 4, caractérisé en ce que la durée de la rampe (STARTUP) de blocage du premier transistor (MR) est choisie pour être nettement supérieure au temps nécessaire, à la sortie du régulateur linéaire, pour atteindre une tension souhaitée.
- Régulateur selon une quelconque des revendications 3 à 5, caractérisé en ce que le circuit de démarrage (20) comprend un générateur de rampe (31) pour commander le premier transistor de commande (MR) et un circuit logique de verrouillage (32) pour ouvrir brusquement le deuxième transistor de commande (ML) à la fin de la rampe (STARTUP) de commande du premier transistor.
- Régulateur selon une quelconque des revendications 1 à 6, caractérisé en ce que la résistance (22) du circuit de démarrage (20) est au moins dix fois inférieure à la résistance (Rg) de l'étage de sortie de l'amplificateur de commande (5).
- Régulateur selon l'une quelconque des revendications 1 à 7, caractérisé en ce que le transistor de puissance (1) est à canal P pour constituer un régulateur de tension positive.
- Régulateur selon l'une quelconque des revendications 1 à 7, caractérisé en ce que le transistor de puissance est à canal N pour constituer un régulateur de tension négative.
- Procédé de commande d'un régulateur linéaire constitué d'un transistor MOS de puissance (1) et d'un amplificateur (5) de régulation dont un étage de sortie comporte, en série entre deux bornes (3, 4) d'alimentation, une résistance (Rg) et un transistor MOS de commande (16), de type de canal (N) opposé par rapport au transistor de puissance, caractérisé en ce qu'il consiste à diminuer ladite résistance lors du démarrage du régulateur.
- Procédé selon la revendication 10, caractérisé en ce qu'il consiste à commuter une résistance (22) en parallèle avec la résistance (Rg) de l'étage de sortie de l'amplificateur (5).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9912978A FR2799849B1 (fr) | 1999-10-13 | 1999-10-13 | Regulateur lineaire a faible chute de tension serie |
FR9912978 | 1999-10-13 |
Publications (2)
Publication Number | Publication Date |
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EP1093044A1 true EP1093044A1 (fr) | 2001-04-18 |
EP1093044B1 EP1093044B1 (fr) | 2004-12-29 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP00410123A Expired - Lifetime EP1093044B1 (fr) | 1999-10-13 | 2000-10-12 | Régulateur linéaire à faible chute de tension série |
Country Status (4)
Country | Link |
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US (1) | US6445167B1 (fr) |
EP (1) | EP1093044B1 (fr) |
DE (1) | DE60017049T2 (fr) |
FR (1) | FR2799849B1 (fr) |
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US7010336B2 (en) * | 1997-08-14 | 2006-03-07 | Sensys Medical, Inc. | Measurement site dependent data preprocessing method for robust calibration and prediction |
JP3680784B2 (ja) * | 2001-11-12 | 2005-08-10 | 株式会社デンソー | 電源回路 |
US6724176B1 (en) * | 2002-10-29 | 2004-04-20 | National Semiconductor Corporation | Low power, low noise band-gap circuit using second order curvature correction |
US6979498B2 (en) * | 2003-11-25 | 2005-12-27 | General Electric Company | Strengthened bond coats for thermal barrier coatings |
JP2005176476A (ja) * | 2003-12-10 | 2005-06-30 | Seiko Instruments Inc | スイッチングレギュレータ |
US7078883B2 (en) * | 2004-04-07 | 2006-07-18 | The Board Of Trustees Of The University Of Illinois | Method and apparatus for starting power converters |
US20050255329A1 (en) * | 2004-05-12 | 2005-11-17 | General Electric Company | Superalloy article having corrosion resistant coating thereon |
US7091712B2 (en) * | 2004-05-12 | 2006-08-15 | Freescale Semiconductor, Inc. | Circuit for performing voltage regulation |
FR2872305B1 (fr) * | 2004-06-24 | 2006-09-22 | St Microelectronics Sa | Procede de controle du fonctionnement d'un regulateur a faible chute de tension et circuit integre correspondant |
US7557550B2 (en) * | 2005-06-30 | 2009-07-07 | Silicon Laboratories Inc. | Supply regulator using an output voltage and a stored energy source to generate a reference signal |
US7301316B1 (en) * | 2005-08-12 | 2007-11-27 | Altera Corporation | Stable DC current source with common-source output stage |
US7450354B2 (en) * | 2005-09-08 | 2008-11-11 | Aimtron Technology Corp. | Linear voltage regulator with improved responses to source transients |
US7459891B2 (en) * | 2006-03-15 | 2008-12-02 | Texas Instruments Incorporated | Soft-start circuit and method for low-dropout voltage regulators |
US7882383B2 (en) * | 2006-11-01 | 2011-02-01 | Freescale Semiconductor, Inc. | System on a chip with RTC power supply |
JP4932612B2 (ja) * | 2007-06-15 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | バイアス回路 |
CN101398694A (zh) * | 2007-09-30 | 2009-04-01 | Nxp股份有限公司 | 具有快速过电压响应的无电容低压差稳压器 |
US8716994B2 (en) * | 2012-07-02 | 2014-05-06 | Sandisk Technologies Inc. | Analog circuit configured for fast, accurate startup |
CN103151766B (zh) * | 2013-04-01 | 2017-07-18 | 深圳联辉科电子技术有限公司 | 一种可控制静态电流限流加速保护电路 |
CN103208789B (zh) * | 2013-04-01 | 2017-06-06 | 深圳联辉科电子技术有限公司 | 一种可控制静态电流限流加速保护电路 |
CN103267548B (zh) * | 2013-04-03 | 2016-02-24 | 上海晨思电子科技有限公司 | 一种电压装置 |
EP2977849A1 (fr) * | 2014-07-24 | 2016-01-27 | Dialog Semiconductor GmbH | Régulateur de faible chute de haute tension à basse tension avec référence de tension autonome |
US10853523B2 (en) | 2016-03-22 | 2020-12-01 | New York University In Abu Dhabi Corporation | System, method and computer-accessible medium for satisfiability attack resistant logic locking |
WO2020110959A1 (fr) | 2018-11-26 | 2020-06-04 | 株式会社村田製作所 | Circuit de sortie de courant |
WO2021128199A1 (fr) * | 2019-12-26 | 2021-07-01 | 深圳市汇顶科技股份有限公司 | Régulateur et puce |
TWI787681B (zh) | 2020-11-30 | 2022-12-21 | 立積電子股份有限公司 | 電壓調節器 |
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US4972136A (en) * | 1989-11-07 | 1990-11-20 | The United States Of America As Represented By The Secretary Of The Navy | Linear power regulator with current limiting and thermal shutdown and recycle |
EP0690364A2 (fr) * | 1994-06-27 | 1996-01-03 | International Business Machines Corporation | Génerateur de tension de référence d'écartement de bande avec régulation et circuit de dérranage rapide |
US5666044A (en) * | 1995-09-29 | 1997-09-09 | Cherry Semiconductor Corporation | Start up circuit and current-foldback protection for voltage regulators |
US5698973A (en) * | 1996-07-31 | 1997-12-16 | Data General Corporation | Soft-start switch with voltage regulation and current limiting |
FR2755804A1 (fr) * | 1996-11-08 | 1998-05-15 | Sgs Thomson Microelectronics | Mise en veille d'un regulateur lineaire |
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US5004986A (en) * | 1989-10-02 | 1991-04-02 | Advanced Micro Devices, Inc. | Op-amp with internally generated bias and precision voltage reference using same |
JP3456904B2 (ja) * | 1998-09-16 | 2003-10-14 | 松下電器産業株式会社 | 突入電流抑制手段を備えた電源回路、およびこの電源回路を備えた集積回路 |
-
1999
- 1999-10-13 FR FR9912978A patent/FR2799849B1/fr not_active Expired - Fee Related
-
2000
- 2000-10-12 DE DE60017049T patent/DE60017049T2/de not_active Expired - Fee Related
- 2000-10-12 US US09/689,146 patent/US6445167B1/en not_active Expired - Lifetime
- 2000-10-12 EP EP00410123A patent/EP1093044B1/fr not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4972136A (en) * | 1989-11-07 | 1990-11-20 | The United States Of America As Represented By The Secretary Of The Navy | Linear power regulator with current limiting and thermal shutdown and recycle |
EP0690364A2 (fr) * | 1994-06-27 | 1996-01-03 | International Business Machines Corporation | Génerateur de tension de référence d'écartement de bande avec régulation et circuit de dérranage rapide |
US5666044A (en) * | 1995-09-29 | 1997-09-09 | Cherry Semiconductor Corporation | Start up circuit and current-foldback protection for voltage regulators |
US5698973A (en) * | 1996-07-31 | 1997-12-16 | Data General Corporation | Soft-start switch with voltage regulation and current limiting |
FR2755804A1 (fr) * | 1996-11-08 | 1998-05-15 | Sgs Thomson Microelectronics | Mise en veille d'un regulateur lineaire |
Also Published As
Publication number | Publication date |
---|---|
DE60017049T2 (de) | 2006-01-12 |
US6445167B1 (en) | 2002-09-03 |
FR2799849B1 (fr) | 2002-01-04 |
DE60017049D1 (de) | 2005-02-03 |
EP1093044B1 (fr) | 2004-12-29 |
FR2799849A1 (fr) | 2001-04-20 |
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