EP1093044A1 - Linear regulator with low serial voltage dropout - Google Patents

Linear regulator with low serial voltage dropout Download PDF

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Publication number
EP1093044A1
EP1093044A1 EP00410123A EP00410123A EP1093044A1 EP 1093044 A1 EP1093044 A1 EP 1093044A1 EP 00410123 A EP00410123 A EP 00410123A EP 00410123 A EP00410123 A EP 00410123A EP 1093044 A1 EP1093044 A1 EP 1093044A1
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EP
European Patent Office
Prior art keywords
transistor
regulator
channel
mos
resistance
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Granted
Application number
EP00410123A
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German (de)
French (fr)
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EP1093044B1 (en
Inventor
Nicolas Marty
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STMicroelectronics SA
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STMicroelectronics SA
SGS Thomson Microelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S323/00—Electricity: power supply or regulation systems
    • Y10S323/901—Starting circuits

Definitions

  • the present invention relates to the field of regulators of linear voltages which are intended to supply a voltage regulated from a reference voltage and a voltage power supply not stabilized.
  • the invention relates, more particularly, regulators with one power element connected in series with the load to be supplied and which are designed to introduce a low series voltage drop (LDO), so to be able to operate with a minimum supply voltage.
  • LDO low series voltage drop
  • FIG. 1 shows a classic example of a regulator linear to which the present invention applies.
  • Such regulator is intended to supply a load (Q) 2.
  • the regulator basically consists of a power MOS transistor 1 intended to be connected in series with the load 2. This serial association is connected between an application terminal 3 of a more positive potential Vbat and an application terminal 4 more negative potential (for example, mass). Voltage Vbat is, for example, supplied by a battery (not shown).
  • Transistor 1 is controlled by a regulation circuit 5, generally based on a differential amplifier.
  • a first inverting input of circuit 5 receives a voltage of Vref reference and a second non-inverting input receives the output voltage Vout, taken at the midpoint of the association in series of transistor 1 with load 2. This midpoint constitutes the regulator output terminal 6.
  • a capacitor C is generally connected between terminal 6 and ground to filter and stabilize the output voltage Vout.
  • linear regulators An example of application of linear regulators is the field of mobile phones.
  • the phone battery is used to power one or more regulators linear which must, downstream, provide the power supplies necessary for different polarization and control circuits and digital and analog processing.
  • the voltage Vout delivered by the regulator should generally be very precise. Through example, in a telephony application, we want a accuracy of plus or minus 3%.
  • the power transistor 1 is generally bulky insofar as the regulator must operate over the entire operating range in current of the circuits which it supplies downstream.
  • the surface necessary to produce the power transistor is of the order of 1 mm 2 .
  • the importance of the surface area required is also linked to the fact that, in order to respect the constraint of a low voltage drop in series, the resistance of transistor 1 must be, in the on state (RdsON), the lowest possible.
  • a consequence of the large size of the transistor of power is that its grid capacity is generally relatively large. For example, for a transistor of the type from that indicated above by way of example, one obtains a grid capacity of the order of 100 picofarads.
  • transistor 1 When the circuit is energized or, more precisely, when the regulator is switched on by a specific signal, transistor 1 then supplies a large current to capacitor C which charges. As long as the voltage Vout does not reach not the desired voltage Vref at output, amplifier 5 remains imbalance. When the voltages Vout and Vref become equal, the output terminal of amplifier 5 switches to stop the large current supply in transistor 1. However, due to the high gate capacity of the transistor 1, it is not loaded immediately and one results delay in circuit reaction. Output voltage exceeds then the desired value and there is an overvoltage.
  • the output stage (not shown in Figure 1) of the amplifier 5 generally consists of a MOS transistor with channel N (more precisely, of the type of channel opposite to that of power transistor) in series with a current source.
  • the current source is itself in parallel with a resistor, called grid, whose role is, precisely, to charge the gate capacitance of power transistor 1 when the output of the amplifier switches.
  • the grid resistor also serves to set the gain of the amplifier and conditions the stability of the circuit. Another role of this resistance is to polarize amplifier output stage 5. Therefore, the value of this resistance also conditions consumption of the circuit.
  • the present invention aims to propose a new solution which overcomes the problems of overvoltage when starting up classic linear regulators.
  • the present invention aims, in particular, to propose a solution that is compatible with low consumption of circuit in steady state.
  • the invention also aims to propose a solution which is easily configurable to adjust the response time of the starting circuit.
  • a first solution would be to modify the reference amplifier voltage during start-up.
  • this solution is not desirable in practice since where the same voltage reference is generally used for several linear regulators. Therefore, by modifying this reference, there is a risk of impairing the functioning of other regulators who would be in an established regime.
  • the present invention aims to propose a solution which is compatible with individualized operation of several regulators using the same voltage reference.
  • the present invention provides a linear regulator of the type comprising a MOS transistor of a first type of channel, controlled by an amplifier one output stage of which comprises, between two application terminals of a supply voltage, a first resistance and a first MOS control transistor of a second type of channel, the regulator comprising a starting circuit having a resistor switchable in parallel on said first resistor.
  • the starting circuit comprises, in series between the source and the gate of the power MOS transistor, said resistor switchable and first and second MOS transistors for controlling the first type of channel.
  • the two MOS transistors for controlling the starting circuit are passers-by on switching on the regulator, blocking of the first transistor being progressive by means of a control ramp.
  • the second transistor of the starting circuit is blocked at the end of the blocking ramp of the first transistor.
  • the duration of the blocking ramp of the first transistor is chosen to be significantly greater than the time required, at the exit of the linear regulator, to reach a desired voltage.
  • the starting circuit includes a ramp generator for controlling the first control transistor and a logic circuit of latch to suddenly open the second transistor of control at the end of the control ramp of the first transistor.
  • the resistance of the starting circuit is at least ten times lower to the resistance of the output stage of the amplifier ordered.
  • the power transistor has a P channel to form a regulator of positive voltage.
  • the power transistor is N-channel to constitute a regulator of negative voltage.
  • the invention also provides a control method a linear regulator consisting of a power MOS transistor and a control amplifier including an output stage comprises, in series between two supply terminals, a resistor and a control MOS transistor, of opposite channel type with respect to the power transistor, the process of decrease said resistance when starting the regulator.
  • the method consists in switching a resistance in parallel with the resistance of the amplifier output stage.
  • a feature of the present invention is provide, between the gate of the power transistor (for example, P channel) and the terminal (opposite the load) for applying the supply voltage to which this transistor is connected in direct, switchable resistance.
  • this resistor is controlled to be inserted into the circuit only when starting the regulator, and is of lower value to that of the resistance of the amplifier output stage of regulation.
  • FIG. 2 shows, very schematically, a regulator 10 according to one embodiment of the present invention.
  • the regulator includes an amplifier 5, connected between an application terminal 3 of a positive voltage Vbat and the mass 4, and which is responsible for control a MOS transistor of power 1, connected between the terminal 3 and an output terminal 6 to which a load is connected 2.
  • a linear regulator using a P-channel power MOS transistor and delivering a positive tension. Note however that the invention applies also in the case of a negative voltage regulator or a regulator whose power MOS transistor is N channel.
  • the conventional amplifier 5 essentially consists a differential stage 11 receiving, on an inverting terminal, the reference voltage Vref setting the value of the voltage desired output and, on a non-inverting terminal, the output voltage Vout of the regulator taken from drain 6 of the transistor 1. If necessary, a resistive divider bridge can be introduced, between terminal 6 and the non-inverting input of the amplifier 5, to obtain a voltage Vout greater than the voltage Vref.
  • the differential stage 11 is supplied by a source of current 12 connected to terminal 3. Output 13 of the differential stage is sent to an output stage 14 constituted, in series between terminals 3 and 4, a current source 15 and a transistor MOS (here, at channel N) 16 whose grid is connected to the terminal 13.
  • the midpoint 17 of the serial association of the current source 15 and transistor 16 constitutes the terminal of output of amplifier 5, connected to the gate of the transistor 1.
  • a resistance Rg, having the role of fixing the gain of amplifier 5, to ensure its stability and to charge the gate of transistor 1, is connected in parallel on the source current 15.
  • one connects in parallel on the resistance Rg, a starting circuit 20 constituted, so functional, of a switch 21 in series with a resistor 22.
  • the value of resistance 22 is chosen to be low (preferably, in a ratio of 10 to 100) compared to the resistance value Rg. So, for a resistance Rg of the order of a hundred k ⁇ , we will preferably choose a resistance 22 between 1 and 10 k ⁇ .
  • control of the starting circuit that is to say the switching of the switch 21 must respect certain constraints. In particular, care will be taken not to reproduce, on the switching of this switch, the delay at switching detrimental to the operation of the regulators classics.
  • Another feature of this invention is to associate, in series with the resistor 22 of the starting circuit, two switches (preferably two MOS transistors) controlled in a special way as we will see later.
  • FIG. 3 partially shows a mode of realization of a starting circuit according to the invention, comprising a switch 21 in series with a resistor 22.
  • the switch 21 is formed here, between terminal 3 and a first resistor 22 terminal whose second terminal is connected to terminal 17, of a first P-channel MOS MR transistor in series with a second MOS ML transistor, P channel.
  • the MR transistor is controlled by a STARTUP signal while the ML transistor is controlled by a LOCK signal.
  • the STARTUP signal has the form of a ramp whose role is to control the MR transistor in linear to, following ignition, increase its series resistance (RdsON) which is added to the resistor 22, the transistor ML being in a normally closed state when the circuit is switched on.
  • the STARTUP signal is normally low so that when starting of the regulator, the MR transistor is closed with a resistor minimum series (RdsON).
  • the gradual increase in MR transistor series resistance gradually increases the resistance in parallel on the resistance Rg and, by way of consequence, causes a progressive switching upon opening of the starting circuit of the invention.
  • the control ramp at the opening of the MR transistor must be slow enough for the start to finish at the end of the ramp. In other words, we have to make sure that the capacitor C has reached the desired voltage level before the end of the opening ramp of the MR transistor.
  • the role of the ML transistor is to lock the opening of the starting circuit to prevent possible disturbance of the battery voltage Vbat does not turn on again the MR transistor under the effect of a parasitic conduction of the generator ramp as we will see later.
  • the ML transistor is controlled by an edge, which is not annoying insofar as, when one causes its opening, the starting circuit is already, in practice, opened by the MR transistor.
  • FIG. 4 represents a preferred embodiment a starting circuit 20 according to the present invention.
  • the Figure 4 does not only represent the serial association of MR and ML transistors constituting switch 21 with the resistor 22, but also the circuit for generating respective STARTUP and LOCK signals for controlling the MR transistors and ML.
  • Circuit 20 is based on a ramp generator 31 delivering the STARTUP signal, associated with a logic locking circuit 32 intended to generate the LOCK signal when the signal STARTUP has reached its high state.
  • stages 33, 34 delivering signals BP and BN for biasing the MOS transistors respectively P channel and N channel.
  • the circuit 20 of the invention is intended to be controlled exclusively by the regulator activation signal linear.
  • This signal consists of a logic signal PD and its reverse PDN.
  • PD logic signal
  • PDN reverse PDN
  • the bias circuit 33 is, for example, constituted, in series between terminals 3 and 4, of a MOS transistor MP1, with channel P, and from a current source 35.
  • the transistor MP1 is mounted as a diode, its source being connected to terminal 3 and its drain being connected to a first terminal of the current source 35 of which the other terminal is connected to ground 4.
  • the transistor drain MP1 is also connected to its gate and to the drain of the transistor MP5, and constitutes the output terminal of circuit 33 delivering the BP signal.
  • the current source 35 is, for example, formed of a resistor or an MOS transistor, with N channel, correctly polarized.
  • the bias circuit 34 is, for example, constituted, in series between terminal 3 and terminal 4, from a source of current 36 and a MOS transistor MN1, with N channel.
  • the transistor MN1 is mounted on a diode, its source being connected to terminal 4 and its drain being connected to a first terminal of the current source 36, the other terminal of which is connected to terminal 3.
  • the drain of transistor MN1 is also connected to its gate and to the gate of transistor MN5, and constitutes the output terminal of the circuit 34 delivering the signal BN.
  • the current source 36 is, for example, formed by a resistor or a MOS transistor, channel P, correctly polarized.
  • the BP and BN signals are, respectively, substantially at potentials Vbat-Vtp (Vtp represents the threshold voltage of a transistor P channel MOS) and Vtn (Vtn represents the threshold voltage of a N-channel MOS transistor).
  • the ramp generator 31 is based on the use, in series between terminals 3 and 4, of a MOS transistor MP3, P-channel, associated with a C1 capacitor and, for locking as will be seen later, of a MOS transistor MN3, N channel.
  • the source of the MP3 transistor is connected to the terminal 3. Its drain is connected to a first terminal of the capacitor C1 which fixes the time constant of the ramp.
  • the other terminal of capacitor C1 is connected to the drain of transistor MN3 whose source is connected to ground.
  • the transistor gate MP3 is connected, via an MP4 MOS transistor, to channel P, at terminal 3.
  • the transistor MP4 is controlled by the PDN signal and its drain is also connected to the transistor gate MP3, connected to the source of an MP5 MOS transistor, channel P, whose drain receives the signal BP and whose gate receives the PD signal.
  • the drain of the MP3 transistor which constitutes the terminal 37 of the ramp generator 31 is further connected, by via an MN4 MOS transistor, N-channel, controlled by the PD signal at terminal 4.
  • the role of the transistor MP4 is to force, by passing, blocking of the MP3 transistor when the PDN signal is at low state, i.e. when the regulator is off.
  • the role of the transistor MP5 is, conversely, to force turning on the MP3 transistor while conducting when PD signal is low, i.e. when the regulator is on.
  • transistor MN4 The role of transistor MN4 is to short-circuit the capacitor C1 and transistor MN3 when signal PD is at high state, i.e. when the regulator is off.
  • the STARTUP signal delivered by the output terminal 37 of the ramp generator 31, is sent directly to the grid of the transistor MR and at the input of the locking circuit 32.
  • the circuit 32 comprises, in series between the terminals 3 and 4, one MP6 MOS transistor, P channel, and two MN5 MOS transistors and MN6, N channel.
  • the source of transistor MP6 is connected to the terminal 3. Its gate receives the STARTUP signal. Its drain is connected to the drain of transistor MN6 whose gate receives the PDN signal.
  • the source of transistor MN6 is connected to the drain of transistor MN5 whose source is connected to terminal 4 and whose the gate receives the signal BN.
  • the common drain of the transistors MP6 and MN6 is also connected to the input of an inverter 38 whose output is sent to a flip-flop 39 constituted, by example, of two doors 40 and 41, of the NOR type (NOR).
  • inverter 38 The exit of inverter 38 is sent to a first door input 40 whose output is sent to a first door entry 41.
  • the exit from door 41 constitutes the exit from the scale 39, sent to the second entrance to door 40.
  • the second entrance to gate 41 receives the PD signal.
  • the exit from the seesaw 39 outputs the LOCK signal.
  • the output of flip-flop 39 is also, preferably, sent, via a inverter 42, on the gate of transistor MN3.
  • transistor MN3 The role of transistor MN3 is to avoid consumption permanent, outside start-up periods, by isolating the generator ramp when the LOCK signal goes high.
  • the role of the transistor MP6 is to open the input branch from circuit 32 when the regulator is off and delete thus the consumption in this circuit 32.
  • FIGS. 5A to 5F represent, in the form of chronograms, an example of the appearance of characteristic signals of a regulator according to the invention.
  • Figure 5A shows the pace of the PDN signal.
  • Figure 5B shows the shape of the signal PD.
  • FIG. 5C shows the shape of the STARTUP signal.
  • the figure 5D represents the shape of the LOCK signal.
  • Figure 5E shows the appearance of the gate signal V17 of the power transistor 1 of the regulator.
  • FIG. 5F represents the shape of the voltage Vout at the output of the regulator.
  • the PDN and PD signals are respectively low and high.
  • Point 37 is grounded by the transistor MN4 is on and the STARTUP signal is therefore low.
  • the MR transistor is therefore conducting.
  • the MP6 transistor is rendered passing through the low state of node 37 while the transistor MN6 is blocked by the low state of the PDN signal. This results in one high level at the input of the inverter 38 and, consequently, a low state at the output of flip-flop 39, that is to say at the input of the inverter 42.
  • the transistor ML is therefore good, the signal LOCK being in the low state.
  • the transistor MN3 is also passerby.
  • the ramp generator 31 is therefore ready to operate.
  • the MP4 transistor On the ramp generator side, the MP4 transistor is blocked by setting the PDN signal to high. In addition, the transistor MP5 is made passing by setting the PD signal low. he As a result, the MP3 transistor turns on, the current in the MP3 transistor being fixed by the current in the transistor MP1, therefore by the signal BP. As the transistor MN4 is located blocked at time t0 by setting the PD signal to a low state, the capacitor C1 is charged by the MP3 transistor. As long as the MP3 transistor is saturated, it provides a constant current of the capacitor C1. Circuit 33 and, more particularly, the sizes of the transistors MP1 and MP5, are chosen from adequately so that the MP3 transistor is saturated. The charging the capacitor C1 under constant current does indeed cause a increasing voltage ramp on the gate of the MR transistor (FIG. 5C), therefore a gradual opening of this transistor by increase in its series resistance (RdsON).
  • the output of flip-flop 39 switches. Indeed, the transistor MP6 is blocked.
  • the input of the inverter 38 switches to the low state. Its output switches to the high state and the output of the gate 40 then switches to the low state.
  • the output of door 41 switches to the high state and, by looping back onto the input of door 40, the state then obtained is stable.
  • the high state output of flip-flop 39 (LOCK signal) blocks transistor ML. This blocking of the transistor ML occurs when the transistor MR is itself already completely blocked by the ramp of the STARTUP signal.
  • the transistor MN3 is blocked by the passage to the high state of the output of the flip-flop 39, inverted by the inverter 42, so that the ramp generator 31 is disconnected.
  • flip-flop 39 The role of flip-flop 39 is actually to memorize the state of the STARTUP signal the first time after switching on of the regulator, we approach the voltage Vbat on the signal STARTUP.
  • the potential of node 37 can no longer vary once the LOCK signal is gone high, as long as the PD signal does not quote, i.e. as long as it is not a question of rekindling.
  • the transistor MN4 discharges the capacitor C1 of the ramp generator, in order to replace it in a correct operating position for the next ignition.
  • FIG. 5E illustrates the shape of the voltage V17 on the gate of the transistor 1. It can be seen that, at the instant t 0 , the voltage V17 drops to make the transistor 1 on. The capacitor C therefore charges under a large current and there results an increase in the voltage Vout.
  • the amplifier 5 (FIG. 2) switches and the transistor 1 is blocked. As it is located at the start of the ramp of the STARTUP signal, the resistor 22 is then fully in parallel with the resistor Rg, which considerably accelerates the blocking of the transistor 1 compared to the conventional circuit.
  • the time ⁇ required to block transistor 1 is equal to Cg * RgR22 / (Rg + R22), where R22 and Rg are the respective values of resistors 22 and Rg, and where Cg denotes the gate capacitance of transistor 1.
  • the value of the resistance 22 is chosen to be at least ten times greater than the resistance Rg of the output stage of the control amplifier, in order to minimize the time ⁇ .
  • An advantage of the present invention is that it allows avoid overvoltages when starting a linear regulator.
  • Another advantage of the present invention is that it does not require other control signals than those available usually for controlling a regulator. Indeed, as shown in figure 4, the only necessary signals for the operation of the starting circuit are the signals PD and PDN which are used to switch the regulator on / off.
  • Another advantage of the present invention is that it does not entail any additional consumption in the regulator in established regime.
  • the present invention is capable of various variants and modifications which will appear to the man of art.
  • the dimensioning of the various components of the circuit of the invention may be chosen by man of the profession depending on the application and, in particular, function of the desired currents and the desired ramp time for the starting circuit.
  • circuit adaptation start of the invention with a regulator using a transistor N-channel power MOS is within the reach of those skilled in the art to from the functional indications given above.
  • the adaptation of the starting circuit and the regulator to deliver a negative voltage is within the reach of the skilled person.

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Abstract

The linear regulator is of the type having an MOS power transistor (1) of a first conductivity type (P), a first resistance (Rg) and a first control MOS transistor (16) of a second conductivity type (N). The regulator has a starting circuit (20) in series between the source and the grid of the MOS power transistor are a switched resistance (22) and see Fig.3, the first (MR) and the second (ML) MOS control transistors of the first conductivity type (P).

Description

La présente invention concerne le domaine des régulateurs de tension linéaires qui sont destinés à fournir une tension régulée à partir d'une tension de référence et d'une tension d'alimentation non stabilisée. L'invention concerne, plus particulièrement, les régulateurs dont un élément de puissance est connecté en série avec la charge à alimenter et qui sont conçus pour introduire une faible chute de tension série (LDO), de façon à pouvoir fonctionner avec une tension d'alimentation minimale.The present invention relates to the field of regulators of linear voltages which are intended to supply a voltage regulated from a reference voltage and a voltage power supply not stabilized. The invention relates, more particularly, regulators with one power element connected in series with the load to be supplied and which are designed to introduce a low series voltage drop (LDO), so to be able to operate with a minimum supply voltage.

La figure 1 représente un exemple classique de régulateur linéaire auquel s'applique la présente invention. Un tel régulateur est destiné à alimenter une charge (Q) 2. Le régulateur est essentiellement constitué d'un transistor MOS de puissance 1 destiné à être connecté en série avec la charge 2. Cette association en série est connectée entre une borne 3 d'application d'un potentiel plus positif Vbat et une borne 4 d'application d'un potentiel plus négatif (par exemple, la masse). La tension Vbat est, par exemple, fournie par une batterie (non représentée). Le transistor 1 est commandé par un circuit de régulation 5, généralement basé sur un amplificateur différentiel. Une première entrée inverseuse du circuit 5 reçoit une tension de référence Vref et une deuxième entrée non-inverseuse reçoit la tension de sortie Vout, prélevée au point milieu de l'association en série du transistor 1 avec la charge 2. Ce point milieu constitue la borne 6 de sortie du régulateur. Un condensateur C est généralement connecté entre la borne 6 et la masse pour filtrer et stabiliser la tension de sortie Vout.Figure 1 shows a classic example of a regulator linear to which the present invention applies. Such regulator is intended to supply a load (Q) 2. The regulator basically consists of a power MOS transistor 1 intended to be connected in series with the load 2. This serial association is connected between an application terminal 3 of a more positive potential Vbat and an application terminal 4 more negative potential (for example, mass). Voltage Vbat is, for example, supplied by a battery (not shown). Transistor 1 is controlled by a regulation circuit 5, generally based on a differential amplifier. A first inverting input of circuit 5 receives a voltage of Vref reference and a second non-inverting input receives the output voltage Vout, taken at the midpoint of the association in series of transistor 1 with load 2. This midpoint constitutes the regulator output terminal 6. A capacitor C is generally connected between terminal 6 and ground to filter and stabilize the output voltage Vout.

Le fonctionnement d'un régulateur tel qu'illustré par la figure 1 est parfaitement classique et ne sera pas détaillé. On se bornera à signaler que l'amplificateur 5 est, le plus souvent, alimenté par la tension Vbat et que la tension de référence Vref est généralement fournie par un circuit de référence propre à délivrer une tension stable et précise, par exemple, un circuit du type connu sous la dénomination anglosaxonne "bangap".The operation of a regulator as illustrated by Figure 1 is perfectly classic and will not be detailed. We will limit ourselves to pointing out that the amplifier 5 is, more often than not, powered by the voltage Vbat and that the reference voltage Vref is generally supplied by its own reference circuit to deliver a stable and precise voltage, for example, a circuit of the type known by the Anglo-Saxon name "bangap".

Un exemple d'application des régulateurs linéaires est le domaine des téléphones mobiles. Dans ce genre d'application, la batterie du téléphone sert à alimenter un ou plusieurs régulateurs linéaires qui doivent, en aval, fournir les alimentations nécessaires aux différents circuits de polarisation, de commande et de traitement numérique et analogique. La tension Vout délivrée par le régulateur doit généralement être très précise. Par exemple, dans une application à la téléphonie, on souhaite une précision de plus ou moins 3%.An example of application of linear regulators is the field of mobile phones. In this kind of application, the phone battery is used to power one or more regulators linear which must, downstream, provide the power supplies necessary for different polarization and control circuits and digital and analog processing. The voltage Vout delivered by the regulator should generally be very precise. Through example, in a telephony application, we want a accuracy of plus or minus 3%.

Le transistor de puissance 1 est généralement volumineux dans la mesure où le régulateur doit fonctionner sur toute la plage de fonctionnement en courant des circuits qu'il alimente en aval. Par exemple, pour un régulateur devant être capable de délivrer un courant allant jusqu'à 100 mA, la surface nécessaire pour réaliser le transistor de puissance est de l'ordre de 1 mm2. L'importance de la surface requise est également liée au fait que, pour respecter la contrainte d'une faible chute de tension en série, la résistance du transistor 1 doit être, à l'état passant (RdsON), la plus faible possible.The power transistor 1 is generally bulky insofar as the regulator must operate over the entire operating range in current of the circuits which it supplies downstream. For example, for a regulator which must be capable of delivering a current of up to 100 mA, the surface necessary to produce the power transistor is of the order of 1 mm 2 . The importance of the surface area required is also linked to the fact that, in order to respect the constraint of a low voltage drop in series, the resistance of transistor 1 must be, in the on state (RdsON), the lowest possible.

Une conséquence de l'encombrement important du transistor de puissance est que sa capacité de grille est généralement relativement importante. Par exemple, pour un transistor du type de celui indiqué ci-dessus à titre d'exemple, on obtient une capacité de grille de l'ordre de 100 picofarads. A consequence of the large size of the transistor of power is that its grid capacity is generally relatively large. For example, for a transistor of the type from that indicated above by way of example, one obtains a grid capacity of the order of 100 picofarads.

Un problème qui se pose alors est lié à l'apparition de surtensions au démarrage du régulateur. En effet, lorsque le circuit est éteint, la tension de sortie est nulle et l'amplificateur 5 n'est, par conséquent, pas équilibré.A problem which then arises is linked to the appearance of overvoltages when starting the regulator. Indeed, when the circuit is off, the output voltage is zero and the amplifier 5 is therefore not balanced.

Lorsque le circuit est mis sous tension ou, plus précisément, lorsque le régulateur est allumé par un signal spécifique, le transistor 1 fournit alors un courant important au condensateur C qui se charge. Tant que la tension Vout n'atteint pas la tension Vref souhaitée en sortie, l'amplificateur 5 reste déséquilibré. Lorsque les tensions Vout et Vref deviennent égales, la borne de sortie de l'amplificateur 5 commute pour arrêter la fourniture de courant importante dans le transistor 1. Toutefois, en raison de la forte capacité de grille du transistor 1, celle-ci n'est pas chargée immédiatement et il en découle un retard à la réaction du circuit. La tension de sortie excède alors la valeur souhaitée et on assiste à une surtension.When the circuit is energized or, more precisely, when the regulator is switched on by a specific signal, transistor 1 then supplies a large current to capacitor C which charges. As long as the voltage Vout does not reach not the desired voltage Vref at output, amplifier 5 remains imbalance. When the voltages Vout and Vref become equal, the output terminal of amplifier 5 switches to stop the large current supply in transistor 1. However, due to the high gate capacity of the transistor 1, it is not loaded immediately and one results delay in circuit reaction. Output voltage exceeds then the desired value and there is an overvoltage.

Cette surtension doit rester dans les limites acceptables en fonction des tolérances requises pour la tension de sortie. Plus la capacité de grille est importante, plus il est difficile de respecter cette contrainte.This overvoltage must remain within acceptable limits according to the tolerances required for the output voltage. The higher the grid capacity, the more difficult it is to respect this constraint.

L'étage de sortie (non représenté en figure 1) de l'amplificateur 5 est généralement constitué d'un transistor MOS à canal N (plus précisément, de type de canal opposé à celui du transistor de puissance) en série avec une source de courant. La source de courant est elle-même en parallèle avec une résistance, dite de grille, dont le rôle est, précisément, de charger la capacité de grille du transistor de puissance 1 lorsque la sortie de l'amplificateur commute. La résistance de grille sert également à fixer le gain de l'amplificateur et conditionne la stabilité du circuit. Un autre rôle de cette résistance est de polariser l'étage de sortie de l'amplificateur 5. Par conséquent, la valeur de cette résistance conditionne également la consommation du circuit. Or, bien entendu, dans les applications où on souhaite une miniaturisation élevée, on souhaite également minimiser la consommation pour des questions évidentes d'autonomie. The output stage (not shown in Figure 1) of the amplifier 5 generally consists of a MOS transistor with channel N (more precisely, of the type of channel opposite to that of power transistor) in series with a current source. The current source is itself in parallel with a resistor, called grid, whose role is, precisely, to charge the gate capacitance of power transistor 1 when the output of the amplifier switches. The grid resistor also serves to set the gain of the amplifier and conditions the stability of the circuit. Another role of this resistance is to polarize amplifier output stage 5. Therefore, the value of this resistance also conditions consumption of the circuit. Now, of course, in the applications where you want high miniaturization, we also want to minimize consumption for obvious questions of autonomy.

De ce qui précède, on voit qu'il n'est pas souhaitable d'agir sur cette résistance sous peine de voir les caractéristiques du régulateur se détériorer en régime établi.From the above, we see that it is not desirable act on this resistance under penalty of seeing the characteristics of the regulator deteriorate in steady state.

La présente invention vise à proposer une nouvelle solution qui pallie les problèmes de surtension au démarrage des régulateurs linéaires classiques.The present invention aims to propose a new solution which overcomes the problems of overvoltage when starting up classic linear regulators.

La présente invention vise, en particulier, à proposer une solution qui soit compatible avec une faible consommation du circuit en régime établi.The present invention aims, in particular, to propose a solution that is compatible with low consumption of circuit in steady state.

L'invention vise également à proposer une solution qui soit aisément paramétrable pour régler le temps de réponse du circuit au démarrage.The invention also aims to propose a solution which is easily configurable to adjust the response time of the starting circuit.

Une première solution serait de modifier la référence de tension de l'amplificateur, pendant le démarrage. Toutefois, cette solution n'est pas souhaitable en pratique dans la mesure où une même référence de tension sert généralement à plusieurs régulateurs linéaires. Par conséquent, en modifiant cette référence, on risque de nuire au fonctionnement d'autres régulateurs qui seraient, eux, en régime établi.A first solution would be to modify the reference amplifier voltage during start-up. However, this solution is not desirable in practice since where the same voltage reference is generally used for several linear regulators. Therefore, by modifying this reference, there is a risk of impairing the functioning of other regulators who would be in an established regime.

La présente invention vise à proposer une solution qui soit compatible avec un fonctionnement individualisé de plusieurs régulateurs utilisant une même référence de tension.The present invention aims to propose a solution which is compatible with individualized operation of several regulators using the same voltage reference.

Pour atteindre ces objets, la présente invention prévoit un régulateur linéaire du type comprenant un transistor MOS de puissance d'un premier type de canal, commandé par un amplificateur dont un étage de sortie comprend, entre deux bornes d'application d'une tension d'alimentation, une première résistance et un premier transistor MOS de commande d'un deuxième type de canal, le régulateur comprenant un circuit de démarrage ayant une résistance commutable en parallèle sur ladite première résistance.To achieve these objects, the present invention provides a linear regulator of the type comprising a MOS transistor of a first type of channel, controlled by an amplifier one output stage of which comprises, between two application terminals of a supply voltage, a first resistance and a first MOS control transistor of a second type of channel, the regulator comprising a starting circuit having a resistor switchable in parallel on said first resistor.

Selon un mode de réalisation de la présente invention, le circuit de démarrage comporte, en série entre la source et la grille du transistor MOS de puissance, ladite résistance commutable et des premier et deuxième transistors MOS de commande du premier type de canal.According to an embodiment of the present invention, the starting circuit comprises, in series between the source and the gate of the power MOS transistor, said resistor switchable and first and second MOS transistors for controlling the first type of channel.

Selon un mode de réalisation de la présente invention, les deux transistors MOS de commande du circuit de démarrage sont passants à l'allumage du régulateur, le blocage du premier transistor étant progressif au moyen d'une rampe de commande.According to an embodiment of the present invention, the two MOS transistors for controlling the starting circuit are passers-by on switching on the regulator, blocking of the first transistor being progressive by means of a control ramp.

Selon un mode de réalisation de la présente invention, le deuxième transistor du circuit de démarrage est bloqué à la fin de la rampe de blocage du premier transistor.According to an embodiment of the present invention, the second transistor of the starting circuit is blocked at the end of the blocking ramp of the first transistor.

Selon un mode de réalisation de la présente invention, la durée de la rampe de blocage du premier transistor est choisie pour être nettement supérieure au temps nécessaire, à la sortie du régulateur linéaire, pour atteindre une tension souhaitée.According to an embodiment of the present invention, the duration of the blocking ramp of the first transistor is chosen to be significantly greater than the time required, at the exit of the linear regulator, to reach a desired voltage.

Selon un mode de réalisation de la présente invention, le circuit de démarrage comprend un générateur de rampe pour commander le premier transistor de commande et un circuit logique de verrouillage pour ouvrir brusquement le deuxième transistor de commande à la fin de la rampe de commande du premier transistor.According to an embodiment of the present invention, the starting circuit includes a ramp generator for controlling the first control transistor and a logic circuit of latch to suddenly open the second transistor of control at the end of the control ramp of the first transistor.

Selon un mode de réalisation de la présente invention, la résistance du circuit de démarrage est au moins dix fois inférieure à la résistance de l'étage de sortie de l'amplificateur de commande.According to an embodiment of the present invention, the resistance of the starting circuit is at least ten times lower to the resistance of the output stage of the amplifier ordered.

Selon un mode de réalisation de la présente invention, le transistor de puissance est à canal P pour constituer un régulateur de tension positive.According to an embodiment of the present invention, the power transistor has a P channel to form a regulator of positive voltage.

Selon un mode de réalisation de la présente invention, le transistor de puissance est à canal N pour constituer un régulateur de tension négative.According to an embodiment of the present invention, the power transistor is N-channel to constitute a regulator of negative voltage.

L'invention prévoit également un procédé de commande d'un régulateur linéaire constitué d'un transistor MOS de puissance et d'un amplificateur de régulation dont un étage de sortie comporte, en série entre deux bornes d'alimentation, une résistance et un transistor MOS de commande, de type de canal opposé par rapport au transistor de puissance, le procédé consistant à diminuer ladite résistance lors du démarrage du régulateur. The invention also provides a control method a linear regulator consisting of a power MOS transistor and a control amplifier including an output stage comprises, in series between two supply terminals, a resistor and a control MOS transistor, of opposite channel type with respect to the power transistor, the process of decrease said resistance when starting the regulator.

Selon un mode de réalisation de la présente invention, la procédé consiste à commuter une résistance en parallèle avec la résistance de l'étage de sortie de l'amplificateur.According to an embodiment of the present invention, the method consists in switching a resistance in parallel with the resistance of the amplifier output stage.

Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles :

  • la figure 1, qui a été décrite précédemment, est destinée à exposer l'état de la technique et le problème posé ;
  • la figure 2 représente, de façon très schématique, un mode de réalisation simplifié d'un régulateur linéaire selon la présente invention ;
  • la figure 3 représente un détail d'un circuit de démarrage d'un régulateur selon un mode de réalisation de la présente invention ;
  • la figure 4 est un schéma électrique détaillé d'un circuit de démarrage selon un mode de réalisation de la présente invention ; et
  • les figures 5A à 5F illustrent, sous forme de chronogrammes, le fonctionnement d'un régulateur linéaire selon la présente invention.
    • These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
  • FIG. 1, which has been described previously, is intended to show the state of the art and the problem posed;
  • FIG. 2 very schematically shows a simplified embodiment of a linear regulator according to the present invention;
  • FIG. 3 represents a detail of a starting circuit of a regulator according to an embodiment of the present invention;
  • FIG. 4 is a detailed electrical diagram of a starting circuit according to an embodiment of the present invention; and
  • FIGS. 5A to 5F illustrate, in the form of timing diagrams, the operation of a linear regulator according to the present invention.

    • Les mêmes éléments ont été désignés par les mêmes références aux différentes figures. Pour des raisons de clarté, seuls les éléments du régulateur linéaire qui sont nécessaires à la compréhension de l'invention ont été représentés aux figures et seront décrits par la suite. En particulier, la constitution de l'amplificateur différentiel du régulateur n'a pas été détaillée pour être parfaitement classique, de même que le circuit délivrant la référence de tension d'un régulateur linéaire.The same elements have been designated by the same references to the different figures. For reasons of clarity, only the elements of the linear regulator which are necessary for the understanding of the invention have been shown in the figures and will be described later. In particular, the constitution of the differential amplifier of the regulator has not been detailed to be perfectly classic, as well as the circuit delivering the voltage reference of a linear regulator.

    Une caractéristique de la présente invention est de prévoir, entre la grille du transistor de puissance (par exemple, à canal P) et la borne (opposée à la charge) d'application de la tension d'alimentation à laquelle ce transistor est relié en direct, une résistance commutable. Selon l'invention, cette résistance est commandée pour être insérée dans le circuit uniquement lors du démarrage du régulateur, et est de valeur inférieure à celle de la résistance de l'étage de sortie de l'amplificateur de régulation.A feature of the present invention is provide, between the gate of the power transistor (for example, P channel) and the terminal (opposite the load) for applying the supply voltage to which this transistor is connected in direct, switchable resistance. According to the invention, this resistor is controlled to be inserted into the circuit only when starting the regulator, and is of lower value to that of the resistance of the amplifier output stage of regulation.

    Par l'insertion d'une résistance supplémentaire en parallèle sur la résistance fixant le gain de l'amplificateur de régulation, on diminue la résistance chargeant la grille du transistor de puissance et, par conséquent, on accélère la charge de sa capacité de grille lors du démarrage. La figure 2 représente, de façon très schématique, un régulateur 10 selon un mode de réalisation de la présente invention.By inserting additional resistance in parallel on the resistor fixing the gain of the amplifier regulation, the resistance charging the transistor gate is reduced of power and therefore accelerate the charge of its grid capacity during startup. Figure 2 shows, very schematically, a regulator 10 according to one embodiment of the present invention.

    Comme précédemment, le régulateur comporte un amplificateur de régulation 5, connecté entre une borne 3 d'application d'une tension positive Vbat et la masse 4, et qui est chargé de commander un transistor MOS de puissance 1, connecté entre la borne 3 et une borne 6 de sortie à laquelle est reliée une charge 2. On fera référence par la suite un régulateur linéaire utilisant un transistor MOS de puissance à canal P et délivrant une tension positive. On notera toutefois que l'invention s'applique également au cas d'un régulateur de tension négative ou d'un régulateur dont le transistor MOS de puissance est à canal N.As before, the regulator includes an amplifier 5, connected between an application terminal 3 of a positive voltage Vbat and the mass 4, and which is responsible for control a MOS transistor of power 1, connected between the terminal 3 and an output terminal 6 to which a load is connected 2. We will refer later to a linear regulator using a P-channel power MOS transistor and delivering a positive tension. Note however that the invention applies also in the case of a negative voltage regulator or a regulator whose power MOS transistor is N channel.

    L'amplificateur 5 classique est essentiellement constitué d'un étage différentiel 11 recevant, sur une borne inverseuse, la tension de référence Vref fixant la valeur de la tension de sortie souhaitée et, sur une borne non-inverseuse, la tension de sortie Vout du régulateur prélevée sur le drain 6 du transistor 1. Le cas échéant, un pont diviseur résistif peut être introduit, entre la borne 6 et l'entrée non-inverseuse de l'amplificateur 5, pour obtenir une tension Vout supérieure à la tension Vref. L'étage différentiel 11 est alimenté par une source de courant 12 connectée à la borne 3. La sortie 13 de l'étage différentiel est envoyée sur un étage de sortie 14 constitué, en série entre les bornes 3 et 4, d'une source de courant 15 et d'un transistor MOS (ici, à canal N) 16 dont la grille est connectée à la borne 13. Le point milieu 17 de l'association en série de la source de courant 15 et du transistor 16 constitue la borne de sortie de l'amplificateur 5, connectée à la grille du transistor 1. Une résistance Rg, ayant pour rôles de fixer le gain de l'amplificateur 5, d'en assurer la stabilité et de charger la grille du transistor 1, est connectée en parallèle sur la source de courant 15.The conventional amplifier 5 essentially consists a differential stage 11 receiving, on an inverting terminal, the reference voltage Vref setting the value of the voltage desired output and, on a non-inverting terminal, the output voltage Vout of the regulator taken from drain 6 of the transistor 1. If necessary, a resistive divider bridge can be introduced, between terminal 6 and the non-inverting input of the amplifier 5, to obtain a voltage Vout greater than the voltage Vref. The differential stage 11 is supplied by a source of current 12 connected to terminal 3. Output 13 of the differential stage is sent to an output stage 14 constituted, in series between terminals 3 and 4, a current source 15 and a transistor MOS (here, at channel N) 16 whose grid is connected to the terminal 13. The midpoint 17 of the serial association of the current source 15 and transistor 16 constitutes the terminal of output of amplifier 5, connected to the gate of the transistor 1. A resistance Rg, having the role of fixing the gain of amplifier 5, to ensure its stability and to charge the gate of transistor 1, is connected in parallel on the source current 15.

    Selon l'invention, on connecte en parallèle sur la résistance Rg, un circuit de démarrage 20 constitué, de façon fonctionnelle, d'un commutateur 21 en série avec une résistance 22. La valeur de la résistance 22 est choisie pour être faible (de préférence, dans un rapport de 10 à 100) par rapport à la valeur de la résistance Rg. Ainsi, pour une résistance Rg de l'ordre de la centaine de kΩ, on choisira, de préférence, une résistance 22 comprise entre 1 et 10 kΩ.According to the invention, one connects in parallel on the resistance Rg, a starting circuit 20 constituted, so functional, of a switch 21 in series with a resistor 22. The value of resistance 22 is chosen to be low (preferably, in a ratio of 10 to 100) compared to the resistance value Rg. So, for a resistance Rg of the order of a hundred kΩ, we will preferably choose a resistance 22 between 1 and 10 kΩ.

    Lorsque le commutateur 21 est fermé, l'association en parallèle des résistances Rg et 22 diminue la résistance de grille du transistor 1 par rapport à la simple valeur de la résistance Rg, ce qui diminue le temps de charge de la capacité de grille du transistor 1.When the switch 21 is closed, the association in parallel of the resistances Rg and 22 decreases the resistance of gate of transistor 1 with respect to the simple value of the resistance Rg, which decreases the charging time of the capacity gate of transistor 1.

    On notera que la commande du circuit de démarrage, c'est-à-dire la commutation du commutateur 21, doit respecter certaines contraintes. En particulier, on veillera à ne pas reproduire, sur la commutation de ce commutateur, le retard à la commutation préjudiciable au fonctionnement des régulateurs classiques.It will be noted that the control of the starting circuit, that is to say the switching of the switch 21, must respect certain constraints. In particular, care will be taken not to reproduce, on the switching of this switch, the delay at switching detrimental to the operation of the regulators classics.

    Ainsi, selon un mode de réalisation préféré de la présente invention, on ne se contente pas d'utiliser un transistor MOS pour réaliser le commutateur 21. En effet, en prévoyant un seul transistor MOS en série avec la résistance 22, on risque de reproduire un effet transitoire gênant sur ce transistor, qui se traduit encore par un retard sur l'asservissement du transistor de puissance.Thus, according to a preferred embodiment of the present invention, we don't just use a transistor MOS to make the switch 21. Indeed, by providing a single MOS transistor in series with resistor 22, there is a risk of reproduce an annoying transient effect on this transistor, which again translated by a delay on the enslavement of the transistor power.

    Par conséquent, une autre caractéristique de la présente invention est d'associer, en série avec la résistance 22 du circuit de démarrage, deux commutateurs (de préférence, deux transistors MOS) commandés de façon particulière comme on le verra par la suite.Therefore, another feature of this invention is to associate, in series with the resistor 22 of the starting circuit, two switches (preferably two MOS transistors) controlled in a special way as we will see later.

    La figure 3 représente, de façon partielle, un mode de réalisation d'un circuit de démarrage selon l'invention, comprenant un commutateur 21 en série avec une résistance 22. Le commutateur 21 est ici constitué, entre la borne 3 et une première borne de la résistance 22 dont la deuxième borne est connectée à la borne 17, d'un premier transistor MOS MR, à canal P, en série avec un deuxième transistor MOS ML, à canal P. Le transistor MR est commandé par un signal STARTUP tandis que le transistor ML est commandé par un signal LOCK.FIG. 3 partially shows a mode of realization of a starting circuit according to the invention, comprising a switch 21 in series with a resistor 22. The switch 21 is formed here, between terminal 3 and a first resistor 22 terminal whose second terminal is connected to terminal 17, of a first P-channel MOS MR transistor in series with a second MOS ML transistor, P channel. The MR transistor is controlled by a STARTUP signal while the ML transistor is controlled by a LOCK signal.

    Selon l'invention, le signal STARTUP a la forme d'une rampe dont le rôle est de commander le transistor MR en linéaire pour, suite à l'allumage, augmenter sa résistance série (RdsON) qui s'ajoute à la résistance 22, le transistor ML étant dans un état de repos normalement fermé à l'allumage du circuit. Le signal STARTUP est normalement à l'état bas pour que, au démarrage du régulateur, le transistor MR soit fermé avec une résistance série (RdsON) minimale. L'augmentation progressive de la résistance série du transistor MR augmente progressivement la résistance en parallèle sur la résistance Rg et, par voie de conséquence, entraíne une commutation progressive à l'ouverture du circuit de démarrage de l'invention.According to the invention, the STARTUP signal has the form of a ramp whose role is to control the MR transistor in linear to, following ignition, increase its series resistance (RdsON) which is added to the resistor 22, the transistor ML being in a normally closed state when the circuit is switched on. The STARTUP signal is normally low so that when starting of the regulator, the MR transistor is closed with a resistor minimum series (RdsON). The gradual increase in MR transistor series resistance gradually increases the resistance in parallel on the resistance Rg and, by way of consequence, causes a progressive switching upon opening of the starting circuit of the invention.

    La rampe de commande en ouverture du transistor MR doit être suffisamment lente pour que le démarrage soit fini à la fin de la rampe. En d'autres termes, on doit s'assurer que le condensateur C a atteint le niveau de tension souhaité avant la fin de la rampe d'ouverture du transistor MR.The control ramp at the opening of the MR transistor must be slow enough for the start to finish at the end of the ramp. In other words, we have to make sure that the capacitor C has reached the desired voltage level before the end of the opening ramp of the MR transistor.

    Le rôle du transistor ML est de verrouiller l'ouverture du circuit de démarrage pour éviter qu'une perturbation éventuelle de la tension de batterie Vbat ne rende de nouveau passant le transistor MR sous l'effet d'une conduction parasite du générateur de rampe comme on le verra par la suite.The role of the ML transistor is to lock the opening of the starting circuit to prevent possible disturbance of the battery voltage Vbat does not turn on again the MR transistor under the effect of a parasitic conduction of the generator ramp as we will see later.

    Le transistor ML est commandé par un front, ce qui n'est pas gênant dans la mesure où, quand on provoque son ouverture, le circuit de démarrage est déjà, en pratique, ouvert par le transistor MR.The ML transistor is controlled by an edge, which is not annoying insofar as, when one causes its opening, the starting circuit is already, in practice, opened by the MR transistor.

    La figure 4 représente un mode préféré de réalisation d'un circuit de démarrage 20 selon la présente invention. La figure 4 ne représente pas seulement l'association en série des transistors MR et ML constitutifs du commutateur 21 avec la résistance 22, mais également le circuit de génération des signaux respectifs STARTUP et LOCK de commande des transistors MR et ML.FIG. 4 represents a preferred embodiment a starting circuit 20 according to the present invention. The Figure 4 does not only represent the serial association of MR and ML transistors constituting switch 21 with the resistor 22, but also the circuit for generating respective STARTUP and LOCK signals for controlling the MR transistors and ML.

    Le circuit 20 est basé sur un générateur de rampe 31 délivrant le signal STARTUP, associé à un circuit logique de verrouillage 32 destiné à générer le signal LOCK lorsque le signal STARTUP a atteint son état haut. A la figure 4, on a également représenté, à titre d'exemple, des étages 33, 34 délivrant des signaux BP et BN de polarisation des transistors MOS respectivement à canal P et à canal N.Circuit 20 is based on a ramp generator 31 delivering the STARTUP signal, associated with a logic locking circuit 32 intended to generate the LOCK signal when the signal STARTUP has reached its high state. In Figure 4, we also have shown, by way of example, stages 33, 34 delivering signals BP and BN for biasing the MOS transistors respectively P channel and N channel.

    Le circuit 20 de l'invention est destiné à être commandé exclusivement par le signal d'activation du régulateur linéaire. Ce signal est constitué d'un signal logique PD et de son inverse PDN. A la figure 4, le mécanisme d'inversion du signal d'extinction PD ou d'allumage PDN n'a pas été représenté.The circuit 20 of the invention is intended to be controlled exclusively by the regulator activation signal linear. This signal consists of a logic signal PD and its reverse PDN. In Figure 4, the inversion mechanism of the PD switch-off or PDN switch-on signal has not been shown.

    Le circuit de polarisation 33 est, par exemple, constitué, en série entre les bornes 3 et 4, d'un transistor MOS MP1, à canal P, et d'une source de courant 35. Le transistor MP1 est monté en diode, sa source étant reliée à la borne 3 et son drain étant relié à une première borne de la source de courant 35 dont l'autre borne est connectée à la masse 4. Le drain du transistor MP1 est également connecté à sa grille et au drain du transistor MP5, et constitue la borne de sortie du circuit 33 délivrant le signal BP. La source de courant 35 est, par exemple, formée d'une résistance ou d'un transistor MOS, à canal N, correctement polarisé.The bias circuit 33 is, for example, constituted, in series between terminals 3 and 4, of a MOS transistor MP1, with channel P, and from a current source 35. The transistor MP1 is mounted as a diode, its source being connected to terminal 3 and its drain being connected to a first terminal of the current source 35 of which the other terminal is connected to ground 4. The transistor drain MP1 is also connected to its gate and to the drain of the transistor MP5, and constitutes the output terminal of circuit 33 delivering the BP signal. The current source 35 is, for example, formed of a resistor or an MOS transistor, with N channel, correctly polarized.

    Le circuit de polarisation 34 est, par exemple, constitué, en série entre la borne 3 et la borne 4, d'une source de courant 36 et d'un transistor MOS MN1, à canal N. Le transistor MN1 est monté en diode, sa source étant connectée à la borne 4 et son drain étant relié à une première borne de la source de courant 36 dont l'autre borne est connectée à la borne 3. Le drain du transistor MN1 est également connecté à sa grille et à la grille du transistor MN5, et constitue la borne de sortie du circuit 34 délivrant le signal BN. La source de courant 36 est, par exemple, formée d'une résistance ou d'un transistor MOS, à canal P, correctement polarisé.The bias circuit 34 is, for example, constituted, in series between terminal 3 and terminal 4, from a source of current 36 and a MOS transistor MN1, with N channel. The transistor MN1 is mounted on a diode, its source being connected to terminal 4 and its drain being connected to a first terminal of the current source 36, the other terminal of which is connected to terminal 3. The drain of transistor MN1 is also connected to its gate and to the gate of transistor MN5, and constitutes the output terminal of the circuit 34 delivering the signal BN. The current source 36 is, for example, formed by a resistor or a MOS transistor, channel P, correctly polarized.

    Quand le système est sous tension, c'est-à-dire lorsqu'une tension Vbat est appliquée entre les bornes 3 et 4, les signaux BP et BN sont, respectivement, sensiblement aux potentiels Vbat-Vtp (Vtp représente la tension seuil d'un transistor MOS à canal P) et Vtn (Vtn représente la tension seuil d'un transistor MOS à canal N).When the system is powered on, i.e. when a Vbat voltage is applied between terminals 3 and 4, the BP and BN signals are, respectively, substantially at potentials Vbat-Vtp (Vtp represents the threshold voltage of a transistor P channel MOS) and Vtn (Vtn represents the threshold voltage of a N-channel MOS transistor).

    Selon le mode de réalisation de l'invention illustré par la figure 4, le générateur de rampe 31 est basé sur l'utilisation, en série entre les bornes 3 et 4, d'un transistor MOS MP3, à canal P, associé à un condensateur C1 et, pour le verrouillage comme on le verra par la suite, d'un transistor MOS MN3, à canal N. La source du transistor MP3 est connectée à la borne 3. Son drain est connecté à une première borne du condensateur C1 qui fixe la constante de temps de la rampe. L'autre borne du condensateur C1 est connectée au drain du transistor MN3 dont la source est connectée à la masse. La grille du transistor MP3 est connectée, par l'intermédiaire d'un transistor MOS MP4, à canal P, à la borne 3. Le transistor MP4 est commandé par le signal PDN et son drain est, outre connecté à la grille du transistor MP3, connecté à la source d'un transistor MOS MP5, à canal P, dont le drain reçoit le signal BP et dont la grille reçoit le signal PD. Le drain du transistor MP3 qui constitue la borne 37 de sortie du générateur de rampe 31 est en outre connecté, par l'intermédiaire d'un transistor MOS MN4, à canal N, commandé par le signal PD, à la borne 4. According to the embodiment of the invention illustrated in FIG. 4, the ramp generator 31 is based on the use, in series between terminals 3 and 4, of a MOS transistor MP3, P-channel, associated with a C1 capacitor and, for locking as will be seen later, of a MOS transistor MN3, N channel. The source of the MP3 transistor is connected to the terminal 3. Its drain is connected to a first terminal of the capacitor C1 which fixes the time constant of the ramp. The other terminal of capacitor C1 is connected to the drain of transistor MN3 whose source is connected to ground. The transistor gate MP3 is connected, via an MP4 MOS transistor, to channel P, at terminal 3. The transistor MP4 is controlled by the PDN signal and its drain is also connected to the transistor gate MP3, connected to the source of an MP5 MOS transistor, channel P, whose drain receives the signal BP and whose gate receives the PD signal. The drain of the MP3 transistor which constitutes the terminal 37 of the ramp generator 31 is further connected, by via an MN4 MOS transistor, N-channel, controlled by the PD signal at terminal 4.

    Le rôle du transistor MP4 est de forcer, en étant passant, le blocage du transistor MP3 lorsque le signal PDN est à l'état bas, c'est-à-dire lorsque le régulateur est éteint.The role of the transistor MP4 is to force, by passing, blocking of the MP3 transistor when the PDN signal is at low state, i.e. when the regulator is off.

    Le rôle du transistor MP5 est, à l'inverse, de forcer la mise en conduction du transistor MP3 en étant conducteur lorsque le signal PD est à l'état bas, c'est-à-dire lorsque le régulateur est allumé.The role of the transistor MP5 is, conversely, to force turning on the MP3 transistor while conducting when PD signal is low, i.e. when the regulator is on.

    Le rôle du transistor MN4 est de court-circuiter le condensateur C1 et le transistor MN3 lorsque le signal PD est à l'état haut, c'est-à-dire lorsque le régulateur est éteint.The role of transistor MN4 is to short-circuit the capacitor C1 and transistor MN3 when signal PD is at high state, i.e. when the regulator is off.

    Le signal STARTUP, délivré par la borne 37 de sortie du générateur de rampe 31, est envoyé directement sur la grille du transistor MR et en entrée du circuit de verrouillage 32.The STARTUP signal, delivered by the output terminal 37 of the ramp generator 31, is sent directly to the grid of the transistor MR and at the input of the locking circuit 32.

    Le circuit 32 comprend, en série entre les bornes 3 et 4, un transistor MOS MP6, à canal P, et deux transistors MOS MN5 et MN6, à canal N. La source du transistor MP6 est connectée à la borne 3. Sa grille reçoit le signal STARTUP. Son drain est connecté au drain du transistor MN6 dont la grille reçoit le signal PDN. La source du transistor MN6 est connectée au drain du transistor MN5 dont la source est connectée à la borne 4 et dont la grille reçoit le signal BN. Le drain commun des transistors MP6 et MN6 est en outre connecté à l'entrée d'un inverseur 38 dont la sortie est envoyée sur une bascule 39 constituée, par exemple, de deux portes 40 et 41, de type NON-OU (NOR). La sortie de l'inverseur 38 est envoyée sur une première entrée de la porte 40 dont la sortie est envoyée sur une première entrée de la porte 41. La sortie de la porte 41 constitue la sortie de la bascule 39, envoyée sur la deuxième entrée de la porte 40. La deuxième entrée de la porte 41 reçoit le signal PD. La sortie de la bascule 39 délivre le signal LOCK. La sortie de la bascule 39 est également, de préférence, envoyée, par l'intermédiaire d'un inverseur 42, sur la grille du transistor MN3.The circuit 32 comprises, in series between the terminals 3 and 4, one MP6 MOS transistor, P channel, and two MN5 MOS transistors and MN6, N channel. The source of transistor MP6 is connected to the terminal 3. Its gate receives the STARTUP signal. Its drain is connected to the drain of transistor MN6 whose gate receives the PDN signal. The source of transistor MN6 is connected to the drain of transistor MN5 whose source is connected to terminal 4 and whose the gate receives the signal BN. The common drain of the transistors MP6 and MN6 is also connected to the input of an inverter 38 whose output is sent to a flip-flop 39 constituted, by example, of two doors 40 and 41, of the NOR type (NOR). The exit of inverter 38 is sent to a first door input 40 whose output is sent to a first door entry 41. The exit from door 41 constitutes the exit from the scale 39, sent to the second entrance to door 40. The second entrance to gate 41 receives the PD signal. The exit from the seesaw 39 outputs the LOCK signal. The output of flip-flop 39 is also, preferably, sent, via a inverter 42, on the gate of transistor MN3.

    Le rôle du transistor MN3 est d'éviter une consommation permanente, hors des périodes de démarrage, en isolant le générateur de rampe quand le signal LOCK passe à l'état haut. The role of transistor MN3 is to avoid consumption permanent, outside start-up periods, by isolating the generator ramp when the LOCK signal goes high.

    Le rôle du transistor MP6 est d'ouvrir la branche d'entrée du circuit 32 lorsque le régulateur est éteint et de supprimer ainsi la consommation dans ce circuit 32.The role of the transistor MP6 is to open the input branch from circuit 32 when the regulator is off and delete thus the consumption in this circuit 32.

    On notera que les détails constitutifs des inverseurs et portes logiques du circuit 32 n'ont pas été décrits pour être parfaitement classiques, de même que les sources de courant 35 et 36.It will be noted that the constituent details of the inverters and logic gates of circuit 32 have not been described to be perfectly classic, as well as the 35 and 36.

    Le fonctionnement du circuit représenté en figure 4 est illustré par les figures 5A à 5F qui représentent, sous forme de chronogrammes, un exemple d'allure de signaux caractéristiques d'un régulateur selon l'invention. La figure 5A représente l'allure du signal PDN. La figure 5B représente l'allure du signal PD. La figure 5C représente l'allure du signal STARTUP. La figure 5D représente l'allure du signal LOCK. La figure 5E représente l'allure du signal V17 de grille du transistor de puissance 1 du régulateur. La figure 5F représente l'allure de la tension Vout en sortie du régulateur.The operation of the circuit shown in Figure 4 is illustrated by FIGS. 5A to 5F which represent, in the form of chronograms, an example of the appearance of characteristic signals of a regulator according to the invention. Figure 5A shows the pace of the PDN signal. Figure 5B shows the shape of the signal PD. FIG. 5C shows the shape of the STARTUP signal. The figure 5D represents the shape of the LOCK signal. Figure 5E shows the appearance of the gate signal V17 of the power transistor 1 of the regulator. FIG. 5F represents the shape of the voltage Vout at the output of the regulator.

    Initialement, c'est-à-dire lorsque le régulateur est éteint, les signaux PDN et PD sont respectivement à l'état bas et à l'état haut. Le point 37 est tiré à la masse par le transistor MN4 qui est passant et le signal STARTUP est donc à l'état bas. Le transistor MR est donc passant. De même, le transistor MP6 est rendu passant par l'état bas du noeud 37 alors que le transistor MN6 est bloqué par l'état bas du signal PDN. Il en découle un niveau haut en entrée de l'inverseur 38 et, par conséquent, un état bas en sortie de la bascule 39, c'est-à-dire en entrée de l'inverseur 42. Le transistor ML est donc bien passant, le signal LOCK étant à l'état bas. De plus, le transistor MN3 est également passant. Le générateur de rampe 31 est donc prêt à fonctionner.Initially, i.e. when the regulator is off, the PDN and PD signals are respectively low and high. Point 37 is grounded by the transistor MN4 is on and the STARTUP signal is therefore low. The MR transistor is therefore conducting. Similarly, the MP6 transistor is rendered passing through the low state of node 37 while the transistor MN6 is blocked by the low state of the PDN signal. This results in one high level at the input of the inverter 38 and, consequently, a low state at the output of flip-flop 39, that is to say at the input of the inverter 42. The transistor ML is therefore good, the signal LOCK being in the low state. In addition, the transistor MN3 is also passerby. The ramp generator 31 is therefore ready to operate.

    On suppose qu'à un instant t0, les signaux PD et PDN commutent pour un allumage du régulateur, c'est-à-dire que le signal PD passe à l'état bas tandis que le signal PDN passe à l'état haut. Cela se traduit, sur le circuit de verrouillage 32, par un passage à l'état bas de la première entrée extérieure de la bascule 39 (la deuxième entrée de la porte 41). La sortie de la bascule 39 ne change cependant pas d'état (la sortie de la porte 40 étant toujours à l'état haut) tant que sa deuxième entrée extérieure c'est-à-dire l'entrée de la porte 40 reliée à la sortie de l'inverseur 38 ne change pas d'état. Le transistor MN3 reste donc passant.It is assumed that at an instant t0, the signals PD and PDN switch for regulator ignition, i.e. the PD signal goes low while PDN signal goes to the high state. This translates, on the locking circuit 32, by a transition to the low state of the first external input of flip-flop 39 (the second entrance to door 41). The exit of flip-flop 39 does not change state, however (the output of door 40 is still high) as long as its second external entrance, i.e. the entrance to door 40 connected to the output of the inverter 38 does not change state. The transistor MN3 therefore remains on.

    Côté générateur de rampe, le transistor MP4 est bloqué par la mise à l'état haut du signal PDN. De plus, le transistor MP5 est rendu passant par la mise à l'état bas du signal PD. Il en découle que le transistor MP3 devient passant, le courant dans le transistor MP3 étant fixé par le courant dans le transistor MP1, donc par le signal BP. Comme le transistor MN4 se trouve bloqué à l'instant t0 par la mise à l'état bas du signal PD, le condensateur C1 est chargé par le transistor MP3. Tant que le transistor MP3 est en saturation, il fournit un courant constant de charge du condensateur C1. Le circuit 33 et, plus particulièrement, les tailles des transistors MP1 et MP5, sont choisies de façon adéquate pour que le transistor MP3 soit en saturation. La charge du condensateur C1 sous courant constant provoque bien une rampe de tension croissante sur la grille du transistor MR (figure 5C), donc une ouverture progressive de ce transistor par augmentation de sa résistance série (RdsON).On the ramp generator side, the MP4 transistor is blocked by setting the PDN signal to high. In addition, the transistor MP5 is made passing by setting the PD signal low. he As a result, the MP3 transistor turns on, the current in the MP3 transistor being fixed by the current in the transistor MP1, therefore by the signal BP. As the transistor MN4 is located blocked at time t0 by setting the PD signal to a low state, the capacitor C1 is charged by the MP3 transistor. As long as the MP3 transistor is saturated, it provides a constant current of the capacitor C1. Circuit 33 and, more particularly, the sizes of the transistors MP1 and MP5, are chosen from adequately so that the MP3 transistor is saturated. The charging the capacitor C1 under constant current does indeed cause a increasing voltage ramp on the gate of the MR transistor (FIG. 5C), therefore a gradual opening of this transistor by increase in its series resistance (RdsON).

    Quand le potentiel du noeud 37 atteint la tension Vbat-Vtp (instant t1, figure 5C), la sortie de la bascule 39 commute. En effet, le transistor MP6 se bloque. Comme le transistor MN6 est passant par le signal PDN à l'état haut et que le transistor MN5 est également passant dès que le système est sous-tension, l'entrée de l'inverseur 38 commute à l'état bas. Sa sortie commute à l'état haut et la sortie de la porte 40 commute alors à l'état bas. La sortie de la porte 41 commute à l'état haut et, par le rebouclage sur l'entrée de la porte 40, l'état alors obtenu est stable. La sortie à l'état haut de la bascule 39 (signal LOCK) bloque le transistor ML. Ce blocage du transistor ML intervient lorsque le transistor MR est déjà lui-même entièrement bloqué par la rampe du signal STARTUP. When the potential of node 37 reaches the voltage Vbat-Vtp (instant t 1 , FIG. 5C), the output of flip-flop 39 switches. Indeed, the transistor MP6 is blocked. As the transistor MN6 is passing through the signal PDN in the high state and the transistor MN5 is also passing as soon as the system is under-voltage, the input of the inverter 38 switches to the low state. Its output switches to the high state and the output of the gate 40 then switches to the low state. The output of door 41 switches to the high state and, by looping back onto the input of door 40, the state then obtained is stable. The high state output of flip-flop 39 (LOCK signal) blocks transistor ML. This blocking of the transistor ML occurs when the transistor MR is itself already completely blocked by the ramp of the STARTUP signal.

    A l'instant t1, le transistor MN3 est bloqué par le passage à l'état haut de la sortie de la bascule 39, inversé par l'inverseur 42, de sorte que le générateur de rampe 31 est déconnecté.At time t 1 , the transistor MN3 is blocked by the passage to the high state of the output of the flip-flop 39, inverted by the inverter 42, so that the ramp generator 31 is disconnected.

    Le rôle de la bascule 39 est en fait de mémoriser l'état du signal STARTUP la première fois où, suite à l'allumage du régulateur, on s'approche de la tension Vbat sur le signal STARTUP.The role of flip-flop 39 is actually to memorize the state of the STARTUP signal the first time after switching on of the regulator, we approach the voltage Vbat on the signal STARTUP.

    Si la tension Vbat subit des variations alors que le régulateur est en régime établi, ces variations pourraient entraíner une recharge du condensateur C1 et un nouveau blocage des transistors MR et ML, ce qui perturberait le fonctionnement du régime établi. Grâce aux transistors MN3 et MN4, le potentiel du noeud 37 ne peut plus varier une fois que le signal LOCK est passé à l'état haut, tant que le signal PD ne cite pas, c'est-à-dire tant qu'il ne s'agit pas d'un rallumage provoqué.If the voltage Vbat undergoes variations while the regulator is in steady state, these variations could cause a recharge of the capacitor C1 and a new blocking MR and ML transistors, which would disturb the operation of the established regime. Thanks to the MN3 and MN4 transistors, the potential of node 37 can no longer vary once the LOCK signal is gone high, as long as the PD signal does not quote, i.e. as long as it is not a question of rekindling.

    Lors de l'extinction du régulateur, quand le signal PD repasse à l'état haut, le transistor MN4 décharge le condensateur C1 du générateur de rampe, afin de replacer celui-ci dans une position de fonctionnement correcte pour l'allumage suivant.When the regulator switches off, when the PD signal goes back to the high state, the transistor MN4 discharges the capacitor C1 of the ramp generator, in order to replace it in a correct operating position for the next ignition.

    On notera que, quand le transistor MP6 est bloqué à l'instant t1, il n'y a plus aucune consommation ni dans la bascule 39 ni dans le générateur de rampe 31. La seule consommation provient des transistors MP1 et MN1. Toutefois, ces transistors sont généralement dans un bloc de polarisation du circuit global qui génère les tensions BP et BN qui peuvent servir à d'autres circuits. La consommation des circuits de polarisation 33 et 34 doit donc être considérée comme externe au régulateur.It will be noted that, when the transistor MP6 is blocked at the instant t 1 , there is no longer any consumption either in the flip-flop 39 or in the ramp generator 31. The only consumption comes from the transistors MP1 and MN1. However, these transistors are generally in a polarization block of the overall circuit which generates the voltages BP and BN which can be used for other circuits. The consumption of the bias circuits 33 and 34 must therefore be considered as external to the regulator.

    La figure 5E illustre l'allure de la tension V17 sur la grille du transistor 1. On constate que, à l'instant t0, la tension V17 chute pour rendre le transistor 1 passant. Le condensateur C se charge donc sous un courant important et il en découle une croissance de la tension Vout. Lorsque la tension Vout atteint la tension de référence Vref (instant t2, figure 5F), l'amplificateur 5 (figure 2) bascule et le transistor 1 se bloque. Comme on se situe au début de la rampe du signal STARTUP, la résistance 22 est alors pleinement en parallèle avec la résistance Rg, ce qui accélère considérablement le blocage du transistor 1 par rapport au circuit classique. Le temps τ nécessaire au blocage du transistor 1 est égal à Cg*RgR22/(Rg+R22), où R22 et Rg sont les valeurs respectives des résistances 22 et Rg, et où Cg désigne la capacité de grille du transistor 1. De préférence, la valeur de la résistance 22 est choisie pour être au moins dix fois supérieure à la résistance Rg de l'étage de sortie de l'amplificateur de commande, afin de minimiser le temps τ.FIG. 5E illustrates the shape of the voltage V17 on the gate of the transistor 1. It can be seen that, at the instant t 0 , the voltage V17 drops to make the transistor 1 on. The capacitor C therefore charges under a large current and there results an increase in the voltage Vout. When the voltage Vout reaches the reference voltage Vref (instant t 2 , FIG. 5F), the amplifier 5 (FIG. 2) switches and the transistor 1 is blocked. As it is located at the start of the ramp of the STARTUP signal, the resistor 22 is then fully in parallel with the resistor Rg, which considerably accelerates the blocking of the transistor 1 compared to the conventional circuit. The time τ required to block transistor 1 is equal to Cg * RgR22 / (Rg + R22), where R22 and Rg are the respective values of resistors 22 and Rg, and where Cg denotes the gate capacitance of transistor 1. Preferably , the value of the resistance 22 is chosen to be at least ten times greater than the resistance Rg of the output stage of the control amplifier, in order to minimize the time τ.

    Un avantage de la présente invention est qu'elle permet d'éviter les surtensions au démarrage d'un régulateur linéaire.An advantage of the present invention is that it allows avoid overvoltages when starting a linear regulator.

    Un autre avantage de la présente invention est qu'elle ne nécessite pas d'autres signaux de commande que ceux disponibles habituellement pour la commande d'un régulateur. En effet, comme il ressort de la figure 4, les seuls signaux nécessaires pour le fonctionnement du circuit de démarrage sont les signaux PD et PDN qui servent à allumer/éteindre le régulateur.Another advantage of the present invention is that it does not require other control signals than those available usually for controlling a regulator. Indeed, as shown in figure 4, the only necessary signals for the operation of the starting circuit are the signals PD and PDN which are used to switch the regulator on / off.

    Un autre avantage de la présente invention est qu'elle n'entraíne aucune consommation supplémentaire dans le régulateur en régime établi.Another advantage of the present invention is that it does not entail any additional consumption in the regulator in established regime.

    Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaítront à l'homme de l'art. En particulier, le dimensionnement des différents composants du circuit de l'invention pourront être choisis par l'homme du métier en fonction de l'application et, en particulier, en fonction des courants souhaités et du temps de rampe souhaité pour le circuit de démarrage. En outre, bien que l'invention ait été décrite ci-dessus en relation avec un régulateur utilisant un transistor MOS de puissance à canal P, l'adaptation du circuit de démarrage de l'invention à un régulateur utilisant un transistor MOS de puissance à canal N est à la portée de l'homme du métier à partir des indications fonctionnelles données ci-dessus. De même, l'adaptation du circuit de démarrage et du régulateur pour délivrer une tension négative est à la portée de l'homme du métier.Of course, the present invention is capable of various variants and modifications which will appear to the man of art. In particular, the dimensioning of the various components of the circuit of the invention may be chosen by man of the profession depending on the application and, in particular, function of the desired currents and the desired ramp time for the starting circuit. Furthermore, although the invention was described above in relation to a regulator using a P-channel power MOS transistor, circuit adaptation start of the invention with a regulator using a transistor N-channel power MOS is within the reach of those skilled in the art to from the functional indications given above. Likewise, the adaptation of the starting circuit and the regulator to deliver a negative voltage is within the reach of the skilled person.

    Claims (11)

    Régulateur linéaire du type comprenant un transistor MOS de puissance (1) d'un premier type de canal (P), commandé par un amplificateur (5) dont un étage de sortie comprend, entre deux bornes (3, 4) d'application d'une tension d'alimentation (Vbat), une première résistance (Rg) et un premier transistor MOS de commande (16) d'un deuxième type de canal (N), caractérisé en ce qu'il comprend un circuit de démarrage (20) comprenant une résistance commutable (22) en parallèle sur ladite première résistance.Linear regulator of the type comprising a transistor Power MOS (1) of a first type of channel (P), controlled by an amplifier (5), one output stage of which comprises, between two terminals (3, 4) for applying a supply voltage (Vbat), a first resistor (Rg) and a first MOS control transistor (16) of a second type of channel (N), characterized in that that it comprises a starting circuit (20) comprising a resistor switchable (22) in parallel on said first resistor. Régulateur selon la revendication 1, caractérisé en ce que le circuit de démarrage (20) comporte, en série entre la source et la grille du transistor MOS de puissance (1), ladite résistance commutable (22) et des premier (MR) et deuxième (ML) transistors MOS de commande du premier type de canal (P).Regulator according to claim 1, characterized in what the starting circuit (20) comprises, in series between the source and the gate of the power MOS transistor (1), said switchable resistance (22) and first (MR) and second (ML) MOS control transistors of the first type of channel (P). Régulateur selon la revendication 2, caractérisé en ce que les deux transistors MOS de commande du circuit de démarrage (20) sont passants à l'allumage du régulateur, le blocage du premier transistor (MR) étant progressif au moyen d'une rampe de commande (STARTUP) .Regulator according to claim 2, characterized in what the two MOS transistors control the starting circuit (20) are on when the regulator is switched on, the blocking of the first transistor (MR) being progressive by means of a ramp command (STARTUP). Régulateur selon la revendication 3, caractérisé en ce que le deuxième transistor (ML) du circuit de démarrage (20) est bloqué à la fin de la rampe (STARTUP) de blocage du premier transistor (MR).Regulator according to claim 3, characterized in what the second transistor (ML) of the starting circuit (20) is blocked at the end of the first blocking ramp (STARTUP) transistor (MR). Régulateur selon la revendication 3 ou 4, caractérisé en ce que la durée de la rampe (STARTUP) de blocage du premier transistor (MR) est choisie pour être nettement supérieure au temps nécessaire, à la sortie du régulateur linéaire, pour atteindre une tension souhaitée.Regulator according to claim 3 or 4, characterized in that the duration of the ramp (STARTUP) blocking the first transistor (MR) is chosen to be clearly greater than the time required, at the output of the regulator linear, to achieve a desired tension. Régulateur selon une quelconque des revendications 3 à 5, caractérisé en ce que le circuit de démarrage (20) comprend un générateur de rampe (31) pour commander le premier transistor de commande (MR) et un circuit logique de verrouillage (32) pour ouvrir brusquement le deuxième transistor de commande (ML) à la fin de la rampe (STARTUP) de commande du premier transistor. Regulator according to any one of claims 3 to 5, characterized in that the starting circuit (20) comprises a ramp generator (31) for controlling the first transistor control (MR) and a locking logic circuit (32) for suddenly open the second control transistor (ML) to the end of the first transistor control ramp (STARTUP). Régulateur selon une quelconque des revendications 1 à 6, caractérisé en ce que la résistance (22) du circuit de démarrage (20) est au moins dix fois inférieure à la résistance (Rg) de l'étage de sortie de l'amplificateur de commande (5).Regulator according to any one of claims 1 to 6, characterized in that the resistance (22) of the start (20) is at least ten times lower than the resistance (Rg) of the output stage of the control amplifier (5). Régulateur selon l'une quelconque des revendications 1 à 7, caractérisé en ce que le transistor de puissance (1) est à canal P pour constituer un régulateur de tension positive.Regulator according to any one of the claims 1 to 7, characterized in that the power transistor (1) is at P channel to constitute a positive voltage regulator. Régulateur selon l'une quelconque des revendications 1 à 7, caractérisé en ce que le transistor de puissance est à canal N pour constituer un régulateur de tension négative.Regulator according to any one of the claims 1 to 7, characterized in that the power transistor is at N channel to constitute a negative voltage regulator. Procédé de commande d'un régulateur linéaire constitué d'un transistor MOS de puissance (1) et d'un amplificateur (5) de régulation dont un étage de sortie comporte, en série entre deux bornes (3, 4) d'alimentation, une résistance (Rg) et un transistor MOS de commande (16), de type de canal (N) opposé par rapport au transistor de puissance, caractérisé en ce qu'il consiste à diminuer ladite résistance lors du démarrage du régulateur.Method for controlling a linear regulator consisting a power MOS transistor (1) and an amplifier (5) of regulation of which an output stage comprises, in series between two supply terminals (3, 4), a resistor (Rg) and a control MOS transistor (16), of opposite channel type (N) with respect to the power transistor, characterized in that it consists in reducing said resistance when starting the regulator. Procédé selon la revendication 10, caractérisé en ce qu'il consiste à commuter une résistance (22) en parallèle avec la résistance (Rg) de l'étage de sortie de l'amplificateur (5).Method according to claim 10, characterized in that that it consists in switching a resistor (22) in parallel with the resistance (Rg) of the output stage of the amplifier (5).
    EP00410123A 1999-10-13 2000-10-12 Linear regulator with low serial voltage dropout Expired - Lifetime EP1093044B1 (en)

    Applications Claiming Priority (2)

    Application Number Priority Date Filing Date Title
    FR9912978 1999-10-13
    FR9912978A FR2799849B1 (en) 1999-10-13 1999-10-13 LINEAR REGULATOR WITH LOW DROP VOLTAGE SERIES

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    EP1093044A1 true EP1093044A1 (en) 2001-04-18
    EP1093044B1 EP1093044B1 (en) 2004-12-29

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    US (1) US6445167B1 (en)
    EP (1) EP1093044B1 (en)
    DE (1) DE60017049T2 (en)
    FR (1) FR2799849B1 (en)

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    FR2799849B1 (en) 2002-01-04
    DE60017049T2 (en) 2006-01-12
    FR2799849A1 (en) 2001-04-20
    US6445167B1 (en) 2002-09-03
    EP1093044B1 (en) 2004-12-29
    DE60017049D1 (en) 2005-02-03

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