EP1050182A1 - Systeme et procede de transmission - Google Patents

Systeme et procede de transmission

Info

Publication number
EP1050182A1
EP1050182A1 EP98966214A EP98966214A EP1050182A1 EP 1050182 A1 EP1050182 A1 EP 1050182A1 EP 98966214 A EP98966214 A EP 98966214A EP 98966214 A EP98966214 A EP 98966214A EP 1050182 A1 EP1050182 A1 EP 1050182A1
Authority
EP
European Patent Office
Prior art keywords
data
hbo
transmitted
cell
bit sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98966214A
Other languages
German (de)
English (en)
Inventor
Thomas Zellerhoff
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1050182A1 publication Critical patent/EP1050182A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment

Definitions

  • the present invention relates to a method for Studentstra ⁇ gene of data in an ATM transmission system, as well as an ATM transmission system, in particular an ATM broadband transmission system.
  • STM transmission Synchronous Transfer Mode
  • the data of different data channels are transmitted serially within different time slots, the individual time slots being combined into frames.
  • a specific time slot within a frame is assigned to each data channel.
  • a frame sync word is transmitted so that each time slot of a frame assigned to a specific data channel is at a fixed time interval from the frame sync word.
  • Each time slot can have a relatively small number of bits, e.g. 8 bits, contain and appears at constant intervals.
  • FIG. 3a shows an illustration to explain the ATM principle.
  • a plurality of cells Z are transmitted in succession (in the direction of the arrow) from a transmitter to a receiver.
  • each cell comprises a header with address or control information and an information field with the actual useful information.
  • the information field comprises 48 octets, while the header has 5 octets, so that each cell is formed by 53 octets or bytes.
  • Additional (header) octets can be added to this cell format, which can be used for the routing of the cell when the cell is transmitted from a sending subscriber to a receiving subscriber.
  • the data streams between the individual transmitting and receiving modules are transmitted optically via optical fibers.
  • These ATM broadband communication networks allow a very high data throughput, which, however, cannot be processed by the coupling elements used, which are generally m of CMOS technology, due to technological restrictions. Therefore, the data to be transmitted are sent to transmit modules in parallel over a plurality of data lines and are serially multiplexed by the transmit modules via the optical waveguide to receive modules which transmit the serial ATM data stream again 3 ausgangssei t ig for further processing entsprecnende pa ⁇ rallele data channels divide.
  • a transmitter as DIE nendes absorbed optical ATM link receives digital data meh ⁇ of exemplary data channels K 0 -K n. Furthermore, a clock signal T is fed to the transmitter S. Depending on the clock signal T, the transmitter S thus reads n + 1 bits in parallel and converts these bits into a serial ge-multiplexed ATM data stream D with a correspondingly higher data transmission rate, this data stream D being optically transmitted to a receiver E. This receiver E parallelizes the received serial data stream D and outputs it again in parallel via output-side data channel lines K 0 -K n together with a clock signal T.
  • the block coding in the transmitter S adds a redundancy to the actual serial data stream D, as a result of which the serial data rate of the data stream D increases.
  • a relatively high amount of circuitry is required in the receiver E in order to be able to evaluate the synchronization information added to the serial data stream D. All this has the consequence that for the transmission of cter data of the input data channels K 0 -K- ,- 4 for example, no cheap standard lasers can be used.
  • the present invention is therefore based on the object of creating a transmission method for an ATM transmission system and a corresponding ATM transmission system, it being possible for the serial-transmitted data stream to be demultiplexed on the receiver side with relatively simple circuitry complexity. In particular, it should be possible to correctly demultiplex the serial data stream without adding additional synchronization information and thus without adding redundancy.
  • the digital data of the parallel data channels present at the transmitter end are converted bit by bit into a serial ATM data stream, ie multiplexed, the serial data of the ATM data stream being described in the form of the entry ATM cells are transmitted.
  • a characteristic bit sequence is transmitted within each cell, with the aid of which the beginning of the corresponding ATM cell in the serial data stream can be detected on the receiver side.
  • This characteristic bit sequence is preferably a synchronous octet which is transmitted anyway with each ATM cell, so that by monitoring the received data stream upon the occurrence of this synchronous octet, the beginning of the corresponding ATM cell is recognized and the information of the server is correctly correct - Parallelized 5 len data stream and adopted ⁇ e from ⁇ gangssei t owned data channels can be divided.
  • the digital data of the emgangs nurse parallel zugechtten data channels are interconnected in bitwise data units ⁇ bordered, ⁇ ie each to be transmitted ATM cell form.
  • Each ATM cell transmitted using the serial data stream thus contains several data units, each of which comprises an identical number of bits from each parallel data channel.
  • two or more bits are transmitted from each data channel with each data unit.
  • the parallel data channels on the input side are scanned bit by bit, so that each data unit has only one bit of each data channel.
  • the corresponding bit of a data channel is always located in the same place within each data unit, so that the individual bits can be easily divided on the receiving side after the start of a data unit has been established between the parallel data channels on the output side.
  • each nibble forming a previously described data unit of the ATM cell to be transmitted.
  • Each octet of an ATM cell therefore comprises two of these nibbles.
  • the data of each ATM cell are thus serially transmitted from the transmitter to the receiver in half-bytes.
  • the evaluation according to the invention of the characteristic bit sequence of the cell which is transmitted anyway with the cell and is usually formed by the first byte of each ATM cell, makes it possible for the receiver-side demultiplexing of the serial data stream to have no additional signals or Synchronization information is required for channel mapping. An increase in the data rate of the optically transmitted serial data stream with the associated disadvantages described above can thus be avoided.
  • the invention thus enables data transmission according to the 6
  • the invention particularly relates to the transmission of data within an ATM processing system.
  • FIG. 1 shows a schematic illustration of a preferred exemplary embodiment of the ATM broadband transmission system according to the invention
  • FIG. 2 shows the internal structure of an ATM cell that is transmitted from a transmitter to a receiver via the serial data flow shown in FIG. 1,
  • 3a shows a representation of the basic data flow according to the ATM transmission principle
  • 3b is a schematic representation of a known ATM broadband transmission system.
  • FIG. 1 schematically shows the structure of a preferred exemplary embodiment of the ATM transmission system according to the invention. Viewed from the outside, this structure essentially corresponds to the already known structure shown in FIG. 3.
  • a transmission device S receives a plurality of data channels K c -K 3 and a clock signal T and converts the digital data of these data channels which are present in parallel to it into a serial data stream D which consists of a plurality of ATM cells which are transmitted in succession.
  • This serial data stream D is from 7 received a receiving device E and evaluated and the output side to the output side data channels Kr-K sen zugewie ⁇ .
  • specifics d ty of Ausfuh ⁇ approximately example shown in Fig.
  • the Sendeemrich- tung S four data channels K, -K are supplied to the digital data of four-bit-wise detected in parallel and in serial Since ⁇ data stream D implemented, ie be multiplexed.
  • the Sendeein ⁇ direction S transmits the serial data stream over an optically L chtwellenleiteran für anssen to the receiving device E.
  • the individual data channels K 0 -K 3 may, for example, a
  • the four-bit parallel reading in of the digital data of the four data channels K 0 -K ⁇ is, as will be explained in more detail below, particularly advantageous because the four bits of the individual data channels K 0 -K 3 read in parallel in the transmitting device S can be combined particularly easily into data units in the form of nibbles, which in the form of
  • Each ATM cell of the serial data stream D to be transmitted accordingly comprises, according to the exemplary embodiment shown in FIG. 1, a multiplicity of serially transmitted nibbles, each of which comprises a bit read in parallel from each data channel K 0 -K ⁇ .
  • the ATM cell shown in FIG. 2 comprises the standard ATM cell structure with 53 octets or 8th
  • additional address or control octets are added to this standard ATM cell structure with 5 header octets and 48 information field octets by the transmitting device shown in FIG. 1, which internal routing information for the transmission of the ATM cells between include the individual coupling modules.
  • this internal address or control information includes an “internal” header with an additional 10 octets and an “internal” trailer that terminates the ATM cell with an octet, so that the total of the transmitter S to the receiver E transmitted ATM cells according to FIG. 2 comprise a total of 64 octets or bytes.
  • the receiver monitors the serial data stream supplied to it for the occurrence of this characteristic bit sequence hm and, after recognizing this characteristic bit sequence, can determine and determine the beginning of the corresponding ATM cell within the serially transmitted data stream.
  • this is possible in particular because the bits of the digital data channels K 0 -K 3 (cf. FIG. 1) read in parallel are combined on the sensor side, with each data unit having an identical number of bits from each data channel 9 has.
  • Bits j edes data channel are within a ⁇ individual data units always the same position, so that upon detection of the characteristic bit sequence in the receiver of the beginning of the first data unit of the corresponding ATM cell, the position of the individual units of data in the serial optical ⁇ that specific data stream determined and the individual bits of the individual data units can be correctly distributed on the output side to the individual data channels K 0 -K ⁇ .
  • each serial data unit of each ATM cell of each data channel K 0 - K it would be possible for the individual serial data units of each ATM cell of each data channel K 0 - K to have two or more bits, bits 0 and 1 being the data channel K 0 , bits 2 and 3 being the data channel K, for example , etc. are assigned.
  • the data units to be transmitted were each formed by a full byte, with each ATM cell being transmitted byte by byte from the transmitter to the receiver.
  • each data channel K 0 -K 3 it is advantageous to read and multiplex only one bit of each data channel K 0 -K 3 at the transmitter depending on the supplied clock signal T (see FIG. 1), so that those from the transmitter shown in FIG. 1 S data units of the serial data stream transmitted to the receiver E are each formed by nibbles with four bits, wherein according to FIG. 2 128 nibbles serially transmitted form an ATM cell of the serial data stream D.
  • each octet of the ATM cell shown in FIG. 2 is preferably transmitted from the transmitter S to the receiver E in nibbles by transmitting a nibble HBO and a subsequent second nibble HB1.
  • the one shown in Fig. 2 is preferably transmitted from the transmitter S to the receiver E in nibbles by transmitting a nibble HBO and a subsequent second nibble HB1.
  • the receiver E In order for the bits contained in the individual nibbles to be correctly detected on the receiver side and to be distributed over the output-side data channels K -Kt, the receiver E must be included in the serial data stream D supplied to it in succession 10
  • each ATM cell to determine UD endured nibbles the start of an individual ⁇ A TM cells and the other within each the start of each half-bytes.
  • a characteristic bit sequence is transmitted within each ATM cell of the serial data stream D and is monitored on the receiver side for its occurrence hm.
  • This characteristic bit sequence is always transmitted in the same place, ie in the same octet and divided into the same nibbles, in each of the transmitted ATM cells.
  • the receiver If the receiver thus recognizes the occurrence of this characteristic bit sequence in the serial data stream D supplied to it, it can, since it knows the relationship between the position of the characteristic bit sequence within the ATM cell and the beginning of the ATM cell, ie the location the ATM cell within the serial data stream D, is known to determine the beginning of the corresponding ATM cell and thus the first nibble of this ATM cell, the serial data stream and the individual bits of this first nibble and the subsequent nibbles of the corresponding ATM cell correctly divide successively into the individual data channels K ⁇ -K ⁇ on the output side, so that they are correspondingly output in parallel.
  • the first octet of each ATM cell can advantageously be used as the characteristic bit sequence described above. 11 applies who en d.
  • This octet 0 shown in Fig. 2 at V erwen d ung the cell format shown in Fig. 2 in the un in Fig. 1 d 3 d arge presented ATM broadband Uoertragungssystemen standard for evaluation and determination of the corresponding ATM cell m the individual Coupling structures (transmitter, receiver) required and referred to as a synchronous octet.
  • this synchronous octet comprises bits numbered 0 to 6, which have the same value for each ATM cell to be transmitted and are therefore fixed.
  • the most significant bit 7 of this synchronous octet which is denoted by T in FIG. 2, is an "toggle bit" which is set alternately by the transmitter from ATM cell to ATM cell.
  • T in FIG. 2 ATM cell format shown anyway uses the synchronous octet as a characteristic bit sequence, the occurrence of which in the serial data stream is monitored by the receiver as soon as the receiver E shown in Fig. 1 detects the occurrence of this bit sequence of the synchronous octet in the serial data stream D.
  • a new ATM cell which comprises a total of 64 octets including the synchronous octet, so that the receiver E can evaluate the individual octets of the corresponding ATM cell transmitted in nibbles, as in FIG is shown, according to the preferred exemplary embodiment, of course, the synchronous octet is transmitted in half-byte fashion, ie the four least significant bits 0-3 of the sync Hron octets are transmitted serially within a first nibble HBO and the four high-order bits 4-7 in a subsequent nibble HB1.
  • each ATM cell is transmitted half byte by byte by the successive transmission of a first nibble HBO and a second nibble HB1 from the transmitter to the receiver.
  • Each of these nibbles HBO, HB1 comprises four bits which are read in parallel and which are 12 of the S data channels K -K (see FIG. 1 ) .
  • intra-h al bj e d it nibbles HBO, HB1 a bit position a fe ⁇ most k data associated with anal.
  • the bit corresponds to, for example, as shown in FIG.
  • the receiver E may simply demultiplex the power fed into it se ⁇ rial bit sequence, since it after recognition of the A ufaturs the synchronous octets m the serial data stream is known to the beginning of the first nibble of the corresponding ATM cell, so that it according to the in Figure 2.
  • the assignment shown simply has to distribute each em bit in succession to the output-side data channels K 0 -K 3 , so that the parallel data channels present on the output side again occur correctly at the output of the receiver.
  • the "internal" header added to the standard ("external") ATM cell format with a total of 53 octets comprises, as has already been explained, a total of 10 octets 0 - 9.
  • the individual octets of this "internal" header comprise routing information for the transmission of the corresponding ATM cells within this internal header are some bits R which are not yet used and thus reserved, the bits designated SSN (Switching State Number) are used to transmit the corresponding ATM cell to a specific coupling element in a targeted manner For example, a specific coupling element can use the information from this SSN bit field to recognize whether the respective ATM cell is intended for the corresponding coupling element
  • the bits labeled CF define an unused flag (congestion flag) internal header em parity bit P for checking the parity of the routing information contained in the internal header Auxiliary bits are called AUX.
  • the MCRA bits denote the m 13 upper routing address of the corresponding ATM cell (multicast routing address).
  • the bits HK House Keeping
  • the bits ADI Address Identifier
  • CDP Cell Delay Priority
  • delay priorities can be set for the individual ATM cells.
  • the octets of the internal header designated SN Sequence Number
  • SN Sequence Number
  • RMR Redundant Module Receiver
  • the internal trailer which is also added to the standard cell format (octet 10-62), includes a test bit sequence called FCS2 (Frame Check Sequence) for the useful information (payload) transmitted in the information field.
  • FCS2 Frae Check Sequence
  • this external header contains address information MCI ( Multicast Connection Identifier) and VCI (Virtual Channel Identifier) Furthermore, the type of user information transmitted to the information field is designated (PTI (Payload Type Identification) and a certain cell priority (CLP, Cell Loss Priority) is assigned to the corresponding ATM cell. Finally, the external header contains another test octet ( FCS1, Frame Check Sequence), which is used to check both the external header (octets 10-14) and octets 2-9 of the internal header. 14
  • MCI Multicast Connection Identifier
  • VCI Virtual Channel Identifier
  • PTI Payload Type Identification
  • CLP Cell Loss Priority

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Des données numériques introduites sous forme parallèle d'un nombre déterminé de canaux (K0 - Kn) de données côté entrée sont transformées en un flux (D) de données série et lors de la réception, sont à nouveau divisées à l'aide du démultiplexage correspondant en canaux (K0 - Kn) de données parallèles côté sortie. Selon la présente invention, pour permettre l'affectation des bits entrés en parallèle des canaux (K0 - Kn) de données côté entrée sans processus important de commutation et sans informations de synchronisation supplémentaires, le flux (D) de données série transmis sous forme de cellules MTA est surveillé à la recherche d'une suite de bits déterminée qui est de toute manière transmise avec chaque format de cellule. Cette suite de bits caractéristique permet de déterminer la position des bits individuels des canaux (K0 - Kn) de données correspondants dans le flux de données optique série, si bien qu'une mise en parallèle correcte côté sortie du flux (D) de données série est possible.
EP98966214A 1998-01-22 1998-12-16 Systeme et procede de transmission Withdrawn EP1050182A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19802365 1998-01-22
DE19802365A DE19802365C2 (de) 1998-01-22 1998-01-22 Übertragungsverfahren und Übertragungssystem
PCT/DE1998/003696 WO1999038349A1 (fr) 1998-01-22 1998-12-16 Systeme et procede de transmission

Publications (1)

Publication Number Publication Date
EP1050182A1 true EP1050182A1 (fr) 2000-11-08

Family

ID=7855374

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98966214A Withdrawn EP1050182A1 (fr) 1998-01-22 1998-12-16 Systeme et procede de transmission

Country Status (8)

Country Link
US (1) US6836482B1 (fr)
EP (1) EP1050182A1 (fr)
CN (1) CN1124770C (fr)
AU (1) AU764446B2 (fr)
CA (1) CA2318186A1 (fr)
DE (1) DE19802365C2 (fr)
WO (1) WO1999038349A1 (fr)
ZA (1) ZA99392B (fr)

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DE10030393A1 (de) * 2000-06-21 2002-01-03 Siemens Ag Verfahren zur schnellen Synchronisation von Blockcodierern und -decodierern bei einer blockcodierten, bidirektionalen Datenübertragung über in einen bitorientierten Kanal
US6894970B1 (en) * 2000-10-31 2005-05-17 Chiaro Networks, Ltd. Router switch fabric protection using forward error correction
US20040117499A1 (en) * 2002-12-13 2004-06-17 Bo Liu System and method for detection of delineation of data units for a communication element

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Also Published As

Publication number Publication date
CN1284253A (zh) 2001-02-14
WO1999038349A1 (fr) 1999-07-29
AU764446B2 (en) 2003-08-21
US6836482B1 (en) 2004-12-28
DE19802365C2 (de) 2002-06-13
ZA99392B (en) 1999-07-22
DE19802365A1 (de) 1999-08-05
CN1124770C (zh) 2003-10-15
AU2264099A (en) 1999-08-09
CA2318186A1 (fr) 1999-07-29

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