EP1010048B1 - Spannungsregelungsschaltung zur unterdrückung des latch-up phänomens - Google Patents

Spannungsregelungsschaltung zur unterdrückung des latch-up phänomens Download PDF

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Publication number
EP1010048B1
EP1010048B1 EP98929294A EP98929294A EP1010048B1 EP 1010048 B1 EP1010048 B1 EP 1010048B1 EP 98929294 A EP98929294 A EP 98929294A EP 98929294 A EP98929294 A EP 98929294A EP 1010048 B1 EP1010048 B1 EP 1010048B1
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EP
European Patent Office
Prior art keywords
voltage
terminal
transistor
regulated
circuit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP98929294A
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English (en)
French (fr)
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EP1010048A1 (de
Inventor
Antonio Martino Ponzetta
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EM Microelectronic Marin SA
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EM Microelectronic Marin SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to a circuit for voltage regulation for regulating a voltage disturbed by a phenomenon called "latch-up".
  • a circuit of this type is described in the document GB 2,298,939, and is shown in Figure 1A of the present description.
  • This circuit includes a transistor command Q1 connected in series between an input terminal I and an output terminal O, and a voltage detector output D consisting of two resistors Ra and Rb connected in series between the output terminal O and the earth of the circuit.
  • a voltage corresponding to the output voltage detected by detector D is compared to a voltage of reference E3 by an operational amplifier AO, and the output voltage of the latter is applied to the terminal base of a transistor Q2. So a base current of control transistor Q1 can be controlled by the output voltage of the operational amplifier AO, by through transistor Q2, so the impedance of the control transistor Q1 is controlled to provide a predetermined voltage at the output terminal O.
  • a problem encountered during the operation of such circuit lies in the involuntary appearance of so-called "latch-up" phenomena that occur in a electronic component of the circuit, following external disturbances such as the provision of a electric voltage, electric current or radiation.
  • a device of this type is described in the application Japanese patent application published under No. 5,326,825 in the name of FUNAI ELECTRIC CO LTD, and is shown in Figure 1B of this description.
  • This device includes a integrated circuit IC1 at a first terminal of which is supplied a supply voltage Vdd, by through a bipolar transistor T1, and at the second terminal of which a resonant circuit is connected consisting of a resistor R3 and a capacitor C3.
  • a integrated circuit IC2 detection includes a terminal ground, a first terminal on which the supply voltage Vdd, and a second terminal connected said resonant circuit as well as at the base terminal of a bipolar transistor T2 by a resistor R2.
  • the terminal of base of transistor T1 is connected to the terminal of collector of transistor T2 by a resistor R1, and the emitter terminal of transistor T2 is grounded.
  • An object of the present invention is to provide a voltage regulation circuit intended to suppress a Inopportune latch-up phenomenon.
  • Another object of the present invention is to provide such a circuit meeting the cost criteria and of simplicity.
  • An advantage of the circuit according to the present invention is to provide a voltage regulation circuit having an uncomplicated structure, which makes it inexpensive.
  • Another advantage of the circuit according to this invention is to provide a circuit comprising means voltage comparison at the input of which is supplied the regulated voltage, these means being arranged so as to define two voltage thresholds likely to be predetermined to meet the requirements of the user.
  • Figure 2 shows a preferred embodiment of a circuit 1 according to the present invention.
  • Circuit 1 includes an input terminal I and a output terminal O of which a regulated voltage Vreg must be supplied, the voltage Vreg being supplied from so as to be substantially equal to a level of tension Vo.
  • Circuit 1 further includes a bipolar transistor 2, two capacitors 3 and 9, a resistor 5, a diode Zener 6, and voltage detection means 11.
  • the bipolar transistor 2 typically comprises a collector terminal C, emitter terminal E and terminal base B, terminals C and E being connected respectively at terminals I and O.
  • Resistor 5 is connected between terminal B and terminal C of transistor 2.
  • the Zener diode 6 is arranged so that it provides a voltage having a value chosen so as to form the voltage level Vo on the output terminal O.
  • Capacitors 3 and 9 are connected between the input terminal I and ground, and between the output terminal O and mass, respectively. Those skilled in the art will note that capacitor 3 is conventionally used as deworming capacitor, and that capacitor 9 is conventionally used as a smoothing capacitor and / or deworming. Capacitor 3 is not used as an improvement in the present invention, and therefore is not limiting in nature for the present invention.
  • the means 11 comprise an input terminal connected to terminal O, so as to receive the input Vreg voltage, a ground terminal, and an output terminal connected to terminal B, so as to provide an output control voltage Vres to control transistor 2.
  • the means 11 are arranged so that they detect whether the Vreg voltage is disturbed by a "latch-up" phenomenon and, if necessary, order an initialization of this voltage at its initial voltage level Vo, as is explained in more detail below.
  • the voltage regulation circuit comprises means for voltage detection which, following a type disturbance "latch-up", bring to the ground potential the tension regulated, which has the effect of removing this disturbance.
  • FIG. 3 shows in detail the mode of preferred embodiment of the means 11, according to the present invention.
  • the means 11 comprise means for supplying reference voltage 20 to provide a voltage of reference Vref from the voltage Vreg, a divider of voltage 21 intended to supply two regulated voltages corrected Vreg 'and Vreg "from the regulated voltage Vreg, two voltage comparators 23 and 22 to compare the voltage Vref at the voltages Vreg 'and Vreg ", respectively, and control means 24 for supplying, if necessary, the voltage Vres likely to command the transistor 2, and regulate the voltage Vreg.
  • the means 20 comprise an input terminal connected to the input terminal of the means 11 (i.e. at terminal O), so that the means 20 receive at input voltage Vreg, a ground terminal connected to the ground, and an output terminal connected to the comparators 22 and 23, so that the means 20 provide an output the voltage Vref.
  • the means 20 are known in the technical, see for example the articles "CMOS Analog Integrated Circuits Based on Weak Inversion Operation ", from E. Vittoz et al, IEEE Journal of Solid States Circuits, flight. SC-12, No. 3, June 1977, and “CMOS Voltage References Using Lateral Bipolar Transistors ", by M. Degrauwe et al, IEEE Journal of Solid States Circuits, vol. SC-20, No 6, December 1985.
  • Figure 4 shows a curve 31 corresponding to the relationship between the voltage Vref and the voltage Vreg.
  • the means 20 are arranged so that for a voltage value input voltage greater than 1.5 V, the output voltage Vref is substantially equal to a voltage threshold Vr 'of the order of 1.2 V, and that there is a voltage plateau on which the voltage Vref is substantially equal to a threshold of voltage Vr ", for low values of the voltage Vreg.
  • A'Vr ' as the voltage level below which a phenomenon "latch-up" is assumed to occur. In other words, when Vreg voltage drops significantly, a "latch-up" phenomenon is assumed to be responsible for this fall, as soon as the tension Vreg becomes less than A'Vr '.
  • a "Vr” a second voltage level as the voltage level below which a latch-up phenomenon is suppressed. In other words, during a drop in the voltage Vreg, as this is the case when a latch-up phenomenon occurs, this disturbance is removed, as soon as the voltage Vreg becomes less than A "Vr”.
  • Voltage levels A'Vr 'and A "Vr" are predetermined values according to specific to the user's requirements.
  • the voltage divider 21 is formed by a bridge resistive consisting of three resistors 25, 26 and 27 connected in series between the output terminal O and earth.
  • the connection point between the two resistors 26 and 27 is connected to a first input of comparator 23, so as to provide the input voltage Vreg '.
  • This tension is, by definition, proportional to tension Vreg, the proportionality ratio, referenced by A ', being predetermined and dependent on the values of resistances 27, 26 and 25.
  • FIG. 4 represents a curve 32 corresponding to the relationship between the voltage Vreg 'and the voltage Vreg. Point of connection between the two resistors 25 and 26 is connected to a first input of comparator 22, so to supply as input the voltage Vreg ".
  • This voltage is, by definition, proportional to the Vreg voltage, the proportionality ratio, referenced by A ", being predetermined and dependent on the values of the resistors 25, 26 and 27.
  • FIG. 4 represents a curve 33 corresponding to the relationship between the voltage Vreg "and the voltage Vreg.
  • Each comparator 23, 22 comprises a first terminal input on which a regulated voltage is supplied corrected Vreg ', Vreg ", respectively, as is described above, and a second input terminal on which is supplied the voltage Vref, as it is also described above.
  • the comparator 23 compares the voltage Vreg 'with the voltage Vref, while the comparator 22 compares the voltage Vreg "with the voltage Vref.
  • Each comparator 22, 23 further comprises a terminal output connected to a respective input terminal of control means 24.
  • the control means 24 further comprise a output terminal serving as output terminal of the means 11, so as to switch the voltage Vres, when one of the comparators 22, 23 switches, which controls the regulation of the Vreg voltage, as will be described so more detailed.
  • the means 24 can be formed by a scale known per se to those skilled in the art, and arranged so it switches to output a level voltage logic low enough to bring the transistor 2 in a blocked state, or a logic level of voltage high enough to bring transistor 2 in a conductive state, these two logical levels being designated “0L” and "1L", respectively.
  • circuit 1 The operation of circuit 1 according to this invention will be explained with reference to Figures 5A and 5B.
  • FIGS. 5A and 5B represent so diagram of the timing diagrams of the Vreg and Vres voltages present in circuit 1, respectively.
  • circuit 1 When circuit 1 is operating normally, i.e. when it is not disturbed by a latch-up phenomenon, the voltage Vreg is substantially equal to the level of voltage Vo, and the voltage detection means 11 output a logic level "1L" as voltage Lips. As a result, transistor 2 is held in a conductive state, so the voltage across its terminals base and transmitter subtracted from the terminal voltage of the Zener diode 6 is equal to the voltage level Vo.
  • a latch-up phenomenon is therefore declared responsible for the loss of control over the Vreg voltage.
  • the voltage Vreg '(curve 32) becomes below the threshold of voltage Vr '(curve 31), which causes the switching of comparator 23.
  • the means 24 advantageously bring the voltage Vres to "0L", this logical level being sufficient to block the transistor 2.
  • the integrated circuit under the influence of Latch-up phenomenon is therefore no longer fed under the voltage level Vo. This has the effect of bringing down notably the voltage Vreg and, consequently, the voltage Vref.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Electronic Switches (AREA)
  • Power Conversion In General (AREA)
  • Details Of Television Scanning (AREA)
  • Control Of Electrical Variables (AREA)
  • Control Of Voltage And Current In General (AREA)
  • Measurement Of Current Or Voltage (AREA)

Claims (5)

  1. Spannungsregulierungsschaltung (1) zum Liefern einer regulierten Spannung (Vreg), die einen vorgegebenen Pegel hat, wobei diese Schaltung ein die Spannung störendes "Latch-up"-Phänomen erfassen kann, dieses Phänomen unterdrücken kann und die Spannung auf den vorgegebenen Pegel zurückstellen kann, wobei diese Schaltung einen Eingangsanschluß (I) und einen Ausgangsanschluß (O), von dem die regulierte Spannung (Vreg) geliefert wird, umfaßt, wobei diese Schaltung einen Bipolartransistor (2), dessen Kollektoranschluß (C) an den Eingangsanschluß (I) angeschlossen ist und dessen Emitteranschluß (E) an den Ausgangsanschluß (O) angeschlossen ist, einen Widerstand (5), der zwischen den Kollektoranschluß (C) und den Basisanschluß (B) des Transistors (2) geschaltet ist, Mittel (6) zum Liefern einer im wesentlichen konstanten Spannung an den Basisanschluß des Transistors (2) sowie Spannungserfassungsmittel (11), die zwischen den Ausgangsanschluß (O) für die regulierte Spannung und den Basisanschluß des Transistors (2) geschaltet sind, umfaßt, dadurch gekennzeichnet, daß die Erfassungsmittel umfassen:
    Mittel zum Liefern einer Referenzspannung (20) anhand der regulierten Spannung, wobei diese Mittel mit einem Masseanschluß der Erfassungsmittel verbunden sind, wobei der Eingang dieser Liefermittel an den Ausgangsanschluß (O) für die regulierte Spannung angeschlossen ist, während der Ausgang dieser Mittel die Referenzspannung liefert, die je nach dem Wert der regulierten Spannung im wesentlichen gleich ersten und zweiten Spannungsschwellenwerten sein kann, wobei diese ersten und zweiten Schwellenwerte ersten bzw. zweiten vorgegebenen Spannungspegeln entsprechen;
    einen Spannungsteiler (21), der an zwei Ausgangsanschlüssen eine erste bzw. eine zweite regulierte Spannung liefert, die in Abhängigkeit von der regulierten Spannung korrigiert sind, wobei dieser Teiler einerseits an den Ausgangsanschluß (O) für die regulierte Spannung und andererseits an den Masseanschluß der Spannungserfassungsmittel (11) angeschlossen ist,
    einen ersten Spannungskomparator (23), der dazu bestimmt ist, die erste korrigierte regulierte Spannung mit dem ersten Schwellenwert der Referenzspannung zu vergleichen, wobei dieser Komparator (23) so beschaffen ist, daß er umschaltet, wenn die erste korrigierte regulierte Spannung kleiner als der erste Schwellenwert der Referenzspannung wird;
    einen zweiten Spannungskomparator (22), der dazu bestimmt ist, die zweite korrigierte regulierte Spannung mit dem zweiten Schwellenwert der Referenzspannung zu vergleichen, wobei dieser Komparator (22) so beschaffen ist, daß er umschaltet, wenn die zweite korrigierte regulierte Spannung niedriger als der zweite Schwellenwert der Referenzspannung wird;
    Steuermittel (24) zum Steuern des Umschaltens des Transistors (2) in den gesperrten Zustand oder in den leitenden Zustand, wobei zwei Eingänge der Steuermittel (24) an die Ausgänge des ersten bzw. des zweiten Spannungskomparators (23, 22) angeschlossen sind, während der Ausgang der Steuermittel an den Basisanschluß des Transistors (2) angeschlossen ist, wobei diese Steuermittel (24) so beschaffen sind, daß der Transistor (2) im gesperrten Zustand ist, wenn eine Störung dazu führt, daß die regulierte Spannung unter einen ersten vorgegebenen Spannungspegel abfällt, unterhalb dessen ein "Latch-up"-Phänomen, das für diese Störung verantwortlich ist, definiert ist, wobei das Umschalten des Transistors (2) in den gesperrten Zustand die regulierte Spannung auf Massepotential legt, und daß der Transistor (2) im leitenden Zustand ist, wenn die regulierte Spannung im wesentlichen gleich dem vorgegebenen Pegel ist, d. h. höher als der erste Spannungspegel ist, oder wenn sie niedriger als ein zweiter vorgegebener Spannungspegel ist, unterhalb dessen das "Latch-up"-Phänomen unterdrückt wird.
  2. Spannungserfassungs- und Spannungsregulierungsschaltung (1) nach Anspruch 1, dadurch gekennzeichnet, daß der Spannungsteiler (21) außerdem drei in Reihe geschaltete Widerstände (25, 26, 27) umfaßt, derart, daß sie eine Widerstandsbrücke bilden, die am Ausgang die ersten und zweiten korrigierten regulierten Spannungen liefert.
  3. Spannungserfassungs- und Spannungsregulierungsschaltung (1) nach Anspruch 1, dadurch gekennzeichnet, daß die Spannungsliefermittel (6) aus einer Zener-Diode gebildet sind.
  4. Spannungsregulierungsschaltung (1) nach Anspruch 1, dadurch gekennzeichnet, daß sie außerdem einen ersten Kondensator (3) umfaßt, der zwischen den Eingangsanschluß (I) der Schaltung (1) und Masse geschaltet und als Entstörungskondensator ausgebildet ist.
  5. Spannungsregulierungsschaltung (1) nach Anspruch 1, dadurch gekennzeichnet, daß sie außerdem einen zweiten Kondensator (9) umfaßt, der zwischen den Ausgangsanschluß (O) der Schaltung (1) und Masse geschaltet und als Entstörungs- und Glättungskondensator ausgebildet ist.
EP98929294A 1997-05-12 1998-05-11 Spannungsregelungsschaltung zur unterdrückung des latch-up phänomens Expired - Lifetime EP1010048B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP98929294A EP1010048B1 (de) 1997-05-12 1998-05-11 Spannungsregelungsschaltung zur unterdrückung des latch-up phänomens

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP97107722A EP0878752A1 (de) 1997-05-12 1997-05-12 Spannungsregelung zur Unterdrückung des Latch-up Effekts
EP97107722 1997-05-12
PCT/EP1998/002749 WO1998052111A1 (fr) 1997-05-12 1998-05-11 Circuit de regulation de tension destine a supprimer un phenomene dit 'latch-up'
EP98929294A EP1010048B1 (de) 1997-05-12 1998-05-11 Spannungsregelungsschaltung zur unterdrückung des latch-up phänomens

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EP1010048A1 EP1010048A1 (de) 2000-06-21
EP1010048B1 true EP1010048B1 (de) 2002-05-02

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EP97107722A Withdrawn EP0878752A1 (de) 1997-05-12 1997-05-12 Spannungsregelung zur Unterdrückung des Latch-up Effekts
EP98929294A Expired - Lifetime EP1010048B1 (de) 1997-05-12 1998-05-11 Spannungsregelungsschaltung zur unterdrückung des latch-up phänomens

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EP97107722A Withdrawn EP0878752A1 (de) 1997-05-12 1997-05-12 Spannungsregelung zur Unterdrückung des Latch-up Effekts

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US (1) US6184664B1 (de)
EP (2) EP0878752A1 (de)
JP (1) JP2001525091A (de)
KR (1) KR20010012426A (de)
AT (1) ATE217102T1 (de)
CA (1) CA2289935A1 (de)
DE (1) DE69805188T2 (de)
WO (1) WO1998052111A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465914B1 (en) * 2000-03-09 2002-10-15 Capable Controls, Inc. Microcontroller power removal reset circuit
US6473284B1 (en) * 2000-09-06 2002-10-29 General Electric Company Low-power dc-to-dc converter having high overvoltage protection
EP1280033B1 (de) 2001-07-26 2006-05-31 AMI Semiconductor Belgium BVBA EMV gerechter Spannungsregler mit kleiner Verlustspannung
ATE390713T1 (de) * 2004-06-01 2008-04-15 Deutsch Zentr Luft & Raumfahrt Verfahren zum löschen von in einer schaltung auftretenden latch-ups sowie anordnungen zum durchführen des verfahrens
DE102005025160B4 (de) * 2004-06-01 2008-08-07 Deutsches Zentrum für Luft- und Raumfahrt e.V. Verfahren zum Löschen von in einer Schaltung auftretenden Latch-Ups sowie Anordnungen zum Durchführen des Verfahrens
US7564230B2 (en) * 2006-01-11 2009-07-21 Anadigics, Inc. Voltage regulated power supply system
US9071073B2 (en) * 2007-10-04 2015-06-30 The Gillette Company Household device continuous battery charger utilizing a constant voltage regulator
KR100915830B1 (ko) * 2008-03-12 2009-09-07 주식회사 하이닉스반도체 반도체 집적 회로

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA718127A (en) * 1961-06-20 1965-09-14 J. Giger Adolf Electronic direct current voltage regulator
JPH0727421B2 (ja) * 1990-05-18 1995-03-29 東光株式会社 直流電源回路
US5212616A (en) * 1991-10-23 1993-05-18 International Business Machines Corporation Voltage regulation and latch-up protection circuits
JP2925470B2 (ja) * 1995-03-17 1999-07-28 東光株式会社 直列制御形レギュレータ

Also Published As

Publication number Publication date
CA2289935A1 (en) 1998-11-19
ATE217102T1 (de) 2002-05-15
KR20010012426A (ko) 2001-02-15
DE69805188D1 (de) 2002-06-06
JP2001525091A (ja) 2001-12-04
DE69805188T2 (de) 2002-11-28
EP0878752A1 (de) 1998-11-18
EP1010048A1 (de) 2000-06-21
WO1998052111A1 (fr) 1998-11-19
US6184664B1 (en) 2001-02-06

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