EP1010048B1 - Voltage regulating circuit for eliminating "latch-up - Google Patents

Abstract

The voltage regulator has a series bipolar transistor (2) to adjust the voltage output. The base voltage of the transistor is controlled by a resistor (5) and Zener diode (6) connected across the unregulated potential source, with the base connected to the junction between the resistor and the Zener diode. In addition, a voltage detector circuit (11) is connected across the regulated output and is also connected to the base of the transistor. The voltage detector causes the transistor to switch to the blocking state when latch up occurs. Filter capacitors (3,9) are fitted across the unregulated and the regulated supplies.

Description

The present invention relates to a circuit for voltage regulation for regulating a voltage disturbed by a phenomenon called "latch-up".

There are many circuits in the prior art voltage regulation.

A circuit of this type is described in the document GB 2,298,939, and is shown in Figure 1A of the present description. This circuit includes a transistor command Q1 connected in series between an input terminal I and an output terminal O, and a voltage detector output D consisting of two resistors Ra and Rb connected in series between the output terminal O and the earth of the circuit.

A voltage corresponding to the output voltage detected by detector D is compared to a voltage of reference E3 by an operational amplifier AO, and the output voltage of the latter is applied to the terminal base of a transistor Q2. So a base current of control transistor Q1 can be controlled by the output voltage of the operational amplifier AO, by through transistor Q2, so the impedance of the control transistor Q1 is controlled to provide a predetermined voltage at the output terminal O.

A problem encountered during the operation of such circuit lies in the involuntary appearance of so-called "latch-up" phenomena that occur in a electronic component of the circuit, following external disturbances such as the provision of a electric voltage, electric current or radiation.

We commonly refer to the phenomenon as "latch-up" while phenomenon occurring in an integrated circuit following external disturbances such as the provision of voltage, current or radiation.

There are many prior art devices to detect the latch-up phenomenon in a substrate and, in particular, devices analyzing a current likely to be disturbed by said phenomenon.

A device of this type is described in the application Japanese patent application published under No. 5,326,825 in the name of FUNAI ELECTRIC CO LTD, and is shown in Figure 1B of this description. This device includes a integrated circuit IC1 at a first terminal of which is supplied a supply voltage Vdd, by through a bipolar transistor T1, and at the second terminal of which a resonant circuit is connected consisting of a resistor R3 and a capacitor C3. A integrated circuit IC2 detection includes a terminal ground, a first terminal on which the supply voltage Vdd, and a second terminal connected said resonant circuit as well as at the base terminal of a bipolar transistor T2 by a resistor R2. The terminal of base of transistor T1 is connected to the terminal of collector of transistor T2 by a resistor R1, and the emitter terminal of transistor T2 is grounded.

In the device described above in relation to FIG. 1B, if a "latch-up" phenomenon occurs, a notable drop in the supply voltage Vdd is detected by IC2 integrated circuit. In this case, the transistors T1 and T2 are blocked, and the voltage supplying the integrated circuit IC1 is interrupted, which initializes this circuit. As a result, the integrated circuit IC1 works normally again.

However, these devices have structures complex, and require a large number of components electronics to perform the detection functions and of regulation.

An object of the present invention is to provide a voltage regulation circuit intended to suppress a Inopportune latch-up phenomenon.

Another object of the present invention is to provide such a circuit meeting the cost criteria and of simplicity.

These and other objects are achieved by the voltage regulation circuit according to claim 1.

An advantage of the circuit according to the present invention is to provide a voltage regulation circuit having an uncomplicated structure, which makes it inexpensive.

Another advantage of the circuit according to this invention is to provide a circuit comprising means voltage comparison at the input of which is supplied the regulated voltage, these means being arranged so as to define two voltage thresholds likely to be predetermined to meet the requirements of the user.

• les figures 1A et 1B déjà citées représentent deux circuits de régulation de tension selon l'art antérieur;
• la figure 2 représente un mode de réalisation préféré d'un circuit de régulation de tension selon la présente invention;
• la figure 3 représente de façon détaillée le mode de réalisation préféré des moyens de détection du circuit de la figure 2;
• la figure 4 représente la relation entre trois tensions présentes dans le circuit de régulation de tension selon le mode de réalisation préféré de la présente invention; et
• les figures 5A et 5B représentent les chronogrammes de la tension régulée et du signal fourni par le circuit de régulation de tension selon le mode de réalisation préféré de la présente invention.

These objects, characteristics and advantages, as well as others, of the present invention will appear more clearly on reading the detailed description of a preferred embodiment of the invention, given by way of example only, in relation to the attached figures, among which:

• FIGS. 1A and 1B already cited represent two voltage regulation circuits according to the prior art;
• FIG. 2 represents a preferred embodiment of a voltage regulation circuit according to the present invention;
• Figure 3 shows in detail the preferred embodiment of the detection means of the circuit of Figure 2;
• FIG. 4 represents the relationship between three voltages present in the voltage regulation circuit according to the preferred embodiment of the present invention; and
• FIGS. 5A and 5B represent the timing diagrams of the regulated voltage and of the signal supplied by the voltage regulation circuit according to the preferred embodiment of the present invention.

Figure 2 shows a preferred embodiment of a circuit 1 according to the present invention.

Circuit 1 includes an input terminal I and a output terminal O of which a regulated voltage Vreg must be supplied, the voltage Vreg being supplied from so as to be substantially equal to a level of tension Vo. Circuit 1 further includes a bipolar transistor 2, two capacitors 3 and 9, a resistor 5, a diode Zener 6, and voltage detection means 11.

The bipolar transistor 2 typically comprises a collector terminal C, emitter terminal E and terminal base B, terminals C and E being connected respectively at terminals I and O. Resistor 5 is connected between terminal B and terminal C of transistor 2.

The Zener diode 6 is arranged so that it provides a voltage having a value chosen so as to form the voltage level Vo on the output terminal O.

Capacitors 3 and 9 are connected between the input terminal I and ground, and between the output terminal O and mass, respectively. Those skilled in the art will note that capacitor 3 is conventionally used as deworming capacitor, and that capacitor 9 is conventionally used as a smoothing capacitor and / or deworming. Capacitor 3 is not used as an improvement in the present invention, and therefore is not limiting in nature for the present invention.

The means 11 comprise an input terminal connected to terminal O, so as to receive the input Vreg voltage, a ground terminal, and an output terminal connected to terminal B, so as to provide an output control voltage Vres to control transistor 2. The means 11 are arranged so that they detect whether the Vreg voltage is disturbed by a "latch-up" phenomenon and, if necessary, order an initialization of this voltage at its initial voltage level Vo, as is explained in more detail below.

Indeed, following numerous experiments, the Applicant of the present invention has found that most effective solutions to remove a "latch-up" phenomenon in an integrated circuit consists of bring the voltage level to ground potential of the integrated circuit disturbed by said phenomenon, for a sufficient time for this circuit drops below a certain voltage threshold.

For this purpose, the voltage regulation circuit according to the present invention comprises means for voltage detection which, following a type disturbance "latch-up", bring to the ground potential the tension regulated, which has the effect of removing this disturbance.

Figure 3 shows in detail the mode of preferred embodiment of the means 11, according to the present invention.

The means 11 comprise means for supplying reference voltage 20 to provide a voltage of reference Vref from the voltage Vreg, a divider of voltage 21 intended to supply two regulated voltages corrected Vreg 'and Vreg "from the regulated voltage Vreg, two voltage comparators 23 and 22 to compare the voltage Vref at the voltages Vreg 'and Vreg ", respectively, and control means 24 for supplying, if necessary, the voltage Vres likely to command the transistor 2, and regulate the voltage Vreg.

The means 20 comprise an input terminal connected to the input terminal of the means 11 (i.e. at terminal O), so that the means 20 receive at input voltage Vreg, a ground terminal connected to the ground, and an output terminal connected to the comparators 22 and 23, so that the means 20 provide an output the voltage Vref. The means 20 are known in the technical, see for example the articles "CMOS Analog Integrated Circuits Based on Weak Inversion Operation ", from E. Vittoz et al, IEEE Journal of Solid States Circuits, flight. SC-12, No. 3, June 1977, and "CMOS Voltage References Using Lateral Bipolar Transistors ", by M. Degrauwe et al, IEEE Journal of Solid States Circuits, vol. SC-20, No 6, December 1985.

We briefly recall the operation of means in referring to Figure 4. Figure 4 shows a curve 31 corresponding to the relationship between the voltage Vref and the voltage Vreg. In this example, the means 20 are arranged so that for a voltage value input voltage greater than 1.5 V, the output voltage Vref is substantially equal to a voltage threshold Vr 'of the order of 1.2 V, and that there is a voltage plateau on which the voltage Vref is substantially equal to a threshold of voltage Vr ", for low values of the voltage Vreg.

We define a first voltage level A'Vr 'as the voltage level below which a phenomenon "latch-up" is assumed to occur. In other words, when Vreg voltage drops significantly, a "latch-up" phenomenon is assumed to be responsible for this fall, as soon as the tension Vreg becomes less than A'Vr '. We also define a second voltage level A "Vr" as the voltage level below which a latch-up phenomenon is suppressed. In other words, during a drop in the voltage Vreg, as this is the case when a latch-up phenomenon occurs, this disturbance is removed, as soon as the voltage Vreg becomes less than A "Vr". Voltage levels A'Vr 'and A "Vr" are predetermined values according to specific to the user's requirements.

In the preferred embodiment shown in Figure 3, the voltage divider 21 is formed by a bridge resistive consisting of three resistors 25, 26 and 27 connected in series between the output terminal O and earth. The connection point between the two resistors 26 and 27 is connected to a first input of comparator 23, so as to provide the input voltage Vreg '. This tension is, by definition, proportional to tension Vreg, the proportionality ratio, referenced by A ', being predetermined and dependent on the values of resistances 27, 26 and 25. By way of illustration, FIG. 4 represents a curve 32 corresponding to the relationship between the voltage Vreg 'and the voltage Vreg. Point of connection between the two resistors 25 and 26 is connected to a first input of comparator 22, so to supply as input the voltage Vreg ". This voltage is, by definition, proportional to the Vreg voltage, the proportionality ratio, referenced by A ", being predetermined and dependent on the values of the resistors 25, 26 and 27. By way of illustration, FIG. 4 represents a curve 33 corresponding to the relationship between the voltage Vreg "and the voltage Vreg.

Each comparator 23, 22 comprises a first terminal input on which a regulated voltage is supplied corrected Vreg ', Vreg ", respectively, as is described above, and a second input terminal on which is supplied the voltage Vref, as it is also described above. Thus, the comparator 23 compares the voltage Vreg 'with the voltage Vref, while the comparator 22 compares the voltage Vreg "with the voltage Vref. Each comparator 22, 23 further comprises a terminal output connected to a respective input terminal of control means 24.

The control means 24 further comprise a output terminal serving as output terminal of the means 11, so as to switch the voltage Vres, when one of the comparators 22, 23 switches, which controls the regulation of the Vreg voltage, as will be described so more detailed. The means 24 can be formed by a scale known per se to those skilled in the art, and arranged so it switches to output a level voltage logic low enough to bring the transistor 2 in a blocked state, or a logic level of voltage high enough to bring transistor 2 in a conductive state, these two logical levels being designated "0L" and "1L", respectively.

The operation of circuit 1 according to this invention will be explained with reference to Figures 5A and 5B.

FIGS. 5A and 5B represent so diagram of the timing diagrams of the Vreg and Vres voltages present in circuit 1, respectively.

When circuit 1 is operating normally, i.e. when it is not disturbed by a latch-up phenomenon, the voltage Vreg is substantially equal to the level of voltage Vo, and the voltage detection means 11 output a logic level "1L" as voltage Lips. As a result, transistor 2 is held in a conductive state, so the voltage across its terminals base and transmitter subtracted from the terminal voltage of the Zener diode 6 is equal to the voltage level Vo.

Let us consider, at an instant t1, that a perturbation appears so that the Vreg voltage begins to drop significantly below the voltage level Vo. This fall continues until an instant t2 when the voltage Vreg reaches the voltage level A'Vr ', then becomes below this level.

A latch-up phenomenon is therefore declared responsible for the loss of control over the Vreg voltage. As shown in Figure 4, when the voltage Vreg becomes lower than the voltage level A'Vr ', the voltage Vreg '(curve 32) becomes below the threshold of voltage Vr '(curve 31), which causes the switching of comparator 23. As comparator 23 switches, the means 24 advantageously bring the voltage Vres to "0L", this logical level being sufficient to block the transistor 2. The integrated circuit under the influence of Latch-up phenomenon is therefore no longer fed under the voltage level Vo. This has the effect of bringing down notably the voltage Vreg and, consequently, the voltage Vref.

This fall continues until an instant t3 when the voltage Vreg reaches voltage level A "Vr", then becomes below this level. The latch-up phenomenon responsible for the disturbance of the Vreg voltage in below the voltage level Vo at time t2 is from when deleted. As shown in Figure 4, when the voltage Vreg becomes lower than the level of voltage A "Vr", the voltage Vreg "(curve 33) becomes below the voltage threshold Vr "(curve 31), which causes the comparator 22 to switch. As the comparator 22 switches, the means 24 bring advantageously the voltage Vres at logic level "1L". As this logical level is sufficient to make conductor transistor 2, the voltage between its terminals base and transmitter increased by the voltage across Zener diode 6 is again equal, at time t4, to voltage level Vo. The operation of circuit 1 therefore becomes normal again, until a "latch-up" phenomenon again disrupts circuit 1, and that the situation similar to that of time t1 repeats.

It goes without saying for those skilled in the art that the description detailed above may undergo various modifications without depart from the scope of the present invention. As a variant other means of constant voltage supply as the Zener diode.

Claims (5)

1. Voltage regulator circuit (1) for supplying a regulated voltage (Vreg) having a predetermined level, this circuit being able to detect a latch-up phenomenon disturbing said voltage, to suppress this phenomenon and re-establish the voltage at said predetermined level, this circuit including an input terminal (I) and an output terminal (O) from which the regulated voltage (Vreg) is supplied, this circuit including a bipolar transistor (2) whose collector terminal (C) is connected to said input terminal (I), and whose emitter terminal (E) is connected to said output terminal (O), a resistor (5) connected across the collector terminal (C) and the base terminal (B) of said transistor (2), means (6) for supplying a substantially constant voltage at the base terminal of said transistor (2) and voltage detection means (11) connected across the output terminal (O) of the regulated voltage and the base terminal of said transistor (2), characterised in that detection means include :

   reference voltage supply means (20) from the regulated voltage, said means being connected to an earth terminal of said detection means, the input of said supply means being connected to the output terminal (O) of the regulated voltage and the output of said supply means supplying the reference voltage capable of being substantially equal to first and second voltage thresholds, as a function of the value of the regulated voltage, these first and second thresholds corresponding to said first and second predetermined voltage levels, respectively;

   a voltage divider (21) for supplying via two output terminals, respectively first and second regulated voltages corrected as a function of said regulated voltage, this divider being connected to the output terminal (O) of the regulated voltage and to the earth terminal of said voltage detection means (11),

   a first voltage comparator (23) intended to compare the first corrected regulated voltage to the first reference voltage threshold, this comparator (23) being arranged to switch when the first corrected regulated voltage becomes lower than said first reference voltage threshold;

   a second voltage comparator (22) intended to compare the second corrected regulated voltage to the second reference voltage threshold, this comparator (22) being arranged to switch when the second corrected regulated voltage becomes lower than said second reference voltage threshold;

   control means (24) for controlling the switching of said transistor (2) into the blocked state or the conducting state, two inputs of said control means (24) being connected to the outputs of the first and second voltage comparators (23, 22), respectively, the output of said control means being connected to the base terminal of the transistor (2), these control means (24) being arranged so that the transistor (2) is in the blocked state when a disturbance causes said regulated voltage to drop below a first predetermined voltage level, a level below which a latch-up phenomenon is defined as being responsible for said disturbance, the switching of said transistor (2) into the blocked state bringing said regulated voltage to the earth potential, and so that the transistor (2) is in the conducting state when said regulated voltage is substantially equal to the predetermined level, i.e. higher than the first voltage level, or when it is lower than a second predetermined voltage level, the latch-up phenomenon being suppressed below such level.
2. Voltage detection and regulator circuit (1) according to claim 1, characterised in that said voltage divider (21) further includes three resistors (25, 26, 27) connected in series, so that they form a resistive bridge supplying at its output the first and second corrected regulated voltages.
3. Voltage detection and regulator circuit (1) according to claim 1, characterised in that the voltage supply means (6) are formed of a Zener diode.
4. Voltage regulator circuit (1) according to claim 1, characterised in that it further includes a first capacitor (3) connected across said input terminal (I) of said circuit (1) and earth, this capacitor being arranged as an interference suppression capacitor.
5. Voltage regulator circuit (1) according to claim 1, characterised in that it further includes a second capacitor (9) connected across said output terminal (O) of said circuit (1) and earth, this capacitor being arranged as an interference suppression and smoother capacitor.

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