EP0987849A1 - Direktes spreizspektrum nachrichtenübertragungsystem entsprechend verzögertem multiplex modus, und nachrichtenübertragungsverfahren dieses system verwendend - Google Patents

Direktes spreizspektrum nachrichtenübertragungsystem entsprechend verzögertem multiplex modus, und nachrichtenübertragungsverfahren dieses system verwendend Download PDF

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Publication number
EP0987849A1
EP0987849A1 EP98905638A EP98905638A EP0987849A1 EP 0987849 A1 EP0987849 A1 EP 0987849A1 EP 98905638 A EP98905638 A EP 98905638A EP 98905638 A EP98905638 A EP 98905638A EP 0987849 A1 EP0987849 A1 EP 0987849A1
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European Patent Office
Prior art keywords
data
section
bits
multiplex
spread spectrum
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EP98905638A
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English (en)
French (fr)
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EP0987849A4 (de
Inventor
Naoki Okamoto
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal

Definitions

  • the present invention relates to a spread spectrum communication and more particularly to a spread spectrum communication system conforming to a delayed multiplex mode transmission, and a method of communication using the system.
  • a spread spectrum communication system has recently developed and attracted a great deal of public attention as a new interesting communication method.
  • a typical modulation system used in conventional data communication systems is a narrow band modulation system which can be realized by relatively small circuitry but is weak to interference such as multipath interference and narrow band color noises, which may occur indoors in offices and works.
  • the spread spectrum communication system is free from the above-mentioned problem since it can spread a data spectrum with a spread code and transmit the spread-spectrum coded data in a wide band.
  • the spread spectrum communication system involves a disadvantage of requiring a widened bandwidth to transmit data at a high speed.
  • a bandwidth of 22 MHz is required to realize spread-spectrum transmission of QPSK (Quadrature Phase Shift Keying) modulated data with 11 chips of spread code at a transmission rate of 2 Mbps.
  • QPSK Quadrature Phase Shift Keying
  • the bandwidth of 110 MHz is needed to transmit data at 10 Mbps.
  • radio transmission has restriction on bandwidth makes it more difficult to realize the high-speed data transmission by the spread-spectrum communication method.
  • Delayed multiplex system a method for multiplexing spectrum signals with a delay
  • the use of this method can increase the data transmission rate within a limited bandwidth.
  • the data transmission rate 2 Mbps at 22 MHz (as described before) can be increased to 4 Mbps by multiplexing the data twice and further to 10 Mbps by multiplexing the data five times.
  • Fig. 6 shows a typical block diagram of a conventional system used for proposed delayed multiplex transmission method.
  • data generated by a data generating section 10 is differentially coded by a differential coding section 11 and then converted to parallel sets of data to be multiplexed by a series-to-parallel (S/P) converting section 12.
  • the parallel data sets are transferred to respective multiplying sections (13-1 ⁇ 13-5) whereby they are spread by multiplying by a PN code received from a PN generator 14. Then, the parallel data sets are delayed respectively by the delay elements (15-1 ⁇ 15-5).
  • the delayed parallel data sets are combined by a frequency combining section 17 to form multivalued digital signals which are then modulated with oscillation of an oscillator 18 by a modulator 17 and transmitted through a frequency converter 19 and a power amplifier 20.
  • the delayed multiplex data transmission still encounters an increase in error rate from interference between multiplexed signals.
  • the inventor of the present application also proposed a method for improving the correlation and error rate for the delayed multiplex transmission (Japanese Patent Application No. 8-13963).
  • Fig. 7 shows a typical circuit diagram of a conventional delayed multiplex system by which improvement in error rate has been realized. This example is described below.
  • the transmission system is the same with the system shown before in Fig. 6.
  • a received frequency signal is converted to a base band signal by a frequency converting section 21 and correlated by a correlator 23.
  • the correlation is latched by a latch section 24 at the timing of a correlating spike and, then, is recovered from the deterioration due to auto-correlation by a correlation processing section 25.
  • This correlation output is distributed by a distributor 26.
  • the signal is controlled by a latch controller 29 and latched by latch sections 27 and 28. According to the aforementioned actual example, the signal is latched with 2 chips or 3 chips.
  • the signal is differentiated by a differential section 30 and discriminated and demodulated by a discriminating section 31.
  • Fig. 8 is a typical construction block diagram of the correlating processing section of Fig. 7. This depicts a five-multiplex case. In Fig. 8, there is shown only one line that must be doubled for realizing the system of Fig. 7.
  • An input signal is input to shift registers 25S corresponding to the number of input bits.
  • the registers hold correlation spikes by four before and after a desired demodulation timing spike.
  • An arithmetic unit 25P with a selecting function carries-out operations on the signals at a timing signal generated by a timing signal generator 25T which matches the timings of input and output according to signals from a correlation synchronizing circuit (not shown in Fig. 8).
  • Fig. 9 is a block diagram showing a typical internal construction of the arithmetic unit with a selecting function, which shown in Fig. 8.
  • Fig. 9 The use of the unit of Fig. 9 can considerably decrease a change in amplitude of a signal due to the influence of an auto-correlation side-lobe and can therefore make a great improvement in error rate.
  • the operation of this unit is as follows:
  • signals A and F are input to a selector 25P1
  • signals B and G are input to a selector 25P2
  • signals C and H are input to a selector 25P3
  • signals D and I are input to a selector 25P4.
  • the selectors 25P1-25P4 select signals A, B, C and D respectively.
  • the selected signals A-D are added together by an adder 25P5 and then divided by 11 by a divider 25P6.
  • the resultant signal is added to E' by an adder-subtracter 25P9, then latched by a latching section 25P8 and output.
  • preceding and proceeding correlation signals are used for improvement of the correlation output.
  • received signals are 5-multiplex signals, each signal is composed of five blocks and five correlation outputs are used for improvement in correlation.
  • five blocks cannot be obtained due to the transmitted data length.
  • Fig. 10 is a conceptual illustration of an exemplified state of five-multiples data.
  • the conventional correlation-improved circuit cannot exert a sufficient effect of improving the correlation because blocks of coded signals are partly omitted.
  • An error rate for the last three symbols becomes worse.
  • 1 bit error causes retransmission of data. Therefore, an increase in error rate for above-mentioned symbols decreases the throughput of the packet transmission system.
  • the present invention was made to provide a direct spread spectrum communication system conforming to a delayed multiplex mode transmission and a communication method using the system, which can realize improvement in correlation and improvement in error rate in any data length by applying the below mentioned technical means featuring the present invention.
  • every packet may always contain complete blocks with no lack in a symbol even in the last section thereof by appending additional bits so as to form a packet consisting of, e.g., five blocks when the number of multiplexed signals is 5. This can completely solve the problem of increasing an error rate due to lacking in a last symbol when multiplexing signals, which is involved in a prior art.
  • the transmission error rate of the whole system and the packet throughput of the system can be improved by selectively appending additional bits to the multiplex sections.
  • the additional bits interposed between a simplex section and a multiplexed section can prevent the transmit data from being affected by the unstable operations of digital and analog circuits during a transitional period after switching from a simplex section to a multiplexed section, consequently increasing the throughput of the communication system of the present invention.
  • the additional bit section is placed between a simplex section and a multiplexed section in such a way that 1 ⁇ the number of the bits included the additional bit section corresponds to a time longer than that required for stabilizing the operation of the system (i.e., the length of transitional section plus the unstable section) and 2 ⁇ a total number of added symbols (bits) and symbols in the multiplexed section is an integer multiple of the multiplex number.
  • the data format thus defined enables the additional bits to protect data against the influence of unstable period of the system and improve the transmission error rate of the system due to a lacking of a block.
  • the content of additional bits is controlled so as to cause the bits to function as the preprocessed section for convolutional coding of the data.
  • the transmit data from the head (effective bit) can be effectively corrected for possible error in the format when conducting error correction with the convolutional codes.
  • CRC Cyclic Redundancy Checking
  • the number of additional bits is selected to be equal to a common multiple of the multiplex number and a unit of bits (e.g., 8 bits) to be processed by the system, whereby the transmission length can be represented in a byte unit and no need of calculation with fractions is assured to facilitate the communication processing.
  • a unit of bits e.g. 8 bits
  • Fig. 1 is a view for explaining an example of constructing data blocks to be used for a communication system according to the present invention.
  • MAC layer In the general digital communications such as packet communications, transmissions are usually controlled by an upper layer 1 called MAC layer as shown in Fig. 1.
  • a data generating section 2 is capable of generating transmit information from data received from the upper layer 1 by appending an additional bit to the data by a bit appending means so that the data can have a specified length being an integer multiple of the number of multiplexed data blocks.
  • Any packet in packet communications usually must include a bit synchronization section, a frame synchronization section and a various information section as essential data and then a main transmittable data section.
  • the data transferred from the upper layer is placed in this main data section.
  • the various information section includes usually an error correction mode, a packet length, a scramble method and so on.
  • the bit synchronization section is used for wave detection, carrier restoration and clock reproduction data.
  • the receiving terminal recognizes receipt of transmitted data according to the bit synchronization section and makes the above-described preparation for receiving the transmitted data.
  • the data length of, e.g., 256 bits is used.
  • the receiving terminal When m series of 31-bit patterns are in the frame synchronization section, the receiving terminal knows the data start timing according to the specified bit pattern and recognizes what information each bit carries by calculation on the timing data.
  • Fig. 1 shows three examples of data blocks used in the embodiment of the present invention.
  • An example (B1) of Fig. 1 is a data block in which an additional bit is interposed between a bit synchronization section and a frame synchronization section.
  • the terminal knows the symbol length of a data part can be known from information received from the upper layer 1. Since symbol lengths of a bit synchronization section, a frame synchronization section and a various information section are previously known, the number of additional bits required to adjust the total number of symbols to be an integer multiple of the data blocks to be multiplexed is placed before the frame synchronization section. The total number of symbols of, e.g., five data blocks to be multiplexed is such that it can be divided by 5.
  • a packet can have five complete data blocks and does not suffer lacking in symbols in the last part. This can eliminate the possibility of increasing the error rate due to a lack of a last symbol in a packet.
  • the error rate in packet communications can be improved and the problem that the prior arts have encountered can be thus solved.
  • the total number of symbols in a packet is increased by additional bits placed before the frame synchronization section in each data block but no need for changing of data to be demodulated is caused since each data block can be demodulated referring to the frame synchronization.
  • An exemplified data block (B2) of Fig. 1 has an additional bit section placed before a data section, thereby the start timing of the data section may be changed.
  • a various information section before the additional bit section can include information as to the number of added bits so as to correctly find the header of the data section. This also eliminates the possibility of increasing the error rate due to a lack of a last symbol in a packet.
  • An exemplified data block (B3) of Fig. 1 has an additional bit section placed after the end of a data section, i.e., where a symbol is lacking.
  • the data length (packet length) is previously specified and indicated in a various information section, thus preventing demodulation of the additional bits appended to the data section.
  • the operating mode is automatically switched to the transmission mode on completion of receipt of data.
  • Added bits only compensate lack of a symbol in an incomplete one of blocks multiplexed blocks and may be therefore negligible in relation to a switching time. In this instance, it is also possible to eliminate the possibility of increasing the error rate of a packet due to a lack of a symbol in the last one of the multiplexed blocks.
  • the additional bits were added by the data generating section 2 to the data received from the upper layer.
  • the upper layer prepares all the data, which of course can selectively use the above-mentioned examples (B1), (B2) and (B3) of Fig. 1.
  • a second embodiment of the present invention is described as follows:
  • the inventor of the present invention proposed a construction of the spread spectrum communication system for transmitting information multiplexed according to a transfer format having a simplex (not multiplexed) section and multiplexed section (Japanese Patent Application No. 8-47118).
  • the proposed system is used for providing the compatibility of the communication system and can change the number of multiplexed signals as desired.
  • the transmitting and receiving terminals cannot receive transmitted data without knowing the number of multiplexed signals.
  • a simplex section has common information including the number of multiplexed signals, enabling the receiving terminal to selects the same multiplex number.
  • the transmitting terminal can transmit signals multiplexed in the selected number, while the receiving terminal can receive the signals, having aligned itself to the number of multiplexed signals. This enables the communication system to realize data communication in an optimal multiplex mode in accordance with the state of the communication channel.
  • Fig. 2 depicts a construction of data transmitted in a transfer format having a simplex section and a multiplex section, which is used in the communication system according to an aspect of the present invention.
  • a data structure (A) of Fig. 2 is used in the prior art system, wherein a simplex section (not multiplexed section) followed by a multiplex section contains common information necessary for bit synchronization, frame synchronization, the number of multiplexed signals and so on.
  • Additional bits are written in the place (B) of Fig. 2 so that the number of symbols in each of the multiplexed blocks can be an integer multiple of the number of the multiplexed blocks.
  • information about the start position of the effective bits is included in the various information section of the simplex section. Therefore, the data, from which the additional bits are previously removed according to the above information, is transferred to the upper layer 2. Consequently, the problem with an increased error rate in the packet, which the prior art involves, can be solved.
  • the example (C) of Fig. 2 includes additional bits are attached to the end of data written in the multiplexed section.
  • the last added part of data section does not need demodulation and the same data as is for the prior art can be restored by omitting the added part according to the known number of data included in the information data.
  • data transmitted and received in the transfer format having the simplex section and the multiplexed section can be treated and improved in the error rate and throughput of packets according to the present invention.
  • a third embodiment of the present invention is described as follows:
  • analog and digital circuits may have a certain unstable time after the transmission mode is switched from the simplex section to the multiplex section. This is because the clock is switched over to a multiple of the multiplex number and unstable state after switching operation and a change in amplitude of a signal causes an analog circuit to be transitionally unstable.
  • Fig. 3 is a conceptual view for explaining how the state of transmitting and receiving information changes when switching from a simplex section to a multiplex section.
  • Spread signals prepared in the simplex section are transferred successively one by one, while five spread signals prepared in parallel in the multiplex section are transmitted as multiplexed at a specific delay time.
  • signals [1] and [2] spread with a spreading code are transmitted in the shown order and a transmission mode is changed from the simplex to the multiplex.
  • Signals [3], [4], [5], [6] and [7] are first multiplexed and transmitted at a specific delay time, then signals [8], [9], [10], [11] and [12] are nest multiplexed and transmitted at a specific delay time.
  • the group of the signals [3], [4], [5], [6] and [7] relates to so called transitional section featured by coexistence of partly simplex sections and partly multiplex sections and is followed by the group of completely multiplexed signals.
  • the group of the completely multiplexed signals may also have a certain unstable section until digital and analog circuits become stable.
  • the unstable period of a digital system can be determined as several bits irrespective of a data rate.
  • the time required for stabilizing an analog circuit is generally determined as several microseconds plus a time constant of elements used therein. Therefore, the unstable period of the analog system cannot be of several bits and it depends upon a value determined by dividing a time constant by a transfer rate of the system. Consequently, the number of symbols in the unstable section (period) depends upon the related system and its data rate.
  • the embodiment of the present invention provides these sections with additional bits unrelated to data to be transmitted.
  • the number of additional bits is determined as a least value calculated for the analog system.
  • the number of bits can be round-up at the last part S (Fig. 3) between the unstable section and the stable section. It is of course possible to provide a longer protection period against the unstable section in consideration of dispersion of the analog system elements.
  • the necessary data can be transmitted always in a well-conditioned state assuring an improved error rate and a stable packet throughput.
  • the number of additional bits can be determined according to properties of a transmitter-receiver and a data rate. It is also possible to put an indication of the number of the added bits as multiplex information included in the simplex section.
  • a fourth embodiment of the present invention is described as follows:
  • the number of additional bits was determined on the basis of the time required for stabilizing the system.
  • the number of the bits is desirable to be an integer multiple of the number of multiplexed signals for the reason described before for the first and second embodiments. Accordingly, this embodiment provides a feature that the number of the additional bits corresponds to at least the time required for stabilizing the system and is also an integer multiple of the number of multiplexed signals.
  • the additional bits thus provided can simultaneously exert two kinds of advantageous effects described in all the above-mentioned embodiments.
  • Fig. 4 depicts a data format having a section of the specified number of additional bits, which is used in the embodiments of the present invention.
  • an additional bit section is placed between a simplex section and a multiplex section, and 1 ⁇ the number of the bits included in the additional bit section corresponds to a time longer than that required for stabilizing the operation of the system, i.e., the length of transitional section plus the unstable section as shown in Fig. 3 and 2 ⁇ the total number of added symbols (bits) and symbols in the multiplex section is an integer multiple of the number of multiplexed signals.
  • the data format thus defined can satisfy the above two conditions for additional bits and realize both effects of the additional bits.
  • a fifth embodiment of the present invention is described as follows:
  • the system has a simplex (not multiplex) section and a multiplex section.
  • the multiplex section has a transmission rate being a multiple of the multiplex number and an increased error rate as compared with the simplex section.
  • a 5-multiplex section may have a C/N (carrier to noise) ratio being worse by 7 dB than that of a simplex section.
  • the error correction is sometimes carried out to improve the error rate of the multiplexed section.
  • Probably the most effective method for error correction is error correction by using convolutional codes.
  • the convolutional code requires construction of transmit data from data stored in shift registers, causing the data to be uncertain until the data is accumulated in the shift registers. Normally, 1's are initially set in all the shift registers and data to be transmitted is subsequently input to the registers.
  • the same error correcting function is given to additional bits inserted between a simplex section and a multiplex section, which construction was realized by the embodiments described before.
  • Fig. 5 is a construction block diagram of an exemplified convolutional coding circuit.
  • a clock controller 7 controls the operation of a data generating section 4, a data forming section 5 and a convolutional coding section 6.
  • convolutional coding can be done at a length reduced to 1/2 or 3/4 as compared with the conventional example described above. Therefore, the data generating rate of the data generating section becomes a half of a transmission rate of the convolutionally coded data.
  • the clock controller 7 prepares a clock substantially twice the data clock to provide timings for inserting the additional bits.
  • the additional bits are given preprocessed data suitable for convolutional coding.
  • the additional bits e.g., seven 1's stored in shift registers, are convolutionally coded from the starting bit of the additional bit sequence.
  • the received convolutionally coded data including the additional bit section are demodulated.
  • the demodulated data sequence beginning from the starting position designated by an information bit is used as effective data.
  • the additional bits can thus serve as the preprocessed part of the convolutional coding.
  • the data sequence can be corrected for transmission error from the head to the tail end by appending several bits (e.g., 7 bits) to the data end.
  • the additional bits interposed between the simplex section and the multiplexed section can possess two above-mentioned functions, consequently realizing the effective transmission of the data.
  • the starting position of the effective data sequence is recognized from the information including in the simplex section, thereby the data sequence beginning from the designated data position is transferred to the upper layer.
  • a sixth embodiment of the present invention is as follows:
  • ARQ Automatic Repeat Request
  • FEC Forward Error Correction
  • CRC cyclic Redundancy Check
  • CRC may be applied to only the multiplexed section or both the simplex section and the multiplex section.
  • the CRC can be conducted only on the data sections without the additional bit section interposed between the simplex section and the multiplex section as described before for the third and fourth embodiments. This is because the additional bit section has a worse error rate.
  • the effective data section starting from the start bit position designated by information included in the simplex section is checked by calculating the bits of all the data length. Therefore, CRC is conducted on only the effective data sequence omitting the excessive additional bits and excluding the additional bits from the calculation, consequently realizing effective error detection and increasing the throughput of the system.
  • a seventh embodiment of the present invention is as follows:
  • the number of additional bits is such that a total of symbols is an integer multiple of the number of multiplexed signals.
  • the practical communication systems in many cases process information in a unit of 8-bits or 16-bits. Therefore, data is also formed of 8 bits or 16 bits.
  • the lengths of a packet and effective data contained in a simplex section may be generally represented in a byte unit (8 bits) and in a word unit (16 bits).
  • a total transmission length may differ from a multiple of 8 or 16 when the number of additional bits was determined as merely an integer multiple of the number of multiplexed signals and appended to the data. This may complicate processing of data and packets.
  • the seventh embodiment is therefore featured by appending additional bits whose quantity is a common multiple of the multiplexing number and 8. This ensures well-functioning of the additional bits maintaining the transmission length as a common multiple of 8 and 16 not to complicate the processing.
  • the least value is a least common multiple.
  • practical systems may achieve the same effect of the additional bits determined as any of the common multiples.
  • the transmission length can be now represented in a byte unit. This eliminates the need of calculation with a fraction, thus preventing the complication of the transmission processing.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
EP98905638A 1997-03-18 1998-02-25 Direktes spreizspektrum nachrichtenübertragungsystem entsprechend verzögertem multiplex modus, und nachrichtenübertragungsverfahren dieses system verwendend Withdrawn EP0987849A4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP6502697 1997-03-18
JP9065026A JPH10262029A (ja) 1997-03-18 1997-03-18 遅延多重方式対応スペクトル直接拡散通信システム及び該システムを用いる通信方法
PCT/JP1998/000757 WO1998042094A1 (fr) 1997-03-18 1998-02-25 Systeme de communication directe a spectre disperse correspondant au mode multiplex temporise, et procede de communication utilisant le systeme

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EP0987849A1 true EP0987849A1 (de) 2000-03-22
EP0987849A4 EP0987849A4 (de) 2007-04-25

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US (1) US6501786B1 (de)
EP (1) EP0987849A4 (de)
JP (1) JPH10262029A (de)
AU (1) AU6115698A (de)
WO (1) WO1998042094A1 (de)

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US6859487B1 (en) * 1999-03-03 2005-02-22 Nec Corporation Radio communication system and base station and mobile terminal to be employed therein

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EP0987849A4 (de) 2007-04-25
US6501786B1 (en) 2002-12-31
AU6115698A (en) 1998-10-12
JPH10262029A (ja) 1998-09-29
WO1998042094A1 (fr) 1998-09-24

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