EP0987742A3 - Méthode de formation d'une région dopée par diffusion - Google Patents
Méthode de formation d'une région dopée par diffusion Download PDFInfo
- Publication number
- EP0987742A3 EP0987742A3 EP99118448A EP99118448A EP0987742A3 EP 0987742 A3 EP0987742 A3 EP 0987742A3 EP 99118448 A EP99118448 A EP 99118448A EP 99118448 A EP99118448 A EP 99118448A EP 0987742 A3 EP0987742 A3 EP 0987742A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- zwischenschicht
- intermediate layer
- der
- halbleiterschicht
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 abstract 8
- 239000000758 substrate Substances 0.000 abstract 4
- 239000002019 doping agent Substances 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000005496 tempering Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
- H01L21/2256—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides through the applied layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19842882A DE19842882A1 (de) | 1998-09-18 | 1998-09-18 | Verfahren zum Herstellen eines Dotierungsgebiets |
DE19842882 | 1998-09-18 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0987742A2 EP0987742A2 (fr) | 2000-03-22 |
EP0987742A3 true EP0987742A3 (fr) | 2004-03-03 |
EP0987742B1 EP0987742B1 (fr) | 2007-05-30 |
Family
ID=7881457
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP99118448A Expired - Lifetime EP0987742B1 (fr) | 1998-09-18 | 1999-09-17 | Méthode de formation d'une région dopée par diffusion dans une structure de mémoire |
Country Status (3)
Country | Link |
---|---|
US (1) | US6133126A (fr) |
EP (1) | EP0987742B1 (fr) |
DE (2) | DE19842882A1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6500723B1 (en) | 2001-10-05 | 2002-12-31 | Motorola, Inc. | Method for forming a well under isolation and structure thereof |
US8351236B2 (en) | 2009-04-08 | 2013-01-08 | Sandisk 3D Llc | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture |
KR20110012948A (ko) * | 2009-07-31 | 2011-02-09 | 주식회사 하이닉스반도체 | 반도체장치의 도핑방법 |
US20110297912A1 (en) * | 2010-06-08 | 2011-12-08 | George Samachisa | Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof |
RU2597647C2 (ru) * | 2014-12-15 | 2016-09-20 | Акционерное общество "Рязанский завод металлокерамических приборов" (АО "РЗМКП") | Способ легирования полупроводниковых пластин |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5279976A (en) * | 1991-05-03 | 1994-01-18 | Motorola, Inc. | Method for fabricating a semiconductor device having a shallow doped region |
US5416343A (en) * | 1992-11-20 | 1995-05-16 | U.S. Philips Corporation | Semiconductor device provided with a number of programmable elements |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5242858A (en) * | 1990-09-07 | 1993-09-07 | Canon Kabushiki Kaisha | Process for preparing semiconductor device by use of a flattening agent and diffusion |
DE4113044A1 (de) * | 1990-10-09 | 1992-05-21 | Degussa | Zahnpflegemittel |
FR2729008B1 (fr) * | 1994-12-30 | 1997-03-21 | Sgs Thomson Microelectronics | Circuit integre de puissance |
-
1998
- 1998-09-18 DE DE19842882A patent/DE19842882A1/de not_active Withdrawn
-
1999
- 1999-09-17 EP EP99118448A patent/EP0987742B1/fr not_active Expired - Lifetime
- 1999-09-17 DE DE59914356T patent/DE59914356D1/de not_active Expired - Lifetime
- 1999-09-20 US US09/398,688 patent/US6133126A/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5279976A (en) * | 1991-05-03 | 1994-01-18 | Motorola, Inc. | Method for fabricating a semiconductor device having a shallow doped region |
US5416343A (en) * | 1992-11-20 | 1995-05-16 | U.S. Philips Corporation | Semiconductor device provided with a number of programmable elements |
Non-Patent Citations (1)
Title |
---|
WU S L ET AL: "IMPROVEMENT OF ELECTRICAL CHARACTERISTICS OF POLYCRYSTALLINE SILICON-CONTACTED DIODES AFTER FORWARD BIAS STRESSING", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 57, no. 18, 29 October 1990 (1990-10-29), pages 1904 - 1906, XP000172654, ISSN: 0003-6951 * |
Also Published As
Publication number | Publication date |
---|---|
DE59914356D1 (de) | 2007-07-12 |
EP0987742B1 (fr) | 2007-05-30 |
DE19842882A1 (de) | 2000-03-30 |
US6133126A (en) | 2000-10-17 |
EP0987742A2 (fr) | 2000-03-22 |
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