Classifications

• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
  • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
• • H—ELECTRICITY
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  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
  • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
  • H01L29/0692—Surface layout
  • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
  • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66234—Bipolar junction transistors [BJT]
  • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
  • H01L29/66333—Vertical insulated gate bipolar transistors
  • H01L29/6634—Vertical insulated gate bipolar transistors with a recess formed by etching in the source/emitter contact region
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/70—Bipolar devices
  • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
  • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
  • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
  • H01L29/7395—Vertical transistors, e.g. vertical IGBT
  • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L29/41725—Source or drain electrodes for field effect devices
  • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
  • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
  • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Definitions

• This invention relates to power semiconductor devices comprising a multiple-cellular insulated-gate field-effect transistor structure, for example MOSFETs (insulated-gate unipolar transistors) or IGBTs (insulated-gate bipolar transistors), or MOS-gated thyristors.
• MOSFETs insulated-gate unipolar transistors
• IGBTs insulated-gate bipolar transistors
• MOS-gated thyristors MOS-gated thyristors.
• the invention also relates to methods of manufacturing such power devices.
• Power semiconductor devices comprising a multiple-cellular insulated-gate field-effect transistor structure with each cell present at a corresponding opening in a mesh-shaped gate electrode, wherein the gate electrode extends on a gate insulating layer over channel areas of a transistor- body region of one conductivity type in each cell for gating a conduction channel of the opposite conductivity type in the channel area in operation of the device.
• Published European Patent Application EP-A-0 717449 discloses such a power semiconductor device in which the cells and the openings in the gate electrode are of elongate shape having longitudinal sides at which the channel areas are present under the gate insulating layer under longitudinal parts of the gate electrode.
• a power semiconductor device comprising a multiple-cellular insulated-gate field- effect transistor structure with each cell present at a corresponding opening in a mesh-shaped gate electrode, wherein the gate electrode extends on a gate insulating layer over channel areas of a transistor-body region of one conductivity type in each cell for gating a conduction channel of the opposite conductivity type in the channel area in operation of the device, and wherein the cells and the openings in the gate electrode are of elongate shape having longitudinal sides at which the channel areas are present under the gate insulating layer under longitudinal parts of the gate electrode, characterised in that the channel areas are absent at ends of the elongate cells.
• the design and manufacture of such a device in accordance with the present invention adopts an opposite approach to that of EP-A-0 717 449, in that no channel areas are provided at the ends of the elongate cells (instead of joining together channel areas as in EP-A-0 717449).
• the absence of the channel areas from the ends of the elongate cells can be achieved using one or more of a variety of doping, insulation and/or layout techniques.
• the techniques used may be an appropriate gate-electrode layout pattern, and/or an appropriate source-region layout pattern, and/or inclusion of a thicker insulating layer than the gate insulating layer, and/or inclusion of a more highly doped region in the transistor- body region.
• the gate electrode may be absent from the ends of the elongate cells.
• the longitudinal parts of the gate electrode can be interconnected beyond the ends of the elongate cells by interconnection parts of the gate electrode which can serve to reduce the electrical resistance of the whole gate electrode of the device.
• These interconnection parts can be located on a thicker insulating layer than the gate insulating layer, the thicker insulating layer being present between facing ends of the neighbouring elongate cells where the channel areas are absent.
• This thicker insulating layer may be present only at the ends of the elongate cells where the channel areas are absent. However, it may also extend as thick insulator stripes which are located in-between the longitudinal sides of neighbouring elongate cells.
• thick insulator stripes may be present under a central elongate area of the longitudinal parts of the gate electrode where the gate electrode overlies a semiconductor region of opposite conductivity type between the transistor-body regions of neighbouring cells.
• the thick insulating layer itself may be mesh-shaped and may serve to reduce capacitance between the gate electrode and the semiconductor region of opposite conductivity type between the neighbouring cells.
• a more highly-doped region of the same conductivity type as the transistor-body regions may be present at each end of the elongate cells and may over-dope the transistor-body regions at these ends to terminate the ends of the elongate cells without channel areas at these ends.
• This highly doped region may be formed simply as an extension of a highly-doped region provided already in the cells using existing manufacturing processes.
• step (d) carrying out a doping step into the semiconductor body portion where the cells are to be formed so as to provide each cell with the transistor- body regions, wherein the lateral extent of the transistor-body regions is defined by the mesh pattern of step (c) along the longitudinal sides of the elongate cells and is defined by an edge portion of the thicker insulating layer at each end of the elongate cells, which edge portion of the thicker insulating layer is present within the openings in the mesh-shaped gate electrode so as to avoid the formation of the transistor-body regions under the interconnection parts of the gate electrode at the ends of these openings.
• the step (d) may include carrying out two doping steps into the semiconductor body portion where the cells are to be formed, the two doping steps being with dopant of the same conductivity type but with a higher doping concentration for one of the two doping steps so as to provide each cell also with a more highly-doped region of the same conductivity type as the transistor- body regions.
• the provision of a more highly doped region of the same conductivity type as the transistor-body regions is already part of existing manufacturing processes.
• the lateral extent of this more highly doped region may be defined by a mesh pattern of step (c) along the longitudinal sides of the cells and by the edge portion of the thicker insulating layer at each end of the elongate cells.
• the elongate openings formed in this electrode may be wider than the openings in the etchant mask.
• the doping step (d) may comprise a first doping step for providing the more highly doped region and second doping step for providing the transistor-body regions.
• the lateral extent of the more highly doped region may be defined both by masking with the mesh pattern of the etchant mask and with the edge portion of the thicker insulating layer as in step (d) and by subsequent lateral diffusion in the body portion.
• This lateral diffusion of the more highly doped region may be sufficient to extend the more highly doped region to beneath the edge portion of the thicker insulating layer, while over-doping the transistor-body regions at the ends of the elongate cells so terminating the ends of the elongate cells without channel areas.
• Figure 1 is a plan view of part of the layout of a multiple-cellular insulated- gate field-effect transistor structure in a power semiconductor device in accordance with the present invention
• Figure 2 is an enlarged plan view of the opposite end portions of one of the elongate cells (showing also its semiconductor body regions) of the transistor structure of Figure 1 ;
• Figure 3A is a cross-sectional view on the line A-A of Figure 2;
• Figure 3B is a cross-sectional view of the opposite ends of the elongate cell on the line B-B of Figure 2;
• Figure 4 is a plan view of a modification of the layout of the transistor structure of Figure 1 , illustrating a second embodiment in accordance with the present invention
• Figures 5A and 5B are respective modifications of the cross-sectional views of Figures 3A and 3B, illustrating further modifications in the second embodiment in accordance with the present invention
• Figures 6 to 8 are cross-sectional views of the semiconductor device parts of Figures 3A and 3B, at stages during their manufacture by a method in accordance with the present invention.
• Figures 9A and 9B are modifications of the device structure of Figures 5A and 5B, at a stage of manufacture by a modified method also in accordance with the present invention.
• the power semiconductor device of Figures 1 to 3 comprises a multiple- cellular insulated-gate field-effect transistor structure with each cell 100 present at a corresponding opening 110 in a mesh-shaped gate electrode 11.
• the gate electrode 11 extends on a gate insulating layer 12 over surface areas (which provide channel areas 1) of a transistor-body region 2 of one conductivity type (p-type in the example of Figures 3A and 3B) in each cell 100.
• the gate electrode 11 serves for gating a conduction channel of the opposite conductivity type (n-type in the specific example) in the channel area 1 in operation of the device.
• the device is of the n-channel enhancement type, in which an n-type conduction channel is induced in the p-type transistor body 2 by the overlying insulated gate electrode 11.
• the conduction channel is of charge carriers of said opposite conductivity type (i.e electrons in the specific example) from a source region 4 of the transistor structure.
• the transistor-body regions 2 are provided in a drain drift region 8 of opposite conductivity type (n-type in the specific example) which extends between the transistor-body regions 2 of neighbouring cells 100 to the upper surface of the semiconductor body 10.
• the cells 100 and the openings 110 in the gate electrode 11 are of elongate shape having longitudinal sides X at which the channel areas 1 are present under the gate insulating layer 12 under longitudinal parts 11x of the gate electrode 11.
• the channel areas 1 are absent at the ends Z of the elongate cells 100.
• these interconnection parts 11z are located on a thicker insulating layer 13 than the gate insulating layer 12.
• the thicker insulating layer 13 is present between facing ends Z of neighbouring elongate cells 100 where the channel areas 1 are absent.
• a more highly doped region 3 (see Figure 3B) of the same conductivity type as the transistor-body regions 2 is present at each end Z of the elongate cells 100 and over-dopes the transistor- body regions 2 at these ends so as to terminate the ends Z of the elongate cells 100 without channel areas 1 at these ends Z.
• the conduction channel is unable to be formed at the ends Z of the elongate cells 100 because of (a) the higher doping of the region 3, and (b) the increased thickness of the insulating layer 13, and (c) the cut-back of the interconnection part 11z of the gate electrode 11 from the ends Z.
• the interconnection parts 11z overlie the thick insulating layer 13 on the highly doped regions 3 and intermediate drift region 8 (instead of over the gate dielectric 12 on the transistor-body regions 2).
• the interconnection parts 11c of the gate electrode 11 are unable to induce a conduction channel in the transistor-body region 2 from the source region 4.
• the source region 4 is therefore inactive (not active) at the ends Z of the elongate cells 100.
• the semiconductor body of the device of Figures 1 to 3 typically comprises a highly doped monocrystalline silicon substrate 9 having thereon a lowly doped n-conductivity type silicon epitaxial layer forming the drain drift region 8.
• the power semiconductor device is of vertical configuration and comprises a very large number (hundreds of thousands) of parallel-connected elongate cells which share a common drain drift region 8.
• the substrate 9 is of the same conductivity type as the drain drift region 8 and is contacted at its bottom major surface by a drain electrode 31.
• the substrate 9 is of opposite conductivity type and is contacted by an anode electrode 31 at its bottom major surface.
• Each elongate cell 100 may have the highly doped region 3 extending the length of the cell in addition to being present at both ends Z of the elongate cell 100 to terminate these ends.
• the region 3 may extend between the transistor-body regions 2 which are present at the longitudinal sides X of the cell 100.
• the region 3 extends to the body surface at apertures and/or discontinuities in the source region 4.
• This electrode 34 is a source electrode of the MOSFET device or a cathode electrode of the IGBT device.
• the multiple cells 100 of the device are connected in parallel between these electrodes 31 and 34 at the opposite major surfaces of the body 8,9.
• the area of the thick insulator 13 is hatched in one direction; the area of the gate electrode 11 is hatched in the opposite direction in Figure 1 (and Figure 4) but is unhatched in Figure 2; a dotted line ( • • • ) is used for the outline of the highly doped region 3 in Figure 2; a broken line ( ) is used for the outline of the source region 4 in Figure 2; and a chain-dot line ( - • - • - ) is used for the outline of the transistor-body regions 2 in Figure 2.
• the source region 4 overdopes the region 3 where it overlies the region 3 at the body surface.
• the transistor-body regions 2 are overdoped with the highly doped region 3 as illustrated in Figure 2.
• the contact window in the insulating layer 22 is not shown in Figure 2.
• the Figure 3B cross-section on the line B-B of Figure 2 does not extend the full length of Figure 2, but Figure 3B shows only the ends of the cell 100 as far as the first contact of the electrode 34 with both regions 3 and 4.
• FIG. 6A, 7A and 8A are for the device section of Figure 3A, whereas that in Figures 6B, 7B and 8B are for the device section of Figure 3B.
• the semiconductor body portion which provides the drain drift region 8 is an n-type silicon epitaxial layer 8' doped with, for example, less than 9 x 10 14 phosphorous cm "3 .
• the doping level depends on the desired blocking voltage of the device and may be about 2 x 10 14 cm "3 for a 600 volt device.
• the device structure of Figures 6A and 6B is obtained by the steps of:
• the thickness of the gate insulating layer 12 is less than 0.3 ⁇ m (micrometre), for example about 80nm (nanometre), whereas the thickness of the layer 13 is typically in excess of 1 ⁇ m.
• the layer providing the gate electrode 11 may typically have a thickness in the range of, for example, 0.5 ⁇ m to 1 ⁇ m.
• the etchant mask 41 shown in Figures 6A and 6B may be typically of photoresist having a thickness of, for example 2 ⁇ m. An isotropic dry etch may be used to etch the gate-electrode material at the openings 40 in the photoresist mask 41. As a result of undercutting the mask 41 , the openings 110 in the gate electrode 11 are wider than the openings 40 in the etchant mask 41.
• the width of the windows 40 in the photoresist mask 41 may be, for example, 11 ⁇ m, whereas the width of the openings 110 in the gate electrode 11 may be, for example, 15 ⁇ m.
• These openings 40,110 are elongate, and in a specific embodiment the length of the longitudinal sides X may be, for example, typically an order of magnitude greater than the width of these openings.
• the openings 110 in the gate electrode 11 may have a width of about 15 ⁇ m and a length of about 210 ⁇ m.
• the longitudinal side of the openings 110 are present where the channel areas 1 of the device are to be provided.
• the longitudinal parts 11x of the gate electrode 11 between the openings 110 are present on the gate insulating layer 12.
• the interconnection parts 11z of the gate electrode 11 are present on the thicker insulating layer 13.
• the openings 40 and 110 expose end portions of the thick insulating layer 13, as illustrated in Figure 6B.
• a first doping step is carried out before the removal of the etchant mask 40.
• this doping step comprises the implantation of dopant ions, for example of boron, into the epitaxial layer 8' where the device cells 100 are to be formed.
• This ion implantation serves to provide each cell 100 with the doping for its region 3.
• the boron ion dose for the regions 3 is, for example, in the range of 5 x 10 14 cm "2 to 2 x 10 15 cm 2 .
• the photoresist mask 41 and the thick insulating layer 13 each have a thickness sufficient to mask the underlying semiconductor body portion 8' against implantation of the boron ions 53.
• the lateral extent of the regions 3 as initially implanted is defined by the mesh pattern of the photoresist mask 41 along the longitudinal sides X of the elongate cells 100 as illustrated in Figure 6A and is defined by an edge portion of the thick insulating layer 13 at each end Z of the elongate cells 100 as illustrated in Figure 6B.
• the implanted dopant 53 in the layer 8' is annealed by heating the body 8,9 to 1100°C. This heating treatment causes some diffusion (including lateral diffusion) of the dopant 53 so that the resulting region 3 extends beneath the edge of the thick insulating layer 13 at the ends Z of the cells 100, as illustrated in Figure 7B.
• a second doping step is carried out for providing the transistor-body regions 2.
• This doping step also comprises the implantation of boron ions 52.
• the boron ion dose in this case may be in the range of, for example, 3 x 10 13 to 5 x 10 14 cm ⁇ 2 .
• the lateral extent of the implant is defined by the sides of the gate electrode 11 along the longitudinal sides X of the elongate cells 100 as illustrated in Figure 7A and is defined by the edge portion of the thick insulating layer 13 at each end Z of the elongate cells 100 as illustrated in Figure 7B.
• the same implantation window may be used for dopant ions 54 of the opposite conductivity type for forming source regions 4 with the transistor-body regions 2.
• the implants 52 and 54 are annealed by heating the body structure to 900°C.
• This heating treatment causes some diffusion (including lateral diffusion) of the implanted dopant 52 and 54 (and also the dopant 53 of region 3) so that the resulting transistor-body region 2 extends beneath the edge of the gate electrode 11 to form the channel areas 1 along the longitudinal sides X (see Figure 8A), between the resulting source region 4 and the drain drift region 8.
• Some diffusion also occurs beneath the edge of the thick insulating layer 13 at the ends Z of the cells 100 (see Figure 8B), but in this area the transistor-body region 2 is overdoped by the higher-doped region 3 which already extends beneath the edge of the thick insulating layer 13 at the ends Z of the cells 100.
• the implanted source region 4 is of a higher doping concentration than the highly doped region 3 and so is not overdoped by the region 3.
• Figures 8A and 8B illustrate a subsequent stage in the manufacture in which selected areas of the source region 4 are removed to permit the source electrode 34 to contact both the source region 4 and the highly doped region 3 at the semiconductor body surface.
• this removal is effected using an etchant mask 44 of, for example, photoresist.
• the photoresist mask 44 is provided on an insulating layer 22 (for example of silicon dioxide) over the device structure.
• the selected areas of the source region 4 and overlying areas of the insulating layers 12 and 22 can be removed at the windows 45 in the photoresist mask 44 using an anisotropic etching treatment (for example plasma etching).
• the insulating layers 12 and 22 may be cut back at the windows 45 using a wet isotropic etch so as to expose surface areas of the source regions 4.
• metallisation such as aluminium can be deposited to form the electrode 34.
• the thicker insulating layer 11 is in the form of a stripe which extends only at and between facing ends Z of neighbouring elongate cells 100.
• Figures 4, 5A and 5B illustrate a modification in which the thick insulating layer 13 is mesh-shaped in comprising further stripes 13x which are located in-between the longitudinal sides X of neighbouring elongate cells 100.
• These thick insulator stripes 13x are present under a central elongate area of the longitudinal parts 11x of the gate electrode 11 where the gate electrode 11 overlies the drain drift region 8.
• a lower gate-drain capacitance can be achieved by the inclusion of these stripes 13x.
• Figures 5A and 5B also illustrate a further modification in which the source region 4 of each cell is absent from the ends Z of the cell.
• the inactive parts of the source region 4 of the Figure 1 device at the ends Z may be omitted.
• the resulting source region 4, as in Figures 5A and 5B, may be in the form of two parallel stripe portions 4a and 4b which are parallel to the longitudinal sides X of the elongate cell 100. These stripe portions 4A and 4B terminate short of the ends Z, as illustrated in Figure 5B.
• the highly doped region 3 extends to the body surface at the ends Z and also in-between the stripe portions 4a and 4b.
• the stripe portions 4A and 4B may be wholly separated from each other, or they may be joined to each other at intermediate positions along the elongate cell 100 by cross-portions 4c, as illustrated in Figure 4.
• a masking pattern 46 (of, for example, photoresist) may be used to define the lateral extent of the source region 4, instead of using the etchant mask 44.
• the doping concentration for the source region 4 may be provided by implantation of dopant ions 54 at an implantation window which is defined by the gate electrode 11 along the longitudinal sides X of the cells 100 and by the additional mask 46 at the ends Z of the cells 100 and at intermediate positions along the cells 100.
• the additional (photoresist) masking pattern 46 extends into the window in the thick insulating layer 13 at the ends Z of the cells 100.
• the edge of the thick insulating layer 13 at the ends Z may be used to mask the region 3 at the ends Z against implantation of the dopant ions 54 so as to prevent formation of the source region at the ends Z of the cells 100.
• Figures 1 to 9 have been described in terms of a MOSFET device or an IGBT device.
• the present invention may be used with a MOS-gated thyristor device having its channel regions 1 absent from the ends Z of elongate cells 100.
• n-channel devices have been described, the present invention may (of course) be applied to p-channel devices, in which the conductivity types of the various regions 2, 3, 4, 8 and 9 are reversed.

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• 1997
  • 1997-12-19 GB GBGB9726829.6A patent/GB9726829D0/en not_active Ceased
• 1998
  • 1998-12-14 EP EP98957086A patent/EP0970526A2/de not_active Withdrawn
  • 1998-12-14 JP JP53353299A patent/JP2001512629A/ja active Pending
  • 1998-12-14 WO PCT/IB1998/002027 patent/WO1999033119A2/en not_active Application Discontinuation

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