EP0968591A1 - Fernmeldevermittlungssystem - Google Patents

Fernmeldevermittlungssystem

Info

Publication number
EP0968591A1
EP0968591A1 EP98909672A EP98909672A EP0968591A1 EP 0968591 A1 EP0968591 A1 EP 0968591A1 EP 98909672 A EP98909672 A EP 98909672A EP 98909672 A EP98909672 A EP 98909672A EP 0968591 A1 EP0968591 A1 EP 0968591A1
Authority
EP
European Patent Office
Prior art keywords
stage
destination
source
index
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98909672A
Other languages
English (en)
French (fr)
Inventor
Roderick Peter Webb
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
British Telecommunications PLC
Original Assignee
British Telecommunications PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Telecommunications PLC filed Critical British Telecommunications PLC
Priority to EP98909672A priority Critical patent/EP0968591A1/de
Publication of EP0968591A1 publication Critical patent/EP0968591A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1507—Distribute and route fabrics, e.g. sorting-routing or Batcher-Banyan
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3018—Input queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/356—Switches specially adapted for specific applications for storage area networks
    • H04L49/357—Fibre channel switches

Definitions

  • a switch can permute the inputs in any order then the switch is known as non- blocking, otherwise it is known as blocking.
  • Two or more of the routes through a self-routing switch may overlap causing internal blocking.
  • Prevention of internal blocking may be achieved either by sorting the packets so they start at different inputs, or by bypassing blocked packets, transmitting non-blocked packets which arrive at the switch after the blocked packets.
  • the control means may be connected to receive destination addresses from packets stored in the buffer, to select packets which can be transmitted through the switching device without mutual blocking, and to release the selected packets from the buffers,
  • Figure 1 shows a general form of an electrical neural network
  • Figure 9 shows a Banyan exchange with bit reversal
  • Figure 10 shows paths blocked for various source and bit-reversed destination line addresses
  • the source and destination lines may correspond to the first and second co-ordinate directions of the two dimensional array of neurons depending on the source indices and destination indices which are allocated to the element inputs and outputs.
  • Figure 1 3 represents one possible way of allocating each element input with source indices and each element output with destination indices for a three stage Banyan network.
  • the source and destination lines are labelled with the letters A to H and I to J respectively to avoid confusion between the source and destination lines and binary numbers which are used to address them.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
EP98909672A 1997-03-19 1998-03-18 Fernmeldevermittlungssystem Withdrawn EP0968591A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP98909672A EP0968591A1 (de) 1997-03-19 1998-03-18 Fernmeldevermittlungssystem

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP97301842 1997-03-19
EP97301842 1997-03-19
PCT/GB1998/000820 WO1998042105A1 (en) 1997-03-19 1998-03-18 Telecommunications switch
EP98909672A EP0968591A1 (de) 1997-03-19 1998-03-18 Fernmeldevermittlungssystem

Publications (1)

Publication Number Publication Date
EP0968591A1 true EP0968591A1 (de) 2000-01-05

Family

ID=26147346

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98909672A Withdrawn EP0968591A1 (de) 1997-03-19 1998-03-18 Fernmeldevermittlungssystem

Country Status (2)

Country Link
EP (1) EP0968591A1 (de)
WO (1) WO1998042105A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19961269A1 (de) * 1999-12-18 2001-06-21 Alcatel Sa Netzwerkknoten zum Vermitteln von digitalen Informationen unterschiedlicher Protokolltypen

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU6734390A (en) * 1989-11-20 1991-06-13 British Telecommunications Public Limited Company Neural networks

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9842105A1 *

Also Published As

Publication number Publication date
WO1998042105A1 (en) 1998-09-24

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Legal Events

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