EP0968591A1 - Commutateur de telecommunication - Google Patents

Commutateur de telecommunication

Info

Publication number
EP0968591A1
EP0968591A1 EP98909672A EP98909672A EP0968591A1 EP 0968591 A1 EP0968591 A1 EP 0968591A1 EP 98909672 A EP98909672 A EP 98909672A EP 98909672 A EP98909672 A EP 98909672A EP 0968591 A1 EP0968591 A1 EP 0968591A1
Authority
EP
European Patent Office
Prior art keywords
stage
destination
source
index
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98909672A
Other languages
German (de)
English (en)
Inventor
Roderick Peter Webb
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
British Telecommunications PLC
Original Assignee
British Telecommunications PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Telecommunications PLC filed Critical British Telecommunications PLC
Priority to EP98909672A priority Critical patent/EP0968591A1/fr
Publication of EP0968591A1 publication Critical patent/EP0968591A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding in a switch fabric
    • H04L49/253Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254Centralised controller, i.e. arbitration or scheduling
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Packet switching elements characterised by the switching fabric construction
    • H04L49/101Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/15Interconnection of switching modules
    • H04L49/1507Distribute and route fabrics, e.g. sorting-routing or Batcher-Banyan
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • H04L49/3018Input queuing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/35Switches specially adapted for specific applications
    • H04L49/356Switches specially adapted for specific applications for storage area networks
    • H04L49/357Fibre channel switches

Definitions

  • a switch can permute the inputs in any order then the switch is known as non- blocking, otherwise it is known as blocking.
  • Two or more of the routes through a self-routing switch may overlap causing internal blocking.
  • Prevention of internal blocking may be achieved either by sorting the packets so they start at different inputs, or by bypassing blocked packets, transmitting non-blocked packets which arrive at the switch after the blocked packets.
  • the control means may be connected to receive destination addresses from packets stored in the buffer, to select packets which can be transmitted through the switching device without mutual blocking, and to release the selected packets from the buffers,
  • Figure 1 shows a general form of an electrical neural network
  • Figure 9 shows a Banyan exchange with bit reversal
  • Figure 10 shows paths blocked for various source and bit-reversed destination line addresses
  • the source and destination lines may correspond to the first and second co-ordinate directions of the two dimensional array of neurons depending on the source indices and destination indices which are allocated to the element inputs and outputs.
  • Figure 1 3 represents one possible way of allocating each element input with source indices and each element output with destination indices for a three stage Banyan network.
  • the source and destination lines are labelled with the letters A to H and I to J respectively to avoid confusion between the source and destination lines and binary numbers which are used to address them.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

Un commutateur à acheminement automatique, tel qu'un commutateur de Banyan, comporte un contrôleur qui reconnaît les demandes d'acheminement entrantes susceptibles de provoquer un blocage dans le commutateur et fait une sélection optimale des demandes en attente pouvant être traitées sans blocage. Le contrôleur est constitué d'un réseau de neurones optique comprenant un ensemble de sources lumineuses (14) qui illuminent un ensemble de photodétecteurs (26) au travers d'un masque (15), chaque traversée possible du commutateur comportant un élément de l'ensemble de sources lumineuses (20) et un élément photodétecteur (27). L'attribution des chemins menant aux emplacements des ensembles est tel que, pour le chemin correspondant à n'importe quel élément de l'ensemble de sources lumineuses, les positions de l'élément de l'ensemble photodétecteur correspondant aux chemins bloqués forment un motif qui est une version décalée du motif formé par les éléments de l'ensemble photodétecteur correspondant aux chemins bloqués par un trajet correspondant à n'importe quel élément de l'ensemble de sources lumineuses, ce qui permet d'utiliser un seul masque.
EP98909672A 1997-03-19 1998-03-18 Commutateur de telecommunication Withdrawn EP0968591A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP98909672A EP0968591A1 (fr) 1997-03-19 1998-03-18 Commutateur de telecommunication

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP97301842 1997-03-19
EP97301842 1997-03-19
PCT/GB1998/000820 WO1998042105A1 (fr) 1997-03-19 1998-03-18 Commutateur de telecommunication
EP98909672A EP0968591A1 (fr) 1997-03-19 1998-03-18 Commutateur de telecommunication

Publications (1)

Publication Number Publication Date
EP0968591A1 true EP0968591A1 (fr) 2000-01-05

Family

ID=26147346

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98909672A Withdrawn EP0968591A1 (fr) 1997-03-19 1998-03-18 Commutateur de telecommunication

Country Status (2)

Country Link
EP (1) EP0968591A1 (fr)
WO (1) WO1998042105A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19961269A1 (de) * 1999-12-18 2001-06-21 Alcatel Sa Netzwerkknoten zum Vermitteln von digitalen Informationen unterschiedlicher Protokolltypen

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5428466A (en) * 1989-11-10 1995-06-27 British Telecommunications Public Limited Company Neural networks

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9842105A1 *

Also Published As

Publication number Publication date
WO1998042105A1 (fr) 1998-09-24

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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