EP0961261A1 - Verfahren und Schaltung zur automatischen Phasen- und Frequenzeinstellung von einem rückgewonnenen Takt in einer digitalen Bildanzeigevorrichtung - Google Patents

Verfahren und Schaltung zur automatischen Phasen- und Frequenzeinstellung von einem rückgewonnenen Takt in einer digitalen Bildanzeigevorrichtung Download PDF

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Publication number
EP0961261A1
EP0961261A1 EP99107443A EP99107443A EP0961261A1 EP 0961261 A1 EP0961261 A1 EP 0961261A1 EP 99107443 A EP99107443 A EP 99107443A EP 99107443 A EP99107443 A EP 99107443A EP 0961261 A1 EP0961261 A1 EP 0961261A1
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EP
European Patent Office
Prior art keywords
image
horizontal
clock
coordinates
termination
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Withdrawn
Application number
EP99107443A
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English (en)
French (fr)
Inventor
Osamu Sameshima
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of EP0961261A1 publication Critical patent/EP0961261A1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery

Definitions

  • the present invention relates to a digital image display apparatus for converting an analog video signal outputted from a personal computer or other video signal source into a digital image signal, and in the conversion automatically adjusting the clock frequency, phase timing and display position of the video signal to realize preferable display quality.
  • the inputted analog video signal is distinguished with respect to its number of displaying pixel and refresh rate according to its horizontal and vertical synchronization frequencies, and then converted into a digital image signal based on a standard display parameter (preset data) previously held in a storage.
  • the digital image display apparatus thus displays a video image based on the digital image signal generated in the above manner.
  • Analog video signals outputted from personal computers are not completely standardized. Therefore, output timing of the analog video signals are often different from a standard timing in individual personal computers as well as among various kinds of personal computers.
  • FIG. 5 shown as one of means for solving the above problems is a digital image display apparatus with an automatic adjusting function proposed in U.S. Patent Application Serial No. 08/847,593 filed on April 24, 1997 and assigned to the same assignee of the preset application.
  • a digital image display DD includes a video adapter VA, an image display driving circuit 10, and an image display 11.
  • the video adapter VA is connected to a personal computer (not shown in the drawing), to generate a digital image signal Sid and display control data Sdc based on an analog image signal Sia supplied from the personal computer.
  • the image display driving circuit 10 is connected to the video adapter VA, to generate a digital image driving signal SD for driving the image display portion 11 based on the digital image signal Sid and the display control data Sdc supplied from the video adapter VA.
  • the image display portion 11 is connected to the image display driving circuit 10 and driven by the digital signal SD, to display images.
  • the video adapter VA has an A/D converter 1, a clock generation circuit 2, an image start/termination coordinate detection circuit 3, a display control circuit 4, and a delay circuit 5.
  • the A/D converter 1, the image start/termination coordinate detection circuit 3 and the delay circuit 5 are respectively connected to the personal computer, to receive an analog image signal Sia, a vertical synchronizing signal Vsync, and a horizontal synchronizing signal Hsync from the personal computer, respectively.
  • the analog image signal Sia, the vertical synchronizing signal Vsync, and the horizontal synchronizing signal Hsync constitute the analog video signal.
  • the delay circuit 5 delays the horizontal synchronizing signal Hsync by a predetermined period Ts based on phase data Sp supplied from the display control circuit 4, thereby generates a delayed horizontal synchronizing signal Shs and supplies it to the clock generation circuit 2.
  • the clock generation circuit 2 generates a clock Sc which is phase-synchronized with the delayed horizontal synchronizing signal Shs and is having a frequency corresponding to clock count data Scd supplied from the display control circuit 4, and supplies the clock Sc to the A/D converter 1 and the image start/termination coordinate detection circuit 3.
  • the A/D converter 1 converts the analog image signal Sia into a digital signal based on the clock Sc, to generate a digital iamge signal Sid and to output it to the image start/termination coordinate detection circuit 3 and image display driving circuit 10.
  • the image start/termination coordinate detection circuit 3 detects start coordinates and termination coordinates in the horizontal and vertical directions of the image in one frame represented by the digital image signal Sid, based on the digital image signal Sid supplied from the A/D converter 1, the clock Sc supplied from the clock generation circuit 2, the delayed horizontal synchronizing signal Shs supplied from the delay circuit 5, and the vertical synchronizing signal Vsync supplied from the personal computer.
  • the image start/termination coordinate detection circuit 3 then generates an image information signal Si representing the state of the image.
  • the display control circuit 4 is connected to the image start/termination detection circuit 3, to receive the image information signal Si.
  • the display control circuit 4 generates the above-mentioned clock count data Scd, phase data Sp, and display control data Sdc based on the image information signal Si.
  • the analog image signal Sia has an effective horizontal display period HEDP which is displaying the image on one horizontal line, and is positioned with good balance within a horizontal synchronization period Th of the horizontal synchronizing signal Hsync. More specifically, in the image signal on one horizontal line, the effective horizontal display period HEDP is bracketed by a preceding no-display period TnP and a following no-display period TnF which include no display image data.
  • each pixel of the digital image signal Sid which is analog-digital converted from the analog image signal Sia in synchronization with clock pulses of the clock Sc which is a basis of the A/D conversion contains an image or not.
  • a line image starting pixel Ps' and a line image ending pixel PE' of the effective horizontal display period HEDP can thus be detected in each line of the digital image signal Sid.
  • the horizontal position of the line image starting pixel PS' is then defined as left horizontal image coordinates HcS', and the horizontal position of the line image ending pixel PE' is defined as right horizontal image coordinates HcE'.
  • the image start/termination coordinate detection circuit 3 performs the above processing for each screen image, and can thereby detect the horizontal coordinates HcS' for a pixel position at the left end (an image starting point) in one screen image and the horizontal coordinates HcE' for a pixel position at the right end (an image ending point) in the screen image.
  • the horizontal coordinates HcS' and the horizontal coordinates HcE' are hereinafter referred to as the image starting point and the image ending point.
  • the effective horizontal display period HEDP contains image information relating to a horizontal pixel count which conforms to a resolution of the output video adapter of the personal computer. More specifically, a standard screen resolution of an image outputted from a VGA video adapter is 640 horizontal pixel count by 480 vertical pixel count in a graphics mode. That is, the image information for 640 pixels is included in the effective horizontal display period HEDP.
  • the effective horizontal display period HEDP can therefore be expressed by the horizontal pixel count H of the digital image signal Sid. Note also that the processing procedure performed in synchronization with a period between the pulses of the clock Sc is a clock cycle.
  • the value of the clock count data Scd must be adjusted so that the clock Sc has 640 pulses in the effective horizontal display period HEDP in order to generate the digital image signal Sid containing image information for 640 pixels in the effective horizontal display period HEDP by A/D conversion of the analog image signal Sia.
  • A/D conversion processing performed in the digital video display DD is described.
  • the A/D converting processing in the digital video display is to sample an analog image signal value at the leading (or trailing) edge of each divided wave which is produced by dividing the horizontal synchronization period Th by a same period interval Tc, and then to convert the sampled value into a digital value.
  • a clock Sc is produced divided waves.
  • the horizontal synchronizing signal Hsync and the analog image signal Sia are not completely synchronized with each other.
  • the clock Sc therefore, must be delayed relative to the horizontal synchronizing signal Hsync so that the sampling timing approaches the peak of the analog signal in order to acquire a good conversion result.
  • the range from zero to one dividing period (Tc) is enough as the range to be adjusted by a delay time Td.
  • the above adjustment is referred to as phase adjustment.
  • the clock Sc is delayed by the delay time Td from the starting point of the horizontal synchronization period Th, so that the peak value of the analog image signal Sia is sampled.
  • the image start/termination coordinate detection circuit 3 keeps detecting a line image starting pixel PS' which is at the first pixel position and a line image ending pixel PE' which is at the last pixel position in each horizontal synchronization period Th.
  • the image start/termination coordinate detection circuit 3 outputs the smallest pixel among the line image starting pixels PS' and the line image ending pixels PE' in entire horizontal period in one screen as a horizontal image starting point, and outputs the largest pixel as a horizontal image ending point.
  • a pixel in a divided section where a pixel is first detected is defined as the line image starting pixel PS', and a pixel in a divided section where a pixel is detected at the last is defined as the line image ending pixel PE'.
  • FIG. 8 The relation between the line image starting pixel PS' and the phase is described next, referring to FIG. 8.
  • a portion including the first pixel of the analog image signal Sia in the horizontal synchronization period Th, the threshold value Lt and divided waves Cn (n 0, 1, 2, 3 and 4) which are respectively delayed by an n/5 dividing period with respect to the horizontal synchronizing signal Hsync.
  • Ps (“s" is a positive integer of not less than zero) is a divided section number expressing which divided section from the beginning each pulse of the divided waves Cn is.
  • a pixel positioned at the rising edge of each pulse belonging the "Ps - 1"th divided period is defined as the line image starting pixel PS'.
  • the clocks Sc are generated using the same dividing ratio, if the clocks Sc like the divided waves C0, C1, C2, C3 and C4 whose phase are different from each other are used in A/D conversion, the position of the line image starting pixel PS' varies depending on the phase values of the clocks Sc.
  • FIG. 9 is the same as FIG. 8 except that a part of the analog image signal Sia corresponding to the last pixel in the horizontal synchronization period Th and a divided section number Pe ("e" is an integer larger than "s") are shown. Note that the value of the divided section number Pe in this case is larger than the value of Ps by the value equivalent to the effective horizontal display period HEDP.
  • the analog image signal Sia is A/D converted with the divided waves C0, C1, C2 and C3
  • the analog image signal Sia falls below the threshold value Lt between the "Pe”th pulse and the "Pe + 1"th pulse.
  • a pixel positioned at the rising edge of each pulse belonging to the "Pe"th divided period therefore, is defined as the line image ending pixel PE'.
  • a pixel positioned at the rising edge of a pulse belonging to the "Pe - 1" th divided period is defined as the line image ending pixel PE'.
  • phase value at which the position of the line image starting pixel PS' is changed and the phase value at which the position of the line image ending pixel PE' is changed are not necessarily the same.
  • FIG. 10 shown are an image starting point HcS' and an image ending point HcE' which are respectively positions of the line image starting pixel PS' and the line image ending pixel PE' for each phase value in the examples shown in FIGS. 8 and 9, and the difference therebetween.
  • the drawing shows that, even when A/D conversion is performed with the clocks Sc having the same frequency like the divided waves C0, C1, C2, C3 and C4, the difference between the image ending point HcE' and the image starting point HcS' varies depending on the phase values of the clocks Sc.
  • the difference (HcE' - HcS') between the image ending point HcE' and the image starting point HcS' and an assumed pixel count are compared with each other, and based on the difference therebetween the clock adjustment is made. That is, the clock value is adjusted so that the difference (HcE' - HcS') between the image ending point HcE' and the image starting point HcS' matches the assumed pixel count.
  • the clock Sc is shifted by one pulse when A/D conversion is performed with the clock Sc having the phase of the divided wave C3 shown in FIG. 8. Resultantly, the results of the clock Sc adjustment are varied.
  • the middle of the two change points is considered to be an optimal phase point on a basis that the phase value at which the image starting point is changed is a phase value corresponding to the threshold value Lt for pixel detection (the phase condition of the divided wave C3 in FIG. 8), and the two change points are phase values corresponding to the threshold values Lt in the two divided periods adjacent to each other.
  • the clock adjustment on such basis has problems described below.
  • the pulse egde of clock Sc is not always shift from the point where the analog image signal Sia crosses the threshold value Lt by just half phase period, therefore the middle value of the two change points is not necessarily optimal.
  • the curve of the analog image signal Sia is varied depending on signal sources, it is difficult to select the given threshold value Lt satisfying the above phase condition.
  • the phase condition of entire signal can not be judged based on only the change of the image starting point HcS' detected depending on the rising wave.
  • the adjustment can be made according to the similar idea by using the phase value at which the image ending point HcE' is changed, however, the adjustment is not accurate for the same reason as in the image starting point.
  • the horizontal image start coordinates and the horizontal image termination coordinates are detected, and thereby the clock is adjusted according to the difference between the coordinates.
  • the error in the coordinates due to a phase-shift is not considered, causing a situation in which the clock is deviated by one pixel portion.
  • the phase is adjusted based on the change in the horizontal image starting position when the phase is changed from the minimum value to the maximum value. More specifically, a point at which the horizontal image starting position is changed is determined to be a point in a bad phase-condition.
  • a value for the middle of the two points is determined to be an optimal value.
  • a value which is half out of phase is determined to be an optimal value.
  • the point half out of phase with the change point is not optimal in most cases since the change in the analog waveform is not uniform.
  • the change is misidentified as change in phase value. This leads to a situation where adjustment is made without conforming to the actual phase value.
  • Adjustment of image display position is directly influenced by the accuracy in the clock and the phase adjustment. Accordingly, the display position after the aforementioned situations occur is displaced by one pixel portion.
  • an object of the present invention is to provide a digital image display apparatus proposing a novel method of automatically adjusting a clock, phase and display position, and always resolving the above-described first to fifth problems.
  • a first aspect of the present invention is directed to a digital image display apparatus converting an analog image input signal into digital form for display image, comprising:
  • the horizontal image start coordinates and the horizontal image termination coordinates of the digitized video signal are detected, and by using such data, the clock count data and the phase data conforming to the actual state of the inputted video signal can be set.
  • a second aspect of the present invention is directed to a digital image display apparatus converting an analog image input signal into digital form for display image, comprising:
  • the horizontal image start coordinates and the horizontal image termination coordinates of the digitized video signal are detected, and by using such data, the clock count data and the phase data conforming to the actual state of the inputted video signal can be set.
  • a digital image display apparatus IDA mainly comprises an input video adapter VAi, an image display driver 10, and an image display 11.
  • the input video adapter VAi (hereinafter, referred to as a video adapter VAi) is connected to a personal computer (not shown in the drawing), to generate a digital image signal Sid and image display control data Sdc based on an analog image signal Sia, a vertical synchronizing signal Vsync, and a horizontal synchronizing signal Hsync supplied from the personal computer.
  • the image display driver 10 is connected to the video adapter VAi, to generate a digital image driving signal SD for driving the image display 11 based on the digital image signal Sid and the display control data Sdc supplied from the video adapter VAi.
  • the image display 11 is connected to the image display driver 10 and driven by the digital image driving signal SD, to display images.
  • the image display 11 can be a liquid crystal display, plasma display, cathode type flat display, or other various image display devices used for displaying images by means of a digital image signal.
  • the video adapter VAi has an A/D converting unit ADCU, an image start/termination coordinate detector 3, a display controller 4R, and an image start/termination coordinate storage 6 interconnected as shown in FIG. 1.
  • the A/D converting unit ADCU is connected to the personal computer, and supplied with the analog image signal Sia, the vertical synchronizing signal Vsync, and the horizontal synchronizing signal Hsync constituting an analog video signal.
  • the image start/termination coordinate detector 3 is connected to the personal computer, and supplied with only the vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync.
  • the image start/termination coordinate detector 3 detects start coordinates and termination coordinates in the horizontal and vertical directions in one frame image represented by the digital image signal Sid, based on the digital image signal Sid and a clock Sc supplied from the A/D converting unit ADCU, and the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync supplied from the personal computer, to generate an image information signal Si representing the state of the image.
  • the image start/termination coordinate storage 6 is connected to the image start/termination coordinate detector 3, and supplied with the image information signal Si.
  • the image start/termination coordinate storage 6 then generates an image information signal Sir in response to a read request from the display controller 4R.
  • the display controller 4R is connected to the image start/termination coordinate storage 6, and receives the image information signal Sir.
  • the display controller 4R generates clock count data Scd, phase data Sp, and display control data Sdc based on the image information signal Sir. The operation of the display controller 4R will be described later in detail with reference to FIGS. 3 and 4.
  • the A/D converting unit ADCU includes an A/D converter 1, a clock generator 2, and a delay unit 5.
  • the delay unit 5 is connected to the personal computer and the display controller 4R, and supplied with the horizontal synchronizing signal Hsync and the phase data Sp therefrom, respectively.
  • the delay unit 5 then changes the phase of the horizontal synchronizing signal Hsync according to the phase data Sp, and generates a delayed horizontal synchronizing signal Shs.
  • the clock generator 2 is connected to the delay unit 5 and the display controller 4R, and supplied with the delayed horizontal synchronizing signal Shs and the clock count data Scd therefrom, respectively.
  • the clock generator 2 then generates the clock Sc in which its clock count and phase are controlled, based on the delayed horizontal synchronizing signal Shs and the clock count data Scd.
  • the A/D converter 1 is connected to the personal computer and the clock generator 2, and supplied with the analog image signal Sia and the clock Sc therefrom, respectively.
  • the A/D converter 1 converts the analog image signal Sia into a digital image signal Sid in synchronization with the clock Sc.
  • the clock Sc generated in the clock generator 2 and the digital image signal Sid generated in the A/D converter 1 are also supplied to the image start/termination coordinate detector 3.
  • the video adapter VAi After the analog video signal constituted by the analog image signal Sia, the horizontal synchronizing signal Hsync, and the vertical synchronizing signal Vsync is inputted from the personal computer, the video adapter VAi generates the digital image signal Sid and the display control data Sdc in the following procedure.
  • step #100 the display controller 4R generates the clock count data Scd according to the state of the digital image signal Sid. Based on the clock count data Scd, the clock generator 2 then generates the clock Sc correctly adjusted. Details of the clock adjustment routine performed in the present step will be described later with reference to FIG. 3.
  • step #200 the display controller 4R generates the phase data Sp according to the state of the digital image signal Sid. Based on the phase data Sp, the delay unit 5 adjusts the phase of the horizontal synchronizing signal Hsync, and generates the delayed horizontal synchronizing signal Shs. Details of the phase adjustment routine performed in the present step will be described later using FIG. 4.
  • step #300 the display controller 4R generates the display control data Sdc according to the state of the digital image signal Sid.
  • step #400 the image display driver 10 subjects the digital image signal Sid to image signal processing based on the display control data Sdc generated in step #300, and generates the driving signal SD for the digital image display apparatus.
  • step #500 the image display 11 displays an image in a correct state based on the driving signal SD generated in step #400. The procedure is then terminated.
  • the concept of the clock adjustment according to the present invention is described.
  • the leading and trailing edges of the analog image signal do not make ideal steepness. Resultantly, even if the clock count is correct, when the clock Sc having the same phase value as that of the divided wave C3 is used in A/D conversion, the detected image starting point HcS' and the image ending point HcE' essentially includes errors.
  • the clock adjustment step is not necessarily performed with an optimal phase, which leads to a possibility that the difference (HcE' - HcS') between the image ending point HcE' and the image starting point HcS' is larger than the value measured in an optimal phase condition by one or two.
  • the display controller 4R successively generates the phase data Sp which can be set, then successively measures and stores the difference value (HcE' - HcS') between the image ending point HcE' and the image starting point HcS'.
  • the smallest value among the values successively stored is considered to be a value measured under the optimal phase condition, thereby being used in the clock adjustment.
  • the clock adjustment is made by changing the phase and using the values of the image starting point HcS' and the image ending point HcE' determined under the desirable phase condition, to solve the above problem.
  • the image starting points HcS' and the image ending points HcE' are measured in all phase conditions, and then the value positioned in the center of a phase region in which the differences (HcE' - HcS') between the image ending points HcE' and the image starting points HcS' take assumed values is defined as the optimal phase point. This enables highly accurate phase adjustment.
  • step S101 the system is reset and an assumed image width value NPP is set.
  • step S102 the phase data Sp is set to a minimum value Pmin, and a minimum pixel count NHPmin corresponding thereto is set to a value larger than a maximum value among values returned from the image start/termination detector 3.
  • step S103 the phase data Sp is checked whether to reach a maximum value Pmax or not, and thereby loop processing from the foregoing step S102 to step S108 described later is determined whether to end or not.
  • step S104 the phase data Sp is outputted to the A/D converting unit ADCU.
  • step S105 the image information signal Si is acquired from the image start/termination coordinate detector 3, and thereby the pixel count NHP in an effective horizontal display period is obtained.
  • steps S106 and S107 it is checked whether the pixel count NHP for the present phase data Sp is at the minimum or not. When it is at the minimum, the value of a minimum pixel count NHPmin is updated.
  • step S108 the value of the phase data Sp is updated to a next value.
  • the procedure then returns to step S103 for determining the end of the loop.
  • step S109 the minimum pixel count NHPmin is judged whether to match the desired pixel count NPP indicating the desired image width value or not. When it matches, this means that A/D conversion is performed with the clock count data Scd capable of acquiring the desired image width, and therefore the adjusting processing is terminated. On the contrary, when the minimum pixel count NHPmin does not match the desired pixel count NPP, the clock count data Scd must be corrected, and therefore the procedure advances to step S110.
  • step S110 the clock count data Scd is corrected by the difference between the desired pixel count NPP and the minimum pixel count NHPmin.
  • the minimum pixel count NHPmin is smaller than the desired pixel count NPP
  • the clock count data Scd is increased
  • the clock count data Scd is decreased when the minimum pixel count NHPmin is larger than the desired pixel count NPP.
  • This means new clock count data Scd is calculated by the expression Scd + NPP - NHPmin .
  • step S111 the clock Sc corresponding to the new clock count data Scd is generated and outputted to the image start/termination coordinate detector 3.
  • step S112 the new clock count data is outputted to the A/D converting unit ADCU. The procedure is repeated again from step S102.
  • the leading and trailing edges of the analog image signal do not make ideal steepness. Therefore, even if the clock value is correctly set, when the phase data is deviated, the value obtained by the expression (the image ending point HcE') - (the image starting point HcS') becomes larger than the actual value. Since an analog signal takes sequential values, the phase data capable of being set is successively generated by the display adjusting circuit.
  • the values obtained by the expression (the image ending point HcE') - (the image starting point HcS') are measured in respective phase data conditions, the values are distributed in two blocks. In one of the blocks, the desired values are continuous, while in the other block, values other than (larger than) the desired values are continuous.
  • Noise has effects only when undesired values (larger than the desired values) are measured even in a phase condition where desired values can be measured. The reason is that even in the phase condition where desired values can be read, the undesired value is measured when a noise is superimposed on the region other than the image data region, even if the region is in the horizontal synchronization period Th in one frame. In the case where a value which is actually the undesired value appears to be the desired value due to a noise, however, the real analog data should be canceled by the noise in entire horizontal period. Accordingly, such case does not occur in reality.
  • the measured distributed values include a phase point at which the undesired value is measured due to a noise in spite of the fact that the desired values can be read in the phase condition in reality.
  • the distribution is then shaped by evaluating all distributed values except the values in the longest undesired-value-continuous block as the phase data Sp in which the desired values have been measured.
  • accurate phase adjustment can be made unaffected by a noise.
  • phase adjustment subroutine of the above-described step #200, referring to FIG. 4.
  • step S202 the data is initialized to set the phase data Sp to the minimum value Pmin.
  • step S203 the phase data Sp is checked whether to reach the maximum value Pmax or not. Then it is judged whether loop processing from the foregoing step S202 to step S209 described later ends or not.
  • the loop processing is for detecting the pixel count value NHP which is obtained by the expression (the image ending point HcE') - (the image starting point HcS') in all phase data conditions.
  • step S204 the clock generator 2 outputs the phase data Sp to the A/D converting unit ADCU.
  • step S205 the display controller 4R receives the image information Si from the image start/termination coordinate detector 3 through the image start/termination coordinate storage 6, and determines the pixel count NHP.
  • step S206 it is checked whether the desired pixel count value NHP for the present phase data Sp matches the desired pixel count value NPP or not.
  • step S207 or 208 a judgement result (OK or NG) in response to the result of the check is held in "Status []".
  • step S209 the value of the phase data Sp is updated to a next value.
  • the procedure then returns to step S203 for judging the end of the loop.
  • the procedure moves to noise removal processing in step S210.
  • step S210 the state of the point having an undesired value presumably because of a noise for the above-described reason is rewritten from NG to OK. Specifically, the content of the array "Status []" holding the judgement result is scanned. The block including the longest series of NG is detected, and the points outside the block are rewritten into OK . It should be considered that the block extends over the minimum value Pmin boundary or the maximum value Pmax boundary in some cases.
  • step S211 it is judged whether an optimal value of the phase data Sp is determined as the center of the desired-value-continuous block in the processing after step S220, or as the point half out of phase with the center of the undesired-value-continuous block in the processing after step S230.
  • the distribution of OK and NG in the "Status []" is corrected so as to be divided into two blocks in step S210 by the noise removal processing. Therefore, it is possible to judge that the desired-value block is continuous in the rage from Pmin to Pmax, if the judgment results for the minimum value Pmin and the maximum value Pmax are both NG . On the other hand, if either one or both of the judgement results for the minimum value Pmin and the maximum value Pmax are OK , it is possible to judge that the undesired-value block is continuous in the range from Pmin to Pmax.
  • step S220 the phase data Sp is initialized to the minimum value Pmin in order to be used as an index for scanning "Status []". Moreover, a variable Count for counting the number of OK points and an accumulation index Popt for computing the optimal phase data Sp are each cleared to zero.
  • step S221 it is checked whether the phase data Sp reaches its maximum value or not, to judge the end of the loop.
  • Step S222 the judgement result is checked.
  • the point is the OK point
  • the variable Count is incremented by one in step S223, and the phase data Sp is added to the accumulation index Popt in step S224.
  • step S225 the value of the phase data Sp is updated to a next value. Then the procedure returns to step S221 for judging the end of the loop.
  • step S221 At the time when the end condition is satisfied in step S221 and the procedure branches to step S226, the sum of the variable Count for counting the number of OK points and the index Popt is already computed. Accordingly, an index of the center of the desired-value-continuous block is obtained based on the judgement in step S226 and a division in step S227, and is set in the accumulation index Popt. The index is exactly the optimal point of the phase data Sp to be obtained.
  • step S230 the phase data Sp is initialized to the minimum value Pmin so as to be used as an index for scanning Status [].
  • the variable Count for counting the number of NG points and the accumulation index Popt for computing the optimal phase data Sp are each cleared to zero.
  • step S231 it is checked whether the phase data Sp reaches its maximum value or not to judge the end of the loop.
  • step S232 the judgement result is checked.
  • the point is the NG point
  • the variable Count is incremented by one in step S233, and the phase data Sp is added to the accumulation index Popt in step S234.
  • step S235 the phase data Sp is updated to a next value. The procedure then returns to step S231 for judging the end of the loop.
  • step S236 At the time when the end condition is satisfied in step S231, and the procedure branches to step S236, the sum of the variable for counting the number of NG points and the index Popt is already computed.
  • An index of the center of the undesired-value-continuous block is determined based on judgement in step S236 and a division in step S237, and is set in the accumulation index Popt.
  • step S2308 (Pmax + Pmin)/2 is added to the accumulation index Popt to make the phase value half out of phase. This sometimes results in the case where the accumulation index Popt exceeds the range from the minimum value Pmin to the maximum value Pmax.
  • the accumulation index Popt is, therefore, corrected to be within the range by judgement in step S239 and a subtraction in step S240.
  • the index is exactly the optimal phase data Sp to be obtained.
  • the optimal phase data Sp and the accumulation index Popt obtained by processing after step S220 or step S220 or processing after step S230 is outputted as phase data Sp to the A/D converting circuit.
  • image start/termination coordinates of a digitized video signal are detected, and such data is used to set the clock count data and phase data so as to conform to the actual state of the inputted video signal. Accordingly, it is unnecessary to previously provide preset data conforming to a video signal to be inputted. As a result, it is also not necessary for the user to adjust an offset between the inputted video signal and the preset data.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP99107443A 1998-05-27 1999-04-27 Verfahren und Schaltung zur automatischen Phasen- und Frequenzeinstellung von einem rückgewonnenen Takt in einer digitalen Bildanzeigevorrichtung Withdrawn EP0961261A1 (de)

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JP14536098 1998-05-27
JP14536098 1998-05-27

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2360672A1 (de) * 2010-01-26 2011-08-24 Canon Kabushiki Kaisha Automatische Quantisierungstaktphasen-anpassbare Anzeigevorrichtung
TWI419571B (zh) * 2009-07-03 2013-12-11 Acer Inc Effective display cycle judgment device and its judgment method, resolution judgment system and judgment method thereof
CN110895918A (zh) * 2019-06-11 2020-03-20 研祥智能科技股份有限公司 分辨率调整方法及其系统

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07219485A (ja) * 1994-02-07 1995-08-18 Toshiba Corp 液晶表示装置
EP0791913A2 (de) * 1996-02-22 1997-08-27 Seiko Epson Corporation Verfahren und Vorrichtung zur Einstellung eines Punkttaktsignales
EP0805430A1 (de) * 1996-04-26 1997-11-05 Matsushita Electric Industrial Co., Ltd. Videoadapter und digitales Bildanzeigegerät

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07219485A (ja) * 1994-02-07 1995-08-18 Toshiba Corp 液晶表示装置
EP0791913A2 (de) * 1996-02-22 1997-08-27 Seiko Epson Corporation Verfahren und Vorrichtung zur Einstellung eines Punkttaktsignales
EP0805430A1 (de) * 1996-04-26 1997-11-05 Matsushita Electric Industrial Co., Ltd. Videoadapter und digitales Bildanzeigegerät

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 199, no. 511 26 December 1995 (1995-12-26) *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI419571B (zh) * 2009-07-03 2013-12-11 Acer Inc Effective display cycle judgment device and its judgment method, resolution judgment system and judgment method thereof
EP2360672A1 (de) * 2010-01-26 2011-08-24 Canon Kabushiki Kaisha Automatische Quantisierungstaktphasen-anpassbare Anzeigevorrichtung
US8421920B2 (en) 2010-01-26 2013-04-16 Canon Kabushiki Kaisha Automatic quantization clock phase adjustable display apparatus
CN110895918A (zh) * 2019-06-11 2020-03-20 研祥智能科技股份有限公司 分辨率调整方法及其系统
CN110895918B (zh) * 2019-06-11 2021-10-22 研祥智能科技股份有限公司 分辨率调整方法及其系统

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