Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
  • H04L27/2657—Carrier synchronisation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
  • H04L27/2668—Details of algorithms
  • H04L27/2673—Details of algorithms characterised by synchronisation parameters
  • H04L27/2675—Pilot or known symbols
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
  • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
  • H04L27/38—Demodulator circuits; Receiver circuits
  • H04L27/3845—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier
  • H04L27/3854—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
  • H04L27/3872—Compensation for phase rotation in the demodulated signal

Definitions

• the present invention relates to a method and apparatus for recovering the amplitude and phase of an input data signal.
• the invention is of particular application to recovering input data signals that are Orthogonal Frequency Division Multiplex (OFDM) signals.
• OFDM Orthogonal Frequency Division Multiplex
• the amplitude and phase of the received data signal must be recovered before de-mapping can take place.
• the channel amplitude and phase are recovered for each carrier position and the data is then corrected by this amount. This correction process requires a complex or vector division, sometimes known as 'projection'.
• the CORDIC process is a well-established method of performing vector rotations.
• the accuracy of the result is dependent upon the number of iterations of the process: for n bits of accuracy, n+1 iterations are required. Unfortunately the process does not converge very quickly and there may still be some residual error in the result.
• the present invention now provides a method of recovering the amplitude and phase of an input data signal including at least one data vector and a 0 reference vector, the method comprising the steps of rotating the reference vector, rotating the data vector by reference to the rotation of the reference vector and dividing the resultant data vector by the resultant reference vector.
• the present invention also provides apparatus for recovering the amplitude and phase of an input data signal including at least one data vector and a reference vector comprising a means of rotating a reference vector, a means of rotating a data vector with reference to a reference vector and a means of scalar dividing two vectors.
• a pilot, or reference, signal is received which was transmitted with a known phase and a known amplitude.
• One or more data signals will also be received. Due to distortion caused by the transmission channel the received signals do not necessarily have the same phase or amplitude as when transmitted.
• the reference signal is first rotated to its original transmitted position. The data signal is also rotated by the same amount, thus correcting it for phase distortion. A scalar division of the rotated data signal by the rotated reference signal then corrects the data signal for any distortion in amplitude.
• Figure 1 is a diagram showing an overview of the amplitude and phase recovery system according to the present invention
• Figure 2 is a diagram showing a detailed view of the reference vector rotator according to the present invention.
• Figure 3 is a diagram showing a detailed view of the data vector rotator according to the present invention.
• Figure 4 is a diagram showing a detailed view of the scalar divider according to the present invention.
• Figure 5 is a diagram showing a detailed view of the control section according to the present invention
• Figure 6a is a flow diagram showing the procedure performed by the first cycle of the control section according to the present invention
• Figure 6b is a flow diagram showing the procedure performed by the second and subsequent cycles of the control section according to the present invention
• Figure 7 is a diagram showing the rotation of a reference vector according to the present invention.
• the amplitude and phase of the reference signal and the input data signal are converted into rectangular co-ordinates describing their respective vectors.
• the reference vector is known as the denominator (as it will ultimately be used to divide the data vector) and the data vector is known as the numerator (as it will ultimately be divided by the reference vector).
• FIG. 1 shows an overview of the amplitude and phase recovery system according to the present invention.
• the co-ordinates of a received reference signal 105a are applied at an input 105 to a reference rotator 100.
• the co-ordinates of a received data signal 106a are applied at an input 106 to a data rotator 101.
• the received reference signal 105a undergoes distortions during transmission due to various channel distortions, but the parameters of this signal are known at transmission. The same distortions will also affect the data vector.
• the reference rotator 100 under control of control section 104, rotates the received reference signal 105a to the original known phase, thereby correcting any phase distortion.
• the data rotator 101 under control of control section 104, rotates the received data signal 106a by the same amount as the received reference signal. This causes the received data signal 106a to be corrected for any phase distortion due to the transmission channel.
• the phase corrected reference signal 103a and the phase corrected data signal 103b are subsequently input to a scalar divider 103.
• the rotation stage can cause, however, an increase in amplitude of the received signals.
• the phase corrected data signal 103b is scalar divided by the phase corrected reference signal 103a. This is possible as, after correction, the phase corrected reference signal 103a has a phase of 0 degrees. This means that dividing the phase corrected data signal 103b by the phase corrected reference signal 103a only affects the amplitude and results in correction of the amplitude of the phase corrected data signal.
• the scalar divider 103 takes as inputs the phase corrected reference signal 103a and the phase corrected data signal 103b.
• the scalar divider 103 under the control of the control section 104, divides the phase corrected data signal 103b by the phase corrected reference signal 103a.
• the resultant signal, the received data signal corrected for both phase and amplitude, is then output at 107 where it can be used by further stages of a receiver.
• Figure 2 is a diagram showing a detailed view of the reference vector rotator according to the present invention.
• the received reference signal is input in its rectangular co-ordinate form with the X co-ordinate, Xd, being input at 2a and the Y co-ordinate, Yd, being input at 2b.
• the reference rotator comprises two adders, 8 and 9, which are controlled by way of an adder control signal 13, two shifters, 16 and 17, which are controlled by way of a shift control signal 30, two multiplexers, 20 and 21 , which are controlled by way of a multiplex control signal 29, and another two multiplexers, 24 and 25, which are controlled by way of a load control signal 28.
• the control signals 13, 28, 29, 30 and 31 are supplied by control section 12 as shown in Figure 5. Additionally there are two registers, 4 and 5, which are used to store the current Xd and Yd values.
• the adder control signal, 13, is fed via an inverter, 14, before being input to adder 8. This has the effect that the adder 8 and the adder 9 are generally performing the opposite function - i.e. if the adder 8 is adding, the adder 9 is subtracting, and vice versa.
• the multiplexer 24 is used to either load in a new X co-ordinate into the register 4, or to load the output of the adder 8 into the register 4.
• the multiplexer 25 performs the same operation for the Y co-ordinate and causes either a new Y co-ordinate or the output of the adder 9 to be loaded into the register 5, depending on the value of the load control signal 28.
• the multiplexer 20 under control of the multiplexer control signal 29, allows either a zero or the contents of the register 4 to be fed into the adder 8.
• the multiplexer 21 under control of the multiplexer control signal 29, allows either a zero or the contents of the register 5 to be fed into the adder 9.
• the shift registers 16 and 17 shift their respective data to perform a division by 1 , 2, 4, 8 etc. according to the value of the shift control signal 30.
• control section 104 The operation of the reference vector rotator is controlled by the control section 104, which is described in more detail below.
• the X co-ordinate is output to the scalar divider section 103.
• the Y co-ordinate is not available as an output as it will always be zero at the end of the rotation stage and is therefore not needed further.
• Figure 3 shows one possible embodiment of the data rotator 100.
• the received data signal is input in a rectangular co-ordinate form with the X co-ordinate, Xn, being input at 3a and the Y co-ordinate, Yn, being input at 3b.
• the data rotator comprises two adders, 10 and 11 , which are controlled by way of the adder control signal 13, two shift registers, 18 and 19, which are controlled by way of the shift control signal 30, two multiplexers, 22 and 23, which are controlled by way of the multiplex control signal 29, and another two multiplexers, 26 and 27, which are controlled by way of the load control signal 28.
• the control signals 13, 28, 29, 30 and 31 are supplied by the control section 12 as shown in Figure 5. Additionally there are two registers, 6 and 7, which are used to store the current X and Y co-ordinate values of the data signal.
• the adder control signal, 13, is fed via an inverter, 15, before being input to adder 10. This has the effect that the adder 10 and the adder 11 are generally performing the opposite function - i.e. if the adder 10 is adding, the adder 11 is subtracting, and vice versa.
• the multiplexer 26 is used to either load a new X co-ordinate into the register 6, or to load the output of the adder 10 into the register 6.
• the multiplexer 27 performs the same operation for the Y co-ordinate and causes either a new Y co-ordinate or the output of the adder 11 to be loaded into the register 7, depending on the value of the load control signal 28.
• the multiplexer 22, under control of the multiplexer control signal 29, allows either a zero or the contents of the register 6 to be fed into the adder 10.
• the multiplexer 23, under control of the multiplexer control signal 29, allows either a zero or the contents of the register 7 to be fed into the adder 11.
• the shift registers 18 and 19 shift their respective data to perform a division by 1 , 2, 4, 8 etc. according to the value of the shift control signal 30.
• the pass control signal 31 is input to adders 8, 9, 10 and 11 and allows the adders to perform a pass-through function (i.e. it causes the adders to pass through the data and not to perform any addition or subtraction). This is used in the event that the Y co-ordinate reaches zero quickly, the 'rotation' process can continue for a given number of cycles without affecting the data before the rotation process is deemed complete. This has the desirable effect of keeping the number of cycles required to obtain a result substantially constant.
• the operation of the data vector rotator is controlled by the control section 104, which is described in more detail later.
• both the X and Y co-ordinates are transferred to the scalar divider section 103.
• FIG. 4 is a diagram showing a detailed view of the scalar divider according to the present invention.
• the X co-ordinate of the corrected reference signal, Xd is input to a divider register 39, under control of a load signal 41.
• the X and Y co-ordinates of the corrected data signal, Xn and Yn are input to a register 34 and a register 36 respectively, again under control of the load signal 41.
• the scalar divider 103 further comprises two adders, 37 and 38, two inverters, 42 and 43, and a further two registers, 33 and 35.
• the adders 37 and 38 are controlled by control signals 45 and 44 respectively which are responsible for changing the function of the adders from addition to subtraction according to the values of the control signals.
• the operation of the scalar divider is controlled by the control section 104, and at the end of the operation, the X and Y co-ordinates of the fully
• FIG. 5 shows the inputs and outputs of the control section 104.
• a start signal 1 indicates when new reference and data signals are available and this is used as the trigger to start the correction process.
• the correction process is performed in accordance with the procedures described by the flow diagrams shown in Figure 6a and 6b.
• Figure 6a describes the first cycle of the operation, which causes a 90-degree rotation of the vectors.
• Figure 6b describes the operation of subsequent cycles which results in further rotations of the vectors, either until the Y co-ordinate is equal to zero, or until a fixed number of cycles, or iterations, have been performed.
• the control section 104 generates control signals as appropriate, during the course of processing, to control the actions of the reference signal rotator 100, the data signal rotator 101 and the scalar divider 103.
• phase corrected data vector is scalar divided by the phase corrected reference vector resulting in the data vector being corrected for both phase and amplitude.
• the X and Y co-ordinates of the data vector are then available for further processing as required.
• Figure 7 shows an example (not to scale) of a rotation of a reference vector according to the method described above. It can be seen that each rotation is progressively diminishing in size and also causes an increase in the length of the reference vector. Although Figure 7 shows that with each rotation, the Y co-ordinate of the reference vector changes sign; this may not always be the case depending on the initial value.
• the present invention is not limited, however, just to the method as describe above.
• the process can be implemented entirely in software, through use of an appropriately programmed microprocessor or other computing means.
• the two rotators i.e. the reference vector rotator and the data vector rotator
• the two rotators can be replaced by a single rotator which is used first to rotate the reference vector and then used to rotate the data vector by the same amount. This would have the effect of further reducing the amount of hardware or software to implement the present invention.
• references to vector division could also encompass complex division techniques.

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• 1997
  • 1997-01-31 GB GBGB9701984.8A patent/GB9701984D0/en active Pending
• 1998
  • 1998-01-30 ZA ZA98803A patent/ZA98803B/xx unknown
  • 1998-02-02 WO PCT/GB1998/000323 patent/WO1998034382A1/en not_active Application Discontinuation
  • 1998-02-02 AU AU58745/98A patent/AU5874598A/en not_active Abandoned
  • 1998-02-02 EP EP98902127A patent/EP0956684A1/de not_active Withdrawn

Non-Patent Citations (1)

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