EP0953239B1 - Procede de remplissage pour la transmission plesiochrone de donnees - Google Patents

Procede de remplissage pour la transmission plesiochrone de donnees Download PDF

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Publication number
EP0953239B1
EP0953239B1 EP96913426A EP96913426A EP0953239B1 EP 0953239 B1 EP0953239 B1 EP 0953239B1 EP 96913426 A EP96913426 A EP 96913426A EP 96913426 A EP96913426 A EP 96913426A EP 0953239 B1 EP0953239 B1 EP 0953239B1
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Prior art keywords
stuffing
data
clock pulse
segments
procedure according
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German (de)
English (en)
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EP0953239A1 (fr
Inventor
Ulrich Menzi
Hans Zahnd
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Keymile AG
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Keymile AG
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/073—Bit stuffing, e.g. PDH

Definitions

  • the invention further relates to a data transmission system and a terminal for implementation of the procedure.
  • the object of the invention is to provide a method of the type mentioned at the outset, this is a reduction of the jitter amplitudes going beyond the state of the art allowed.
  • the solution according to the invention is defined by the features of claim 1.
  • a difference frequency existing between the clock signals e.g. measured in the form of a ppm deviation
  • one accordingly predefined modulation curve is used as a threshold.
  • the (threshold) modulation curve can be different from segment to segment. According to the invention are at least two different segments with different modulation curves specified.
  • each segment one is preferably optimized with regard to minimal jitter amplitudes Modulation curve set. It has been shown to be much easier for only a section of the total permissible maximum difference frequency Avoid amplitude maxima than for the entire range.
  • the area adjacent to the zero point can be defined as a separate segment, that works with its own modulation curve. I.e. outside the segment mentioned a modulation curve "A" could be used while within it another modulation curve "B" is used.
  • the segments are preferably of different sizes. However, this does not have to be for everyone apply, some can easily be the same size.
  • the determined modulation curves are in the form of tables of values in a memory in the data transmission system stored. The tamping process then simply selects the correct table and reads out the values that vary from data frame to data frame.
  • the periodicity is preferably N 10. 10. Good results can be achieved with 5 N N 7 7.
  • the maximum value of the (integer) index K is preferably not greater than 2 5 . It turns out that the amplitudes D K, m are proportional to 1 / K. The maximum amplitude values to be minimized are predominantly small index values.
  • the resolution ⁇ should be better than 1/5. Good results have been achieved e.g. B. with a resolution 1/20 reached. If the resolution is too fine (e.g. ⁇ 1/100), the numerical optimization is used very lengthy and still cannot make any corresponding improvements to produce the result.
  • a differential frequency range from Z. B. - 80 ppm to + 80 ppm 9 segments provided.
  • the inventive Segmentation should typically develop its strengths from 4 segments. The optimal one However, the number will depend on the individual case. In a specific application was successfully with z. B. 9 or 14 segments operated.
  • a terminal is essential in a data transmission system according to the invention, which is a circuit for determining an existing between the clock signals Difference frequency and a correspondingly relevant segment, and that over one Memory that contains a modulation curve for each segment. If not large segments is also a table with the respective segment boundaries provided.
  • a terminal 3 or 4 is now available for each of these stations.
  • the data transfer between the terminals 3, 4 i.e. the transmission link 5) is, for example formed by two pairs of copper wires 6.1, 6.2. These are operated at a data rate, which is slightly higher than half the data rate of the data sources 1.1, 1.2. It is z. B. 1'168 Kbit / s (HDSL clock rate). The maximum transmission power is therefore included 2,336 kbps.
  • One of the two terminals has an independent clock signal generator 7 for generation the clock signal for data transmission.
  • This clock signal is in the second Terminal 4 taken over by the clock signal arrester 8. Terminals 3, 4 are therefore synchronized with each other.
  • the plesiochronous interface exists between terminals 3, 4 and the external ones Data sources or sinks 1.1, 1.2 or 2.1, 2.2.
  • a control circuit 9 or 10 (Framer) on the one hand, the data to be transferred to the two copper wire pairs 6.1, 6.2 divided and on the other hand the received data merged and output to the data sink 2.1 or 2.2.
  • the copper wire pairs 6.1, 6.2 are from Transmitter / receiver circuits 11.1, 11.2, 12.1, 12.2 (data pumps) are operated.
  • the control circuit 9 and 10 distribute the data to be transmitted to the two transmitter / receiver circuits 11.1, 11.2 or 12.1, 12.2 (switches 13.1, 14.1) and leads on the other hand the incoming data together (switches 13.2, 14.2).
  • the essence of the invention is the stuffing control circuit integrated in the control circuit 9, 10 15, 16.
  • this comprises an elastic memory 19, a comparator 20 and an AND gate 21.
  • the data to be transmitted (TX_DATA_IN) entered into the memory 19. They are output on the basis of the clock signal of the transmission system (HDSL_CLK). Since the readout with a slightly higher clock rate is done as the input, stuff bits have to be inserted from time to time.
  • a comparator 20 For control this process, a comparator 20 is provided, which the two clock signals (WRITE_CLK and HDSL_CLK) compares and depending on the within a data frame accumulated phase difference generates an enable signal that is in the AND gate 21 is linked to the HDSL clock signal.
  • a frame end pulse generator 24 shows the end of a user data block. Whenever the phase difference when the frame end pulse occurs exceeds a certain threshold, then the readout clock (READ_CLK) for z. B. 4 HDSL clock periods stopped. (There the number of useful bits per data frame are known on the receiver side, it is possible to eliminate the stuff bits generated in this way.)
  • the threshold value for the phase difference of Frame to frame varies in a certain way (stuffing threshold modulation).
  • the purpose is to determine the difference frequency in advance.
  • a Frequency discriminator 27 is provided, which compares WRITE_CLK and HDSL_CLK and the difference frequency (e.g. in the form of a counter reading which is converted into a ppm value can be converted) to the table memory 28.
  • FIG. 3 shows an example of a circuit for measuring the differential frequency.
  • the clock signal TX_USER_CLK of the external data source is given to the input of a frequency divider 22. This realizes, for example, a division ratio 2 21 .
  • the resulting divided output signal is given on the one hand to the reset input of a counter 23 and on the other hand to the clock input of a memory 24.
  • the counter 23 is incremented by the clock signal HDSL_CLK (and reset in accordance with the output pulse of the frequency divider 22).
  • a word (counter reading) with 8 bits is generated on the output side of the counter 23 and is stored in the memory 24. From there it can e.g. B. can be picked up by a microprocessor of the terminal (in order to determine the relevant segment and the correct modulation curve).
  • difference frequency can also be determined in other ways.
  • a range 25 from -82 ppm to + 82 ppm is shown by way of example in FIG. 4.
  • This area 25 depends on the specific system parameters. It essentially results in that both the clock signal of the data source and that of the transmission system may deviate from the nominal value by a predetermined range.
  • the maximum ppm deviation is usually defined by a standard. (The in the In principle, the ppm values used in this description represent the sum the relative deviations of the user clock and the HDSL clock from each the nominal value of the corresponding clock rate.)
  • the whole ppm range 25 is divided into a plurality of segments according to the invention 26.1 to 26.9 divided.
  • Each segment is a (digital) modulation curve 27.1 to 27.9 assigned.
  • the ppm values given not all of them are Segments 26.1 to 26.9 of the same size. In particular, the segments are close to 0 ppm smaller than that at higher ppm values.
  • the smallest segment 26.5 is in the present Example in the middle, the largest segments 26.1, 26.9 are outside.
  • Every deviation (Xppm) in the ppm range corresponds to a stop rate ⁇ .
  • the relationship is determined by the following formula.
  • the N-tuple (T 0 , ..., T N-1 ) is varied over all permissible base value combinations and for each combination all amplitude values D K, m are calculated.
  • the N-tuple (T 0 , ..., T N-1 ) that shows the best amplitude values also defines the optimal base value combination or the optimal modulation curve.
  • the numerical optimization can also be done in other ways. It is particularly conceivable that a certain type of curve is considered as predefined (e.g. a sawtooth or Gaussian curve) and that only the scaling (e.g. the parameters periodicity ,. Value range etc.) can be optimized. So it is z. B. possible that in each Segment, an optimal sawtooth curve is used as the modulation curve:
  • the modulation curves and segments according to the invention can be in a ROM of the Terminals are stored.
  • the tamping process pulls the different one after the other Values of the modulation curve to be taken into account on the basis of the determined phase difference approach.
  • threshold_1, threshold_2 For a 0/2/4 tamping process, for example, two thresholds (threshold_1, threshold_2) are defined, which vary synchronously (according to the values specified in the table) and are spaced apart by 2 HDSL cycles. A new threshold is defined for each data frame (index i). (As a rule, the threshold value will change continuously, but this does not mean that, in exceptional cases, two successive values can be the same.)
  • the stuffing bits are inserted on the basis of the following comparisons: Phase difference ⁇ -Schwelle_1 ⁇ 0 insert stuffing bits - Threshold_2 ⁇ phase difference ⁇ -Shreshold_1 ⁇ insert 2 stuff bits Phase difference ⁇ -Schwelle_2 ⁇ insert 4 stuff bits
  • the stuffing threshold modulation according to the invention leads to a receiver-side modulation PLL circuit 17, 18 (see Fig. 1) below the cutoff frequency (i.e. typically in the ⁇ 1 Hz range) has rather small jitter or wander amplitude peaks.
  • the stuffing threshold modulation according to the invention brings particularly good results for 0/4 and 0/2/4 tamping processes (i.e. tamping processes with one or two thresholds).
  • tamping processes with one or two thresholds.
  • other applications make sense. Basically it comes does not depend on how many bits are inserted at a time.
  • Hardware are next to Transmission systems with two wire pairs also those with three or only one of Interest.
  • the invention can be used in any transmission system (especially in optical).

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Dental Preparations (AREA)
  • Communication Control (AREA)

Claims (10)

  1. Procédé de remplissage pour une transmission plésiochrone de données, selon lequel
    a) des données sont introduites sur la base d'un premier signal de cadence (TX_DATA_IN) dans une mémoire élastique (19), et
    b) sont délivrées sur la base d'un second signal de cadence (HDSL_CLK), qui est asynchrone par rapport au premier signal,
    c) selon lequel, lors de la lecture à la fin d'une trame de données, on introduit si besoin des bits de remplissage, et ce en se basant sur le fait qu'une différence de phase mesurée entre les signaux de cadence dépasse au moins un seuil prédéterminé par valeurs supérieures ou par valeurs inférieures,
    caractérisé en ce que
    d) on mesure une fréquence différentielle existant entre les signaux de cadence et on utilise en tant que seuil une courbe de modulation prédéfinie de façon correspondante en fonction de celui de plusieurs segments prédéterminés, dans lequel cette différence se situe.
  2. Procédé de remplissage selon la revendication 1, caractérisé en ce que la courbe de modulation d'un segment est optimisée en ce qui concerne une amplitude minimale de petites oscillations et en ce qu'on utilise ensemble au moins deux courbes de modulation différentes.
  3. Procédé de remplissage selon la revendication 2, caractérisé en ce que les segments (26.1-26.9) ont des tailles différentes.
  4. Procédé de remplissage selon l'une des revendications 1 à 3, caractérisé en ce que pour l'obtention d'une courbe de modulation optimisée de façon numérique, pour un segment déterminé, on utilise les étapes suivantes consistant à :
    a) déterminer une gamme admissible, correspondant au segment sélectionné, de la cadence de remplissage ρ;
    b) fixer un nombre désiré de valeurs de base T0, ..., TN-1 et une résolution numérique ε pour chaque valeur d'appui;
    c) fixer un indice maximum désiré Kmax et déterminer tous les couples d'indices K, m pour la cadence de remplissage ρ = m/KN dans la gamme admissible;
    d) déterminer les valeurs d'appui T0, ... , TN-1, qui conduisent aux plus petites valeurs des amplitudes DK,m. DK , m = 1π · K (d r K,m )2 + (d t K,m ) 2 avec
    Figure 00230001
    Figure 00230002
  5. Procédé de remplissage selon la revendication 4, caractérisé en ce que le nombre N est N ≤ 10, en particulier ≤ 7 et de préférence ≥ 5.
  6. Procédé de remplissage selon la revendication 4 ou 5, caractérisé en ce que l'indice maximum est Kmax ≤ 25.
  7. Procédé de remplissage selon l'une des revendications 4 à 6, caractérisé en ce que la relation 1/100 ≤ ε ≤ 1/20 est vérifiée.
  8. Procédé de remplissage selon l'une des revendications 1 à 7, caractérisé en ce qu'on utilise au moins 4 segments.
  9. Système de transmission de données, qui convient pour la mise en oeuvre d'un procédé de remplissage selon l'une des revendications 1 à 3, comportant des terminaux (3, 4) disposés aux extrémités d'une section de transmission (5), les terminaux (3, 4) comportant
    a) une source de signaux de cadence (7) pour la transmission de données et au moins une mémoire élastique (10) pour la mémorisation temporaire des données arrivantes et à transmettre,
    b) un comparateur (20) pour déterminer une différence de phase entre un signal de cadence des données entrantes et la source de signaux de cadence (7),
    c) un générateur (15, 16) de trames comportant un circuit (15, 16) de commande des bits de remplissage,
    caractérisé par
    d) un circuit pour déterminer une fréquence différentielle qui existe entre les signaux de cadence,
    e) une mémoire comportant respectivement une courbe de modulation pour chacun de plusieurs segments prédéterminés, et
    f) un circuit pour déterminer, celui des segments dans lequel est situé la fréquence différentielle, de manière à utiliser en tant que seuil la courbe de modulation prédéfinie de façon correspondante, en fonction du segment déterminé.
  10. Terminal pour un système de transmission de données selon la revendication 9, comprenant:
    a) une source de signaux de cadence (7) pour la transmission de données et au moins une mémoire élastique (10) pour la mémorisation temporaire des données arrivantes et à transmettre,
    b) un comparateur (20) pour déterminer une différence de phase entre un signal de cadence des données entrantes et la source de signaux de cadence (7),
    c) un générateur (15, 16) de trames comportant un circuit (15, 16) de commande des bits de remplissage,
    caractérisé par
    d) un circuit pour déterminer une fréquence différentielle qui existe entre les signaux de cadence,
    e) une mémoire comportant respectivement une courbe de modulation pour chacun de plusieurs segments prédéterminés, et
    f) un circuit pour déterminer, celui des segments dans lequel est située la fréquence différentielle, de manière à utiliser en tant que seuil la courbe de modulation prédéfinie de façon correspondante, en fonction du segment déterminé.
EP96913426A 1996-05-21 1996-05-21 Procede de remplissage pour la transmission plesiochrone de donnees Expired - Lifetime EP0953239B1 (fr)

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PCT/CH1996/000197 WO1997044923A1 (fr) 1996-05-21 1996-05-21 Procede de remplissage pour la transmission plesiochrone de donnees

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EP0953239B1 true EP0953239B1 (fr) 2004-11-24

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EP (1) EP0953239B1 (fr)
AT (1) ATE283588T1 (fr)
AU (1) AU722136B2 (fr)
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WO (1) WO1997044923A1 (fr)

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Publication number Priority date Publication date Assignee Title
US6952826B1 (en) * 1999-10-21 2005-10-04 Sony Corporation Method for implementing a multi-level system model for deterministically handling selected data
US6904111B1 (en) * 2000-03-01 2005-06-07 Northrop Grumman Corporation Asynchronous resampling for data transport
JP3478228B2 (ja) * 2000-03-07 2003-12-15 日本電気株式会社 速度変換回路及びその制御方法
US6944190B1 (en) 2000-09-14 2005-09-13 Ciena Corporation Methods and apparatuses for serial transfer of SONET framed data between components of a SONET system
US7023100B2 (en) * 2003-12-15 2006-04-04 Glycon Technologies, L.L.C. Method and apparatus for conversion of movement to electrical energy
US7489675B2 (en) * 2005-09-12 2009-02-10 Motorola, Inc. Method for indicating padding in a digital mobile radio system
US10957445B2 (en) 2017-10-05 2021-03-23 Hill-Rom Services, Inc. Caregiver and staff information system
US10672098B1 (en) * 2018-04-05 2020-06-02 Xilinx, Inc. Synchronizing access to buffered data in a shared buffer

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Publication number Priority date Publication date Assignee Title
CA1262173A (fr) * 1986-05-29 1989-10-03 James Angus Mceachern Synchronisation de signaux de donnees asynchrones
US5111485A (en) * 1990-05-18 1992-05-05 Northern Telecom Limited Method of and circuit for synchronizing data
US5268935A (en) * 1991-12-20 1993-12-07 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
US5563891A (en) * 1995-09-05 1996-10-08 Industrial Technology Research Institute Waiting time jitter reduction by synchronizer stuffing threshold modulation

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US6470033B1 (en) 2002-10-22
ATE283588T1 (de) 2004-12-15
AU5643296A (en) 1997-12-09
DE59611151D1 (de) 2004-12-30
AU722136B2 (en) 2000-07-20
WO1997044923A1 (fr) 1997-11-27
EP0953239A1 (fr) 1999-11-03

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