EP0931354A1

EP0931354A1 - Power mos component

Info

Publication number: EP0931354A1
Application number: EP97941862A
Authority: EP
Inventors: Martin Kerber
Original assignee: Siemens AG
Current assignee: Infineon Technologies AG
Priority date: 1996-09-30
Filing date: 1997-09-01
Publication date: 1999-07-28
Also published as: JP2001501372A; DE19640308A1; KR20000048749A; WO1998015011A1

Abstract

A power MOS component comprising a source, drain, gate and channel controlled by the gate. Channel is formed by pillars (5). Diameter of pillars (5) is so small that their charge carrier concentration is fully depleted. No field intensity peaks occur on lower edge of pillars because of complete depletion of pillars (5). Breakdown voltage is therefore solely determined by dopant profile in substrate 1. Also disclosed is a method for the production of such a component.

Description

description

Power MOS device

The invention relates to a power MOS component having a source, drain, gate and a channel controlled by the gate. Furthermore, the invention relates to a method for producing such a component.

Such semiconductor components, which are used to switch large electrical powers, must insulate high voltages in the open state and, in the closed state, allow the greatest possible current density with a small voltage drop. Furthermore, the control performance should be as small as possible.

Bipolar transistors are often used to implement such power semiconductors if a high current density and a low series resistance are required.

Field effect transistors are used in particular when a small control power is required. Field effect transistors are used in a number of different forms as power semiconductors. In VMOS power semiconductors, for example, V-shaped trenches with (111) oriented crystal surfaces are exposed by anisotropic etching with KOH. A gate oxide is grown on this and a control gate is applied. In contrast, with DMOS transistors, a current from the source is laterally under a control gate and then vertical to the drain, which is from

Substrate is formed, led. In this case, the control gate is therefore implemented on the semiconductor surface of an n-doped wafer. The local p-well of the MOS transistor is formed by deep boron doping at the source. One problem that occurs again and again with such power semiconductors is insufficient insulation strength, which occurs due to field peaks in the component. Furthermore, it is problematic to simultaneously realize a high current density with a corresponding dissipation of the power loss.

The invention is based on the objective of creating a component of the type mentioned at the outset which has a high insulation strength, in particular due to the avoidance of field peaks. Furthermore, the invention has for its object to provide a method for producing such a component.

To solve this problem, the channel of the component

Columns whose cross-section is so small at least in one direction that the columns are completely depleted with regard to their charge carrier concentration.

Due to the complete depletion, no field peaks occur at the lower edge of the column, so that the insulation strength and the breakdown voltage are only determined by the dopant profile in the substrate. Due to the complete depletion of the columns, ideal control behavior is also achieved due to a very large sub-threshold slope (control voltage through drain current) of 60 mV per decade.

The columns and the entire component are preferably manufactured using silicon technology, the cross section of the columns being approximately 0.2 μm in one direction in order to achieve complete depletion.

In a preferred embodiment, the columns are essentially square in cross section. A wall-shaped formation is also possible, as long as the "wall thickness" is so thin is that complete depletion is reached. With the preferred square or round cross section of the columns, the columns can be arranged periodically on a surface, so that a true symmetrical three-dimensional structure is made possible. This also enables a full-surface, self-positioned and therefore low-impedance source contact.

The columns are preferably about one micron high. The columns are advantageously arranged very close to one another so that a very high current density can be achieved. The distance between the columns can be reduced to the distance that can be achieved in terms of process technology. This is usually the fineness of structure F. The width of the columns is also approximately 1F, but can be further reduced using additional spacer techniques. In a preferred embodiment, the gate consists of polysilicon arranged between the columns, as a result of which a low gate resistance is achieved. The polysilicon of the gate is preferably doped in a p-conducting manner, so that the work function of the gate electrode ensures a sufficiently high threshold voltage even with completely depleted columns.

To produce such a power MOS component, a p-doped layer is produced on a heavily n-doped semiconductor substrate, which forms a drain, and a hard mask is applied to the p-doped layer and structured, an isotropic etching for production performed by columns in the p-doped layer, which oxidizes the columns and a structure produced in the area of the etching to produce a gate oxide, the structure formed by the etching is filled with polysilicon and etched back isotropically, so that the columns are exposed in an upper area the upper area is covered by a nitride spacer, the polysilicon is oxidized or a planarizing oxide is applied, the nitride is removed and in the upper area Region of the column produces an n-doped source region by the ^¬ plantation.

A preferred exemplary embodiment of the invention is explained in more detail below on the basis of a schematic drawing. The schematic representations in detail in

Figures 1 to 7 different stages of the manufacturing process according to the invention;

FIG. 8 shows a two-dimensional dopant distribution along the axis of symmetry through the silicon column;

FIG. 9 shows a dopant profile along the axis of symmetry through the silicon column;

FIG. 10 shows a potential distribution at a 10 V drain voltage;

FIG. 11 shows an enlarged section from FIG. 10;

Figure 12 shows a potential distribution at 50V drain voltage and

Figure 13 is a reverse current characteristic.

A lightly n-doped layer 2 of a few μm thickness is epitaxially grown on a heavily n-doped semiconductor wafer, which is referred to below as substrate 1. The epitaxial layer is then redoped in the area of the vertical MOS transistors to be formed later by implantation.

Alternatively, the epitaxial layer can also be doped accordingly. This state of the process is shown in FIG. represents, the arrows 3 in the upper region indicate the channel implantation.

Nitride is applied to the epitaxial layer 2 using a CVD (Chemical Vapor Deposition) process to form a hard mask and structured using a photo technique or spacer technique. For this purpose, a mask is first applied and the nitride outside the mask is removed using a RIE (reactive ion etching) technique. The mask material is then removed, so that only the nitride mask designated by 4 in FIG. 2 remains. The nitride mask 4 is used to produce columns in the epitaxial layer 2. The lateral dimensions of this nitride mask 4 are so small in at least one direction that the silicon columns 5 structured with them are completely depleted. As shown in FIG. 3, with this nitride mask 4 the exposed epitaxial layer is etched approximately one μm by an isotropic RIE etching.

A gate oxide 6 is now produced on the entire structure, with the exception of the top surfaces of the silicon columns 5. Polysilicon is deposited thereon to form a gate 7, so that the spaces between the silicon columns 5 are completely filled. The thickness of the gate oxide 6 must be matched to the maximum control voltage at the gate 7. The polysilicon is deposited using a CVD technique and doped with p-type boron. The polysilicon is etched back isotropically by reactive ion etching (RIE) to such an extent that the upper region of the silicon column 5 is exposed. This process state is shown in FIG. 4.

In the next step, the free-standing parts of the silicon columns 5 are covered by a nitride spacer 8, which is produced by chemical deposition from the vacuum (Chemical Vapor Deposition) nitride is deposited and the nitride spacers 8 are generated by reactive ion etching. These nitride spacers 8 are shown in FIG. 5.

In the next steps, shown in FIG. 6, the polysilicon, which forms the gate 7, is oxidized to such an extent that sufficient insulation for the source metallization is ensured. This oxide layer is designated 9. As an alternative to self-aligned polysilicon oxidation, a planarizing oxide (e.g. BPSG, i.e. boron phosphor silicate glass) can be applied and etched back.

Finally, and shown in FIG. 7, the nitride on the tips of the silicon columns 5 is removed and these areas are either n-conductively doped with arsenic with sufficiently high energy or laterally at an oblique angle. The tips of the silicon columns 5 thus form a source region. For electrical contacting, a metal layer 10 is then applied, which is designed over the entire surface and thus ensures a low-ohmic connection and good heat dissipation. The substrate 1 forms the drain, the gate 7 is formed by the polysilicon, which is arranged around the silicon columns 5, which represent the channel, and the source regions are formed by the tips of the silicon column and the metal layer 10.

The mode of operation of the component according to the invention is further illustrated below using exemplary simulation graphics. FIG. 8 shows a section of the three-dimensional column MOS transistor. A distance in μm is indicated on the y-axis, with the 0 point placed at the top of the column and the total height corresponding to a distance of 4 μm. The x-axis also shows a distance in μm on the same scale. The distance from 0 to 4 μ is plotted on the x-axis in FIG. 9, the O point being at the tip of the silicon columns in the source region. The dopant concentration per cm ^{3 is} plotted logarithmically on the y axis. Between the heavily n-doped substrate, which forms the drain, and the weakly doped epitaxial layer, there are four orders of magnitude in the dopant concentration. The column tip, which on the one hand has been doped by implantation, again has a dopant concentration that is an order of magnitude smaller. Due to the small lateral dimensions, this area is also completely impoverished. Due to the arsenic implantation in the tip of the column, a high dopant concentration is present in the uppermost column area, whereby the source area is formed.

10 and 11 potential distributions are plotted at a substrate voltage of 10V. FIG. 11 shows an enlargement of the upper area of FIG. 10. The depletion zone marked 11 is located in the lower column area. In the upper area there is almost accumulation due to the work function of the gate material on the lateral oxide surface. Here the p + doped gate meets the p-well / channel area. Within the silicon column 5 and at the bottom edge of the gate, only voltages occur that are less than approximately IV. As a result, no field peaks occur, which creates problems in other power MOS technologies.

Similar to FIG. 10, a potential distribution is plotted in FIG. 12, but with a substrate voltage of 50V.

A blocking characteristic curve is shown in FIG. 13, the substrate voltage in volts being plotted on the x axis and the substrate current is plotted logarithmically in μA on the y-axis. This means that up to 50V problem-free locking behavior can be achieved. The extent of the potential lines into the highly doped substrate can be seen from FIGS. 10 and 12. Of course, the maximum reverse voltage depends on the thickness of the n-doped epitaxial layer 2 and must be adapted to the requirements.

Claims

claims

1. Power MOS device with source, drain, gate and a channel controlled by the gate, characterized in that the channel has columns (5) whose cross-section is at least in one direction so small that the columns (5) with respect to their charge carrier concentration are completely poor.

2. Component according to claim 1, so that the columns are silicon columns (5) and that the cross section of the silicon columns in one direction is smaller than

0.2 µm.

3. Component according to one of claims 1 or 2, so that the columns (5) are essentially square in cross-section.

4. Component according to one of the preceding claims, that the columns (5) are arranged periodically on a surface.

5. Component according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the columns (5) are about 1 micron high.

6. Component according to one of the preceding claims, characterized in that columns (5) are so close together that the distance between them is only slightly more than a column width.

7. Component according to one of the preceding claims, that the gate (7) has polysilicon arranged between the columns (5).

8. Component according to one of the preceding claims, that the gate (7) is doped p-type.

9. A method for producing a power MOS component according to one of the preceding claims, in which on a heavily n-doped semiconductor substrate (1) which forms a drain, a slightly n-doped layer (2) is generated, the upper region thereof is doped, a hard mask is applied and structured on the layer (2), an isotropic etching for the production of columns (5) is carried out in the layer (2), the columns and a structure produced in the area of the etching for producing a gate oxide ( 6) are oxidized, the structure resulting from the etching is filled with polysilicon and isotropically etched back so that the columns are exposed in an upper region, this upper region is covered by a nitride spacer (8), the polysilicon is oxidized or a planarizing oxide is applied the nitride is removed and an n-doped source region is generated by implantation in the upper region of the columns.