Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
  • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
  • H05K3/041—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by using a die for cutting the conductive material
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
  • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
  • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/03—Conductive materials
  • H05K2201/0302—Properties and characteristics in general
  • H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10227—Other objects, e.g. metallic pieces
  • H05K2201/10295—Metallic connector elements partly mounted in a hole of the PCB
  • H05K2201/10303—Pin-in-hole mounted pins
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10227—Other objects, e.g. metallic pieces
  • H05K2201/10363—Jumpers, i.e. non-printed cross-over connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10621—Components characterised by their electrical contacts
  • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/06—Lamination
  • H05K2203/063—Lamination of preperforated insulating layer
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
  • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
  • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• This invention relates to electrically conductive circuits which include a plurality of layers of conductive material applied to insulative layers in selected patterns by stamping.
• circuits are commonly manufactured by lamination of metal foils onto insulative plastic substrate materials.
• the metal foils are generally chemically etched following a photo-patterning step to yield conductive traces and pads for electronic component attachment.
• This method has been used to fabricate multi- layered circuits (i.e. circuits including a plurality of interconnected circuit layers each including a relatively thin patterned conductive layer (typically up to 70 microns) formed on a layer of insulative material. To increase the current carrying capabilities of these thin conductive layers, wider circuit traces must be utilised.
• stamping processes i.e., processes which do not use any chemical etching or stripping
• a hot-stamping process which employs a stamping die, preferably heated, including a designed pattern of the desired conductive traces for a circuit, and wherein the die is employed to press a thin film of conductive material (often referred to as a stamping foil) into the desired pattern on a poorly conductive substrate.
• stamping foil a thin film of conductive material
• Some potential advantages of the stamping process are that it is a dry process, and may be employed to apply a relatively thick circuit trace to a substrate as well as apply the conductive foil to a three-dimensional (i.e., non-planar) substrate.
• the present invention provides a multi-layer circuit wherein a plurality of layers of conductive material are applied by stamping metallic foils into desired patterns on layers of insulative material, aligning the patterned conductive layers, and interconnecting the conductive layers as desired to form a multi-layer circuit.
• the conductive layers may be defined in selected patterns and applied to an insulative layer. Apertures are formed at selected locations on the insulative layer for interconnection of two or more conductive layers, all by stamping a conductive foil on the insulative layer using a suitably designed die.
• a multi ⁇ layer electronic circuit includes a non-planar plastic substrate wherein a conductive layer is stamped into a desired pattern on the substrate, wherein additional other layers of conductive material are pressed into desired patterns on additional layers of insulative material, and wherein the insulative layers and substrate are laminated together in conformance with the non-planar topography of the substrate.
• the multi-layer circuit includes a plurality of layers of conductive material that are stamped into defined patterns on insulating layers and wherein the conductive layers are suitably aligned for interconnection, and wherein the insulating layers are defined with apertures at selected locations which define wells of defined height and volume to provide a controlled stand-off for a solder joint between interconnected conductive layers, or between a subsequently installed component and the mounting pad on one of the conductive layers in the circuit.
• a method embodying present invention comprises applying a layer of conductive material on a layer of insulative material using a stamping die which defines a selected pattern in the conductive layer as it is adhered to the insulative layer, applying another layer of conductive material on another layer of insulative material also using a stamping die which defines a selected conductive pattern for the layer, wherein each of the insulative layers including the layers of patterned conductive material are aligned and adhered together, and interconnecting the layers of conductive material at selected locations.
• the layer of conductive material is preferably a metal foil.
• the stamping die is also preferably heated so that, upon the application of pressure and heat during stamping, the metal foil is adhered to the layer of insulative material simultaneous with the stamping of the desired conductive pattern into the foil.
• the method includes sequential steps of stamping an insulative substrate with the first conductive layer, applying a dielectric material onto the stamped substrate, defining apertures at selected locations in the dielectric material for subsequent component mounting and/or interconnection with other conductive layers, stamping another conductive layer onto the applied dielectric layer, and interconnecting the first and second conductive layers where desired.
• an insulative substrate is stamped with a first conductive layer as described above.
• Each of the other plurality of conductive layers are separately stamped onto a layer of insulative material having apertures defined at preselected locations. It will be appreciated that, in this embodiment of the method, the stamping of the conductive layers on the various substrate and insulative layers may be performed in any sequence, or simultaneously.
• the pre-stamped insulative layers are then aligned and adhered to the substrate, and layer-to-layer interconnection of the conductive layers is performed to complete the multi-layer circuit.
• the method includes the step of defining apertures at selected locations in the insulative layers by stamping the aperture into the layer using a suitably designed die prior to or simultaneously with stamping the patterned conductive material onto that insulative layer.
• the present invention provides a multi-layer circuit in which each of a plurality of layers of patterned conductive material are formed by stamping the conductive material onto an insulative layer including apertures defined at selected locations, and electrical interconnection of the otherwise separated conductive layers as desired, to form an electronic circuit on a substrate which may be non-planar and which may include previously moulded-in structural features such as integral connectors, attachment clips and housings.
• Figure 1 is a chart illustrating the method of the present invention
• Figure 2 is a perspective exploded view of the multi ⁇ layer circuit of the present invention.
• Figure 3 is a perspective view of the multi-layer circuit shown in Figure 2;
• Figure 4 is a cross-sectional view of the multi-layer circuit of Figures 2 and 3 taken along line 4-4;
• Figure 5 is a partial cross-sectional view of a non- planar multi-layer circuit
• Figure 6 is a chart illustrating the steps employed in one embodiment of the method of the present invention.
• Figure 1 is a chart illustrating the steps employed in another embodiment of the method of the present invention.
• Figure 8 is a schematic cross-sectional diagram of a multi-layer circuit according to one embodiment of the invention.
• Figure 9 is a schematic cross-sectional diagram of a multi-layer circuit illustrating an aperture formed in a conductive layer and an insulative layer and a component interconnecting two conductive layers;
• Figure 10 is a schematic cross-sectional diagram illustrating two conductive layers of a multi-layer circuit according to the present invention interconnected by a zero Ohm resister component;
• Figure 11 is a schematic cross-sectional diagram of another embodiment of the invention including two conductive layers interconnected by solder or conductive adhesive.
• the method, generally referred to as 10, of making a multi-layer electronic circuit comprises applying a layer of conductive material on a layer of insulative material using a stamping die which defines a selected pattern in the conductive layer as it is adhered to the insulative layer, applying another layer of conductive material on another layer of insulative material also using a stamping die which defines a selected pattern for that conductive layer as it is adhered to the insulative layer and repeating the steps of stamping conductive layers to define patterns and adhere the layers to additional insulative layers until the desired number of conductive layers is obtained.
• Each of the conductive layers is suitably aligned so that the layers may be laminated together into a multi-layer structure wherein the layers of conductive material are sandwiched between at least one layer of insulative material.
• the layers of conductive material are interconnected m various ways, as described hereinafter, to obtain a multi ⁇ layer electronic circuit in a dry manufacturing process that eliminates the plating and etching steps typically associated with fabrication of multi-layer circuits. It should be appreciated that by applying the conductive layers to each of the insulative layers using the stamping (and, preferably hot stamping) process, relatively thicker circuit conductors (up to 250 microns) may be obtained on selected layers to provide increased current carrying capability without increasing the width of the conductor paths. It should also be appreciated that the manufacturing steps described above and shown in Figure 1 may be performed in various sequences, and, as well, may include additional steps, as hereinafter described, all without departing from the spirit of the invention.
• Figures 2-4 illustrate one embodiment of the multi ⁇ layer circuit 30 of the present invention, comprising a substrate 32 which is preferably formed of an insulative thermoset or thermoplastic material and provides the primary structural definition for the finished circuit.
• a layer of conductive material 34 is stamped with a die having a design suitable to define a desired conductive pattern in the layer 34, as well as adhere the layer 34 to the substrate 32.
• Layer 34 may comprise any film or sheet of a highly conductive material having physical characteristics suitable for defining a desired electrically conductive trace pattern and simultaneously bonding that pattern to the substrate (or other insulative layer) by the application of pressure and/or heat from a stamping die using a conventional hot stamping process employed to apply such conductive trace patterns to substrates to form single layer circuits.
• the heat stamping process may, for example, employ a vertical stamping press (such as a 40 ton press available from Baier Pragepressen-münfabrik of Rudersberg, Germany) which, in turn, utilises a plurality of interchangeable stamping dies which have been engraved to define the appropriate conductive trace pattern on the conductive material as it is stamped onto the insulative layer.
• a vertical stamping press such as a 40 ton press available from Baier Pragepressen-münfabrik of Rudersberg, Germany
• the layer of conductive material is preferably a metallic foil. Any hot-stamping foil may be used, depending on the desired circuit properties, including copper, copper/nickel, copper/tin-lead, etc. Metallic foils suitable for application in existing stamping processes may be up to about 150 microns thick.
• the layer 34 is adhered to the substrate 32 simultaneously with the stamping of the trace pattern by the application of pressure and/or heat from the stamping die. This adhesion may be achieved through mechanical bonding where, for example, the pressure and heat from the stamping die is adequate to bond the metal foil to a thermoplastic layer.
• stamping the metallic foil with a heated die may initiate a chemical bonding between the conductive layer 34 and the substrate 32 by additionally employing any of a wide variety of known adhesives to the foil and/or insulative layer.
• adhesives including thermoplastics
• thermoplastics may be employed and activated by sufficiently heating the stamping die so that the pressure and heat applied to the metallic foil is adequate to activate the adhesive and bond the metallic foil to the substrate.
• various adhesives may be employed, depending on the type of conductive film and insulative substrate, to achieve an adequate bonding of the conductive traced onto the substrate using a conventional hot stamping process .
• Another layer of conductive material 36 is applied to another layer of insulative material 38, again by hot stamping the desired conductive pattern and bonding the conductive material 36 to the insulative layer 38.
• insulative material 38 may be adhered to the substrate (or to other insulative layers) by various known techniques, such as by bonding an insulative film, or by curtain-coating, screen- printing, etc.
• Apertures 40, 42, 44 are preferably defined in layer 38 at selected locations where interconnection of the conductive trace 36 with conductive layer 34 is desired.
• apertures may be obtained using known screen printing processes. Alternatively, or in addition, the apertures may be stamped into the layer where desired, by employing a stamping die having suitably designed cleats or protuberances for stamping the apertures in the insulative layer.
• Each of the conductive layers 34, 36 are interconnected, and/or are connected to other components which are integrally moulded into the substrate or mounted on the finished multi-layer circuit by using a variety of connection techniques that will be described in additional detail hereinafter. It will also be appreciated that internal conductive layers may be selectively exposed to provide access for test probes and other components, as well as for providing the above-described layer-to-layer interconnection.
• a suitably shaped stamping die may be employed to conform and adhere a desired conductive trace pattern by stamping a metal foil 46 on a three- dimensional (i.e., non-planar) insulative substrate 48.
• additional multiple circuit layers may also be fabricated in conformance with the non-planar shape of the substrate 48 by stamping metal foils 50 on insulative films 52.
• the multiple circuit layers are again appropriately interconnected, to achieve three-dimensional multi-layer circuits.
• each of the plurality of circuit layers is separately fabricated by stamping a metallic foil to define a desired conductive pattern and adhere the patterned metal foil to an insulative layer as previously described.
• each of the circuit layers are then properly aligned and laminated on top of the substrate using conventional material bonding techniques.
• a metallic foil preferably ranging in thickness between about .0014 to .0012 inches (about 35 to 28 microns) is stamped on insulative film ranging m thicknesses of about .001 to .015 inches (about .254 to 3.81 millimetres) to obtain the individual circuit layers.
• the substrate is a dielectric material, such as a thermoset or thermoplastic
• the substrate itself may be stamped to form a circuit trace.
• the method of Figure 6 may be employed using a conductive substrate by either coating- the substrate with a dielectric prior to stamping a circuit trace thereon, or by laminating the other stamped insulative film layers to the unstamped conductive substrate. After the multi-layer circuit has been laminated, or prior to lamination where appropriate, the layers of conductive material are interconnected, and the desired components added to the circuit, to complete the multi-layer circuit. It will be appreciated that the method of Figure 6 is particularly efficient since it allows for simultaneous fabrication of the multiple circuit layers to the extent that multiple presses are available.
• the layers of insulative film may be formed to conform to the shape of the substrate either prior to or after the conductive trace pattern is stamped thereon, by pressing the insulative film on a suitably shaped mould (or between two suitably shaped matching dies) prior to alignment and lamination of the multiple circuit layers onto the similarly shaped substrate.
• Figure 7 illustrates an alternative embodiment 14 of the method of the present invention which may be efficiently employed to fabricate multi-layer circuits where, for example, a single press, or a limited number of presses, are available.
• a conductive layer such as a metallic foil
• a conductive layer is heat stamped to define and adhere a patterned circuit trace on an insulative substrate (or on a conductive substrate which is suitably coated with a dielectric material) to form the first circuit layer.
• a second insulative layer is then added.
• any of a variety of conventional techniques may be employed to add the insulative layer and to define apertures m the added layer where appropriate to expose the circuit trace below the added layer for subsequent interconnection to one of the upper conductive layers or to a component mounted on the finished circuit.
• the stamping die is then changed, and the desired conductive pattern is stamped on the insulative layer.
• the steps 16 of adding insulative layers, defining apertures where appropriate for interconnection, and stamping the next added insulative layer is repeated until the desired number of circuit layers is obtained. Again, the layers are interconnected as desired, and components added, to form the completed circuit.
• Figure 8 schematically illustrates a multi-layer circuit 60 which may be fabricated by any of the above- described methods.
• any selected internal conductive layer such as layer 62
• the apertures such as 66
• the apertures may be fabricated to desired heights to provide a controlled stand-off between the component 64 and the mounting pad on conductive layer 62.
• the efficiency of the solder connection may be optimised.
• FIG. 9 illustrates an alternative method of interconnection which may be employed in the present invention.
• a stamping die may be provided with a small cleat or other feature suitable to punch through one layer 74 of conductive material, the layer 76 of insulating material to which conductive layer 74 is adhered, and any intervening layers (not shown) to expose a lower layer 78 of conductive material for interconnection of the layers 74 and 78.
• the stamping die which defines the pattern and adheres the conductive layer 74 to the insulative layer 76 may include this aperture-defining feature so that the apertures may be defined simultaneous with application of the metallic foil to insulative layer 76 m one stamping step.
• the interconnection of conductive layers 74 and 78 may be achieved by utilising any of the above-described methods, or by inserting a suitably designed connector pin 80 which can be picked and placed as required at an appropriate time during the fabrication process.
• Figure 10 illustrates interconnection of conductive layers 34 and 36 through aperture 40 (as shown in Figure 2) using a subsequently mounted component 70, such as a zero Ohm resistor.
• Figure 11 shows an alternative form of interconnection of the same conductive layers 34 and 36 using solder or conductive adhesive 72 applied between the layers in aperture 40.
• the present invention provides a method of fabricating a multi-layer circuit employing a hot stamping process for applying the conductive layers in desired trace patterns on insulative layers to quickly and efficiently form complex flat or three- dimensional circuits.
• the method further allows for ease of interconnection of internal layers and/or exposure of selected conductive layers for subsequent access by test probes or connection of components. Controlled stand-offs may be provi ⁇ ed to insure for efficient solder connections between components and internal layers.
• integral three-dimensional structural features, such as connectors, clips, housings, etc. may be moulded into the substrate, since the process is not limited to planar applications.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)
• Manufacturing Of Printed Wiring (AREA)

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• 1997
  • 1997-05-01 EP EP97918271A patent/EP0908077A1/de not_active Withdrawn
  • 1997-05-01 WO PCT/GB1997/001181 patent/WO1997042800A1/en not_active Application Discontinuation

Non-Patent Citations (1)

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