EP0905778A2 - Verbesserte Mehrlagenleitungsstruktur und Verfahren dafür - Google Patents
Verbesserte Mehrlagenleitungsstruktur und Verfahren dafür Download PDFInfo
- Publication number
- EP0905778A2 EP0905778A2 EP98116755A EP98116755A EP0905778A2 EP 0905778 A2 EP0905778 A2 EP 0905778A2 EP 98116755 A EP98116755 A EP 98116755A EP 98116755 A EP98116755 A EP 98116755A EP 0905778 A2 EP0905778 A2 EP 0905778A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- conductive
- dielectric
- dielectric layer
- low capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US939208 | 1992-09-01 | ||
US08/939,208 US5977635A (en) | 1997-09-29 | 1997-09-29 | Multi-level conductive structure including low capacitance material |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0905778A2 true EP0905778A2 (de) | 1999-03-31 |
EP0905778A3 EP0905778A3 (de) | 2001-02-07 |
Family
ID=25472743
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98116755A Ceased EP0905778A3 (de) | 1997-09-29 | 1998-09-04 | Verbesserte Mehrlagenleitungsstruktur und Verfahren dafür |
Country Status (6)
Country | Link |
---|---|
US (1) | US5977635A (de) |
EP (1) | EP0905778A3 (de) |
JP (1) | JPH11163142A (de) |
KR (1) | KR100544030B1 (de) |
CN (1) | CN1134837C (de) |
TW (1) | TW393753B (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7656037B2 (en) | 2005-09-21 | 2010-02-02 | Infineon Technologies Ag | Integrated circuit with improved component interconnections |
US7667256B2 (en) | 2005-09-21 | 2010-02-23 | Infineon Technologies Ag | Integrated circuit arrangement having a plurality of conductive structure levels and capacitor, and a method for producing the integrated circuit arrangement |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6627539B1 (en) * | 1998-05-29 | 2003-09-30 | Newport Fab, Llc | Method of forming dual-damascene interconnect structures employing low-k dielectric materials |
US6153512A (en) * | 1999-10-12 | 2000-11-28 | Taiwan Semiconductor Manufacturing Company | Process to improve adhesion of HSQ to underlying materials |
US6780783B2 (en) * | 2001-08-29 | 2004-08-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of wet etching low dielectric constant materials |
US20050070103A1 (en) * | 2003-09-29 | 2005-03-31 | Applied Materials, Inc. | Method and apparatus for endpoint detection during an etch process |
WO2017099736A1 (en) * | 2015-12-09 | 2017-06-15 | Intel Corporation | Dielectric buffer layer |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0476625A2 (de) * | 1990-09-18 | 1992-03-25 | Nec Corporation | Halbleiteranordnung mit Verbindungen |
EP0703611A1 (de) * | 1994-08-31 | 1996-03-27 | Texas Instruments Incorporated | Verfahren zur Isolierung von Leitungen unter Verwendung von Materialien mit niedriger dielektrischer Konstante und damit hergestellte Strukturen |
US5559055A (en) * | 1994-12-21 | 1996-09-24 | Advanced Micro Devices, Inc. | Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5310700A (en) * | 1993-03-26 | 1994-05-10 | Integrated Device Technology, Inc. | Conductor capacitance reduction in integrated circuits |
US5548159A (en) * | 1994-05-27 | 1996-08-20 | Texas Instruments Incorporated | Porous insulator for line-to-line capacitance reduction |
DE69531571T2 (de) * | 1994-05-27 | 2004-04-08 | Texas Instruments Inc., Dallas | Verbesserungen in Bezug auf Halbleitervorrichtungen |
US5691573A (en) * | 1995-06-07 | 1997-11-25 | Advanced Micro Devices, Inc. | Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines |
US5847464A (en) * | 1995-09-27 | 1998-12-08 | Sgs-Thomson Microelectronics, Inc. | Method for forming controlled voids in interlevel dielectric |
-
1997
- 1997-09-29 US US08/939,208 patent/US5977635A/en not_active Expired - Lifetime
-
1998
- 1998-08-04 TW TW087112836A patent/TW393753B/zh not_active IP Right Cessation
- 1998-09-04 EP EP98116755A patent/EP0905778A3/de not_active Ceased
- 1998-09-23 CN CNB981207073A patent/CN1134837C/zh not_active Expired - Lifetime
- 1998-09-25 KR KR1019980039852A patent/KR100544030B1/ko not_active IP Right Cessation
- 1998-09-29 JP JP10276112A patent/JPH11163142A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0476625A2 (de) * | 1990-09-18 | 1992-03-25 | Nec Corporation | Halbleiteranordnung mit Verbindungen |
EP0703611A1 (de) * | 1994-08-31 | 1996-03-27 | Texas Instruments Incorporated | Verfahren zur Isolierung von Leitungen unter Verwendung von Materialien mit niedriger dielektrischer Konstante und damit hergestellte Strukturen |
US5559055A (en) * | 1994-12-21 | 1996-09-24 | Advanced Micro Devices, Inc. | Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7656037B2 (en) | 2005-09-21 | 2010-02-02 | Infineon Technologies Ag | Integrated circuit with improved component interconnections |
US7667256B2 (en) | 2005-09-21 | 2010-02-23 | Infineon Technologies Ag | Integrated circuit arrangement having a plurality of conductive structure levels and capacitor, and a method for producing the integrated circuit arrangement |
Also Published As
Publication number | Publication date |
---|---|
TW393753B (en) | 2000-06-11 |
US5977635A (en) | 1999-11-02 |
JPH11163142A (ja) | 1999-06-18 |
CN1134837C (zh) | 2004-01-14 |
EP0905778A3 (de) | 2001-02-07 |
KR19990030133A (ko) | 1999-04-26 |
KR100544030B1 (ko) | 2007-03-02 |
CN1213170A (zh) | 1999-04-07 |
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