EP0810647A3 - Procédé de fabrication d'un dispositif MOS comportant des régions de source et drain saillantes et auto-alignées; dispositif obtenu - Google Patents

Procédé de fabrication d'un dispositif MOS comportant des régions de source et drain saillantes et auto-alignées; dispositif obtenu Download PDF

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Publication number
EP0810647A3
EP0810647A3 EP97107546A EP97107546A EP0810647A3 EP 0810647 A3 EP0810647 A3 EP 0810647A3 EP 97107546 A EP97107546 A EP 97107546A EP 97107546 A EP97107546 A EP 97107546A EP 0810647 A3 EP0810647 A3 EP 0810647A3
Authority
EP
European Patent Office
Prior art keywords
drain
source
self
forming
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97107546A
Other languages
German (de)
English (en)
Other versions
EP0810647A2 (fr
Inventor
Robert T. Fuller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harris Corp
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Publication of EP0810647A2 publication Critical patent/EP0810647A2/fr
Publication of EP0810647A3 publication Critical patent/EP0810647A3/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
EP97107546A 1996-05-28 1997-05-07 Procédé de fabrication d'un dispositif MOS comportant des régions de source et drain saillantes et auto-alignées; dispositif obtenu Withdrawn EP0810647A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/654,393 US5804846A (en) 1996-05-28 1996-05-28 Process for forming a self-aligned raised source/drain MOS device and device therefrom
US654393 1996-05-28

Publications (2)

Publication Number Publication Date
EP0810647A2 EP0810647A2 (fr) 1997-12-03
EP0810647A3 true EP0810647A3 (fr) 1998-07-22

Family

ID=24624674

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97107546A Withdrawn EP0810647A3 (fr) 1996-05-28 1997-05-07 Procédé de fabrication d'un dispositif MOS comportant des régions de source et drain saillantes et auto-alignées; dispositif obtenu

Country Status (5)

Country Link
US (1) US5804846A (fr)
EP (1) EP0810647A3 (fr)
JP (1) JPH1056178A (fr)
KR (1) KR970077373A (fr)
TW (1) TW342521B (fr)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2701763B2 (ja) * 1994-11-04 1998-01-21 日本電気株式会社 半導体装置およびその製造方法
JPH1126757A (ja) * 1997-06-30 1999-01-29 Toshiba Corp 半導体装置及びその製造方法
US5940698A (en) * 1997-12-01 1999-08-17 Advanced Micro Devices Method of making a semiconductor device having high performance gate electrode structure
US6172383B1 (en) 1997-12-31 2001-01-09 Siliconix Incorporated Power MOSFET having voltage-clamped gate
US6268242B1 (en) * 1997-12-31 2001-07-31 Richard K. Williams Method of forming vertical mosfet device having voltage clamped gate and self-aligned contact
KR100481984B1 (ko) * 1997-12-31 2005-07-04 매그나칩 반도체 유한회사 반도체장치및그제조방법
US5963799A (en) * 1998-03-23 1999-10-05 Texas Instruments - Acer Incorporated Blanket well counter doping process for high speed/low power MOSFETs
US6162691A (en) * 1999-03-29 2000-12-19 Taiwan Semiconductor Manufacturing Company Method for forming a MOSFET with raised source and drain, saliciding, and removing upper portion of gate spacers if bridging occurs
KR100338104B1 (ko) 1999-06-30 2002-05-24 박종섭 반도체 소자의 제조 방법
DE19940758A1 (de) * 1999-08-27 2001-03-15 Infineon Technologies Ag Verfahren zur Herstellung eines HF-FET und HF-FET
US6093590A (en) * 1999-09-14 2000-07-25 Worldwide Semiconductor Manufacturing Corp. Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant
TW514992B (en) 1999-12-17 2002-12-21 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
US7391087B2 (en) * 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
US6352899B1 (en) * 2000-02-03 2002-03-05 Sharp Laboratories Of America, Inc. Raised silicide source/drain MOS transistors having enlarged source/drain contact regions and method
US6445050B1 (en) 2000-02-08 2002-09-03 International Business Machines Corporation Symmetric device with contacts self aligned to gate
US6303449B1 (en) * 2000-11-16 2001-10-16 Chartered Semiconductor Manufacturing Inc. Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP
US6306714B1 (en) * 2000-11-16 2001-10-23 Chartered Semiconductor Manufacturing Inc. Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide
JP3669919B2 (ja) * 2000-12-04 2005-07-13 シャープ株式会社 半導体装置の製造方法
US6417054B1 (en) 2001-01-26 2002-07-09 Chartered Semiconductor Manufacturing Ltd. Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide
US6570235B2 (en) * 2001-03-20 2003-05-27 Macronix International Co., Ltd. Cells array of mask read only memory
US6869850B1 (en) * 2002-12-20 2005-03-22 Cypress Semiconductor Corporation Self-aligned contact structure with raised source and drain
US7323377B1 (en) 2004-03-26 2008-01-29 Cypress Semiconductor Corporation Increasing self-aligned contact areas in integrated circuits using a disposable spacer
US7663237B2 (en) * 2005-12-27 2010-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Butted contact structure
US7384833B2 (en) * 2006-02-07 2008-06-10 Cypress Semiconductor Corporation Stress liner for integrated circuits
US7745275B2 (en) * 2008-09-10 2010-06-29 Arm Limited Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region
DE102010002411B4 (de) * 2010-02-26 2012-10-31 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung von Kontaktbalken mit reduzierter Randzonenkapazität in einem Halbleiterbauelement
US9287313B2 (en) 2013-03-12 2016-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Active pixel sensor having a raised source/drain

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0043943A2 (fr) * 1980-07-08 1982-01-20 International Business Machines Corporation Procédé pour la fabrication de circuits intégrés à transistors à effet de champ comportant une configuration de régions diélectriques à dimensions étroites et structures fabriquées selon ce procédé
FR2568723A1 (fr) * 1984-08-03 1986-02-07 Commissariat Energie Atomique Circuit integre notamment de type mos et son procede de fabrication
EP0709880A2 (fr) * 1994-10-31 1996-05-01 STMicroelectronics, Inc. Méthode pour former des régions de source/drain saillantes dans un circuit intégré

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4822749A (en) * 1987-08-27 1989-04-18 North American Philips Corporation, Signetics Division Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
US5057902A (en) * 1987-12-02 1991-10-15 Advanced Micro Devices, Inc. Self-aligned semiconductor devices
US4983536A (en) * 1989-11-24 1991-01-08 Gte Laboratories Incorporated Method of fabricating junction field effect transistor
US5397722A (en) * 1994-03-15 1995-03-14 National Semiconductor Corporation Process for making self-aligned source/drain polysilicon or polysilicide contacts in field effect transistors
US5439839A (en) * 1994-07-13 1995-08-08 Winbond Electronics Corporation Self-aligned source/drain MOS process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0043943A2 (fr) * 1980-07-08 1982-01-20 International Business Machines Corporation Procédé pour la fabrication de circuits intégrés à transistors à effet de champ comportant une configuration de régions diélectriques à dimensions étroites et structures fabriquées selon ce procédé
FR2568723A1 (fr) * 1984-08-03 1986-02-07 Commissariat Energie Atomique Circuit integre notamment de type mos et son procede de fabrication
EP0709880A2 (fr) * 1994-10-31 1996-05-01 STMicroelectronics, Inc. Méthode pour former des régions de source/drain saillantes dans un circuit intégré

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"SELF-ALIGNED GATE MOSFETS WITH LOW-TEMPERATURE GATE MATERIAL", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 31, no. 10, March 1989 (1989-03-01), pages 361 - 363, XP000050587 *
LEE V V ET AL: "A SELECTIVE CVD TUNGSTEN LOCAL INTERCONNECT TECHNOLOGY", INTERNATIONAL ELECTRON DEVICES MEETING, SAN FRANCISCO, DEC. 11 - 14, 1988, no. -, 11 December 1988 (1988-12-11), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 450 - 453, XP000013971 *
SEKINE M ET AL: "SELF-ALIGNED TUNGSTEN STRAPPED SOURCE/DRAIN AND GATE TECHNOLOGY REALIZING THE LOWEST SHEET RESISTANCE FOR SUB-QUARTER MICRON CMOS", 1995 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN AND CYBERNETICS, VANCOUVER, OCT. 22 - 25, 1995, vol. VOL. 1, 22 October 1995 (1995-10-22), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 493 - 496, XP000585540 *

Also Published As

Publication number Publication date
US5804846A (en) 1998-09-08
KR970077373A (ko) 1997-12-12
TW342521B (en) 1998-10-11
EP0810647A2 (fr) 1997-12-03
JPH1056178A (ja) 1998-02-24

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