EP0779768A2 - Process and circuit for operating a discharge lamp - Google Patents

Abstract

The load circuit contains the lamp (EL) with a parallel capacitor (C5), a series choke (L2), a capacitor (C6) and a current-measuring resistance (R2). In the preheating phase the load current is measured, an invariant desired value worked out and a clock generator activated at a free-running frequency between the pole values for lamp ignition and extinction. The ignition phase begins with load current measurement and derivation of a variable set-point. The clock generator is synchronised to the invertor frequency. This phase ends with the set-point attaining a value at which the conduction time of a half-bridge exceeds the free-running clock period.

Description

The invention relates to a method and a circuit arrangement for operating a discharge lamp according to the preamble of claims 1 and 2 or according to claim 11.

The mains voltage is rectified and smoothed in lamp ballasts for the high-frequency operation of low-pressure discharge lamps. This DC voltage is usually converted into a high-frequency AC voltage using an inverter, which is preferably designed as a half-bridge arrangement, and is used to supply the lamp with electrical energy via a series resonant circuit arrangement.

In the case of such circuits, the switching elements are to be supplied with a drive power in time with the switching frequency.

In the power range up to 25W, so-called free-floating circuit concepts are usually used almost exclusively, which either control separate switching elements (in particular transistors) of the inverter or the half bridge or separate current transformers (saturation current transformers or as transformers with a defined air gap) or secondary windings on the lamp choke with signal-converting ones Provide networks for each half-bridge switch. "Free swinging" in this context means that the control power for the switching elements of the inverter is taken directly from the load circuit.

However, these free-swinging circuit concepts have the disadvantage that losses in the control circuits (saturation current transformers, secondary windings on the lamp choke with signal-converting networks) impair the efficiency of the overall arrangement and that a relatively large number of components (control circuit components) are required.

Advances in semiconductor technology enable integrated circuit and control concepts in which the control of the two half-bridge transistors can be implemented in an integrated circuit. The drive power for the transistors is provided by drivers that are controlled by digital signals. These circuit concepts are termed "externally controlled".

Previously known embodiments for externally controlled half-bridges with integrated control use oscillators, which usually switch the switching elements (usually voltage-controlled transistors such as FET transistors (field effect transistor) or IGBT transistors (insulated gate bipolar transistor)) of the inverter via drivers with a fixed, unregulated frequency. and switch off.

With such solutions, in which only one oscillator frequency can be specified, however, without a component that varies the natural resonance frequency of the load circuit (for example, PTC thermistor in parallel with part or all of the lamp-parallel capacitance (C5 in FIG. 1), cf. EP 0 185 179 B1) preheating the lamp filaments is almost impossible.

With alternative solutions to this, in which one or more further fixed oscillator frequencies are specified for preheating, an optimal preheating of the lamp filaments cannot be achieved before the lamp is ignited for the reasons explained below.

To preheat the Wendein, the frequency of the inverter must be selected in accordance with the quality curve of the load circuit so that it lies within a certain frequency range. If the frequency of the inverter is above the upper limit of this frequency range, the current flowing in the load circuit is not sufficient to heat the lamp filaments to a temperature at which they are able to emit, given a fixed preheating duration. If the frequency of the inverter is below the lower limit of this frequency range, the voltage applied to the capacitor (C5) connected in parallel to the lamp (cf.EL in FIG. 1) will be greater than a maximum value defined by the lamp (EL), resulting in the lamp igniting prematurely follows.

The quality curve of the load circuit depends on the frequency-determining and usually tolerant components in the load circuit (choke L2, capacitors C5 and C6) as well as the damping in the load circuit caused by ohmic resistances (mainly spiral resistances and effective resistance of choke L2).

A fixed control frequency of the oscillator in previously known embodiments is specified with components that are also subject to tolerance.

Without comparing the oscillator frequency to the load circuit quality curve currently present in a ballast, the required tolerances of the electronic components of the load circuit can be taken as a basis Frequency for preheating cannot be reliably implemented. However, an individual comparison of each ballast in production is hardly feasible for cost reasons. Since the resistance of the filaments increases as they heat up over time, the damping in the load circuit also increases. If the oscillator frequency remains constant in the course of the preheating, the current in the load circuit decreases in accordance with the decrease in the quality of the load circuit.

An improved preheating could be achieved in that the frequency of the inverter is reduced during the preheating so that the current in the load circuit remains almost constant during the entire preheating phase. However, this is not possible with a fixed oscillator frequency.

gegeben ist, muß einen Wert aufweisen, der es ermöglicht, mit der gleichen Oszillatorfrequenz, mit der der Inverter während dem normalen Lampenbetrieb arbeitet, eine ausreichende Spannung über dem der Lampe parallel geschalteten Kondensator (C5 in Figur 1) zu erzeugen. Damit hat der Kondensator (C5) eine unüblich hohe Kapazität aufzuweisen mit der Folge, daß während dem normalen Lampenbetrieb ein hoher Strom in den Lampenwendeln fließt. Abgesehen davon, daß ein Kondensator mit der genannten hohen Kapazität vorzusehen ist, besteht ein weiterer Nachteil darin, daß die Wendein übermäßig belastet werden und der Gesamtwirkungsgrad der Anordnung sinkt.Another disadvantage of the known solutions with a single fixed operating frequency of the inverter results from the following consideration: The pole point of the load circuit, which by $${\mathit{\text{f}}}_{\mathit{\text{res1}}}\text{=}\frac{\mathit{\text{1}}}{\mathit{\text{2nd}}\text{π}\sqrt{\mathit{\text{L2}}\text{·}\frac{\mathit{\text{C5}}\text{·}\mathit{\text{C6}}}{\mathit{\text{C5}}\text{+}\mathit{\text{C6}}}}}$$

given, must have a value which makes it possible to generate a sufficient voltage across the capacitor connected in parallel with the lamp (C5 in FIG. 1) with the same oscillator frequency with which the inverter operates during normal lamp operation. The capacitor (C5) thus has an unusually high capacitance, with the result that a high current flows in the lamp filaments during normal lamp operation. Apart from the fact that a capacitor with the above-mentioned high capacitance is to be provided, there is a further disadvantage in that the Wendein become excessively loaded and the overall efficiency of the arrangement drops.

Based on this state of the art, the object of the invention is to provide a method and a circuit arrangement of the type mentioned at the outset, which enable adequate preheating of the lamp filaments when the switching elements of the inverter are externally controlled.

This object is achieved by a method and by a circuit arrangement, which are defined in the claims.

The invention has a number of advantages.

A first practically important advantage is the simple circuitry feasibility. All control functions can be implemented in an integrated circuit. The functions required by the proposed method can be implemented in terms of circuitry in such a way that only relatively inexpensive resistors are required for external circuitry of this integrated circuit for setting operating parameters.

A second important advantage of the proposed method is that a majority of the functions to be implemented in terms of circuitry in a circuit arrangement can be used in all operating phases of the lamp, and therefore only the parameters typical of the operating phase are specified for each phase.

A further advantageous embodiment of the method according to the invention is characterized in that each individual period of the current in the load circuit is regulated to a predefinable setpoint in each operating phase. This makes it simple, robust and largely non-tolerant Control principle created, since instead of the otherwise used tolerance-affected control characteristics, only simple comparison functions are required.

In this connection, it is advantageously provided that positive and negative half-waves of the current in the load circuit are regulated to the same setpoint. By specifying the same setpoint for positive and negative half-waves of the load current, it is inherently ensured that tolerances in the setpoint formation have the same effect on positive as on negative half-waves of the load current and thereby the ratio between the duty cycles of the two half-bridge switching elements (transistors T1, T2 ) remains constant. This advantage is supplemented by the further advantage that the formation of a setpoint is simpler in terms of circuitry than the generation of two separate setpoints for positive and negative load current half-waves.

In this context, it is provided that in order to regulate the period of the current in the load circuit, the actual value of the current-time area of a half oscillation or an oscillation of the load current is recorded and that this area with the target value of the current-time area of a half oscillation or a vibration of the load current in the current operating phase is compared. If the actual and target values match, the inverter is activated in such a way that a switching element that has just been activated (for example T2) is deactivated and a switching element that is not currently activated (for example T1) is activated. As a control criterion, it is sufficient to exceed the actual value above the setpoint to change the state of the inverter. By recording the actual current-time area and comparing it with a target current-time area, the currently activated switching element is automatically deactivated at the point in time required to fulfill the control target, based on the time profile of the current in the load circuit.

In this context, it is further provided that a predeterminable dead time is realized between the deactivation of the switching element that is currently activated and the activation of the switching element that is not currently activated. This dead time enables the switching elements to be relieved, e.g. by connecting at least one capacitor in parallel to at least one of the two switching elements. This limits the voltage gradient dU (t) / dt occurring at the half-bridge center (connection 9 in FIG. 1) when the half-bridge is switched. Neither of the two half-bridge switching elements is activated in the time in which these capacitance (s) are recharged by the energy stored in the choke (L2), starting with the deactivation of the currently activated switching element.

According to the invention, it can further be provided in this context that in a first period of a start-up phase immediately after the end of the ignition phase, a third time-constant setpoint value of the load current is formed for a predeterminable third period. By specifying the third setpoint after the ignition phase has ended, an increased current can be applied to the load circuit for a predefinable period. An accelerated starting behavior of the lamp and thus a faster reaching of the nominal luminous flux is achieved.

In this context, it is further provided that a second time-variable setpoint is formed in a second period of the start-up phase, which is continuously converted from the third time-constant setpoint into the second time-constant setpoint. The continuous transfer of the third setpoint to the second setpoint achieves a continuous transition from the actual value, which corresponds to the third setpoint, to the actual value, which corresponds to the second setpoint, and is barely perceptible to the observer of the discharge lamp.

The invention will now be described with reference to the drawing.

Figur 1

eine Ausführungsform einer erfindungsgemäßen Schaltungsanordnung;

Figur 2

ein Funktions-Blockschaltbild einer Steuerschaltung in der Schaltungsanordnung nach Figur 1;

Figur 3

ein Diagramm, das den Zusammenhang zwischen Steuerfrequenz, mit der der Inverter angesteuert wird, und Eigenresonanzfrequenz des Lastkreises vor und nach der Zündung der Lampe darstellt; und

Figur 4

schematisch den zeitlichen Verlauf der Ausgangssignale ausgewählter Schaltungskomponenten der Schaltung nach Figur 1 bzw. Figur 2.

It shows

Figure 1

an embodiment of a circuit arrangement according to the invention;

Figure 2

a functional block diagram of a control circuit in the circuit arrangement of Figure 1;

Figure 3

a diagram illustrating the relationship between the control frequency at which the inverter is driven and the natural resonance frequency of the load circuit before and after the lamp is ignited; and

Figure 4

2 schematically shows the time course of the output signals of selected circuit components of the circuit according to FIG. 1 or FIG. 2.

The exemplary embodiment of a circuit arrangement according to the invention for operating a discharge lamp EL shown in FIG. 1 has a fuse SI on the input side in a feed line, which is followed by a rectifier BR. Its output is bridged by a smoothing capacitor C1. The downstream inductor L1 and the capacitor C2 form a radio interference suppression element.

A circuit component IC, which can be constructed as shown in FIG. 2, is a control circuit for driving a transistor T1 (base or gate electrode connection 10 of the control circuit IC) and a transistor T2 (base or gate electrode at the connection) 8 of the control circuit IC). Both transistors T1 and T2 form a half-bridge arrangement or an inverter. Resistors R3, R4, R5 and R6 are connected on the one hand to connections 2 to 5 and on the other hand to connection 6. With the resistor R3 a setpoint (SW1, Figure 4a) of the load current in the preheating phase and With resistor R4, a setpoint (SW3, FIG. 4a) of the load current is formed in the normal operating phase. A dead time is programmed with the resistor R5, which delays the switching on of the one transistor after the switching off of the other transistor. Their function is described with reference to Figure 2.

A capacitor C7 is used to smooth the voltage supply for the circuit component IC. When the overall arrangement shown in FIG. 1 is started up, this capacitor is charged via the resistor R1 by drawing energy from the network. In order to minimize losses in the resistor R1, it is chosen to have a very high resistance. For a sufficient voltage supply of the circuit component IC, however, a larger current than the current that can be supplied via R1 is required. In the operation of the overall arrangement, the circuit component IC is therefore supplied with energy from the load circuit in time with the inverter. For this purpose, as well as for switching relief of the two switching elements T1 and T2, the capacitor C4 is connected between the half-bridge center (IC connection 9) on the one hand and the junction point of two diodes D2 and D3 on the other.

If T1 is activated, capacitor C4 is charged to the voltage at C2 minus the voltage at capacitor C7. If T1 is now deactivated, C4 is discharged by the energy stored in the choke L2 via the load circuit (L2, EL / C5, C6 and R2) and the diode D3. This process limits the voltage gradient dU (t) / dt at the half-bridge center (IC connection 9) and the switching losses in T1. While T2 is activated, C4 remains discharged. If T2 is now deactivated, C4 is charged by the energy stored in the choke L2 via the diodes D2, the capacitor C7 and the load circuit (L2, EL / C5, C6 and R2). This charging current leads to a charging of C7, the voltage gradient dU (t) / dt at the half-bridge center (IC connection 9) and the switching losses in T2 are limited in an analogous manner as described above.

As shown in FIG. 1, the voltage on capacitor C7 can be limited by designing diode D3 as a zener diode. C7 can only be charged as long as the voltage at C7 plus the forward voltage of diode D2 is less than the Zener voltage of diode D3.

Another way of limiting the voltage at C7 is to implement a zener diode in the circuit component IC with the cathode at connection 1 and the anode at connection 6.

Via the diode D1, which can be arranged inside (between the terminals 1 and 11) of the circuit IC or outside the circuit IC, a capacitor C3 connected to the terminal 9 of the circuit IC is charged to the voltage of C7 when the transistor T2 is activated (bootstrap level consisting of D1 and C3).

The load circuit with the discharge lamp EL is connected to terminals 9 and 6 of the circuit IC; this consists of a series circuit of the inductor L2, the discharge lamp EL with the capacitor C5 connected in parallel, a capacitor C6 and a (shunt) resistor R2 which is connected between the connections 6 and 7 of the control circuit IC. Resistor R2 detects the current flowing in the load circuit; the detected current value is fed to the control circuit IC at terminal 7, which processes this current value further, as will be described.

gegeben ist.Before the lamp EL is ignited, that is to say in the preheating phase and in the ignition phase, the load circuit has a first pole point with the frequency f _res1 , which is determined by the formula $${\mathit{\text{f}}}_{\mathit{\text{res1}}}\text{=}\frac{\mathit{\text{1}}}{\mathit{\text{2nd}}\text{π}\sqrt{\mathit{\text{L2}}\text{·}\frac{\mathit{\text{C5}}\text{·}\mathit{\text{C6}}}{\mathit{\text{C5}}\text{+}\mathit{\text{C6}}}}}$$

given is.

gegeben ist, da nun die lampenparallele Kapazität (C5 in Figur 1) durch die Lampe nahezu kurzgeschlossen wird.When the discharge lamp is ignited, a second pole point with the frequency f _res2 , which is approximated by the formula, _{arises suddenly} $${\mathit{\text{f}}}_{\mathit{\text{res2}}}\text{=}\frac{\mathit{\text{1}}}{\mathit{\text{2nd}}\text{π}\sqrt{\mathit{\text{L2}}\text{·}\mathit{\text{C6}}}}$$

is given, since the lamp parallel capacity (C5 in Figure 1) is almost short-circuited by the lamp.

The frequency f _{res1 of} the first pole point (preheating phase TV and ignition phase TZ in FIG. 4) is therefore greater than the frequency f _{res2 of} the second pole point (start-up phase TA and normal operation TN in FIG. 4), since C6 is larger than the series circuit comprising C5 and C6 . The period of the load current in the preheating phase TV and in the ignition phase TZ is thus shorter than the period of the load current in the start-up phase and in normal operation.

FIG. 2 shows a functional block diagram of an embodiment of the control circuit IC shown in FIG. 1. Individual or all of the function blocks shown in FIG. 2 can be implemented as an integrated circuit.

Structure of the control circuit IC

The structure of an exemplary embodiment of the control circuit IC is described below:

The control circuit IC has an input stage ES on the input side (connection 7). The input stage ES is connected to a current regulator circuit SR via its first input SRE1. The current regulator circuit SR is also connected via a second input SRE2 to a current setpoint generation circuit SWE and via a third input SRE3 and an output SRA1 to an output stage AS.

The current setpoint generation circuit SWE is connected to a counter Z via a first input SWEE1 and to a D / A converter DAW via a second input SWEE2. Furthermore, the resistors R3 and R4 are connected to two further inputs SWEE3 and SWEE4 of the current setpoint generating circuit SWE, which are also terminals 2 and 3 of the control circuit IC. A setpoint value SW1 that is constant over time (FIG. 4a) is realized with R3 and a setpoint value SW5 that is constant over time (FIG. 4a) is realized with R4.

A clock generator TG is connected to an ignition detection circuit ZE via an input TGE1; it is also connected to the counter Z via a first output TGA1 and to the ignition detection circuit ZE via a second output TGA2. The resistor R6 is connected to an input TGE2, which is also terminal 5 of the control circuit IC.

The ignition detection circuit ZE is connected to the clock generator TG via an input ZEE1 and to the output stage via a second input ZEE2 AS and connected to the counter Z via a third input ZEE3 and a third output ZEA3. The ignition detection circuit ZE is connected to the clock generator TG via a first output ZEA1 and to the output stage AS via a second output ZEA2.

The counter Z is connected to the undervoltage protection circuit USS via a first input ZE1, to the clock generator TG via a second input ZE2 and to the ignition detection circuit ZE via a third input ZE3 and a first output ZA1. The counter Z is connected via a second output ZA2 to the current setpoint generation circuit SWE and via a third output ZA3 to the D / A converter DAW.

The output stage AS is connected via a first input ASE1 to the undervoltage protection circuit USS, via a second input ASE2 to the current regulator circuit SR and via a third input ASE3 to the ignition detection circuit ZE. The output stage AS is connected via a first output ASA1 to a dead time element TZG and to the ignition detection circuit ZE; it is connected to the current regulator circuit SR via a second output ASA2.

The dead time element TZG is connected via an input TZGE1 to the output stage AS, via a first output TZGA1 with a first driver TT1 of the first transistor T1 (FIG. 1) and via a second output TZGA2 with a second driver TT2 of the second transistor T2 (FIG. 1) connected. The resistor R5 is connected to an input TZGE2, which is also a terminal 4 of the control circuit IC.

The first driver TT1 of the first transistor T1 (FIG. 1) and the second driver TT2 of the second transistor T2 (FIG. 1) are connected via inputs TT1E1 and TT2E1 connected to the dead time element TZG. The first driver TT1 is supplied via the IC connection 1 or VS with a reference potential at the IC connection 6 or GND with the energy required to control the transistor T1. The second driver TT2 with the bootstrap stage, which is formed by the capacitor C3 and the diode D1, via the IC connection 11 or BOOT with a reference potential at the IC connection 9 or OUT with that for controlling the transistor T2 required energy supplied.

The first driver TT1 controls the first transistor T1 (FIG. 1) via its output TT1A1 (also IC connection 10 of the control circuit IC) and the second driver TT2 controls the second transistor via its output TT2A1 (simultaneously IC connection 8 of the control circuit IC) T2 (Figure 1).

A reference voltage circuit REF provides the individual circuit components within the control circuit IC with a reference signal which has a high degree of accuracy and is ideally independent of all environmental conditions. For this purpose, it is connected to the IC connection 6 or GND and the IC connection 1 or VS, which is connected to the capacitor C7 (FIG. 1).

An undervoltage protection circuit USS evaluates the level of the supply voltage at IC connection 1 (FIG. 1) or VS. If this voltage is below a predeterminable value, the output stage AS is blocked by a corresponding signal via its input ASE1 and set to a defined initial state. At the same time, the counter Z is reset to its defined initial counting state by the undervoltage protection circuit USS via the counter input ZE1 when the voltage mentioned is below the predeterminable value.

Operation of the control circuit IC

The mode of operation of the above exemplary embodiment of the control circuit IC is described below:

When the mains voltage is applied to the overall arrangement, an integrator in the current regulator circuit SR is set to a defined starting value and the half-bridge transistor T1 is set at a sufficiently high supply voltage at the IC connection 1 (FIG. 1) or VS for control by the undervoltage protection circuit USS via the output stage AS switched on, which switches the load circuit to the rectified and smoothed mains voltage.

As a result, a current flow begins in the load circuit through the lamp inductor L2, the capacitor C5, the two filaments of the lamp, the capacitor C6 and the resistor R2, which oscillates sinusoidally due to the resonant structure of the load circuit.

At the output of the integrator of the current regulator circuit SR there is now a cosine-shaped voltage which, starting from a fixedly defined initial value, approximates the setpoint formed by the current setpoint generation circuit SWE over the course of the first half-wave of the load current in the load circuit.

The integrator's output voltage can decrease from a high start level ("down-integration" of the load current) or increase from a low start value ("up-integration"). In the following, an integration is assumed only as an example.

If the output voltage of the integrator reaches the desired value, a comparator of the current regulator circuit SR delivers a pulse-shaped signal at the output SRA1 (FIG. 4f), which is passed on to the output stage AS. The result of this is that the half-bridge transistor T1 which is switched on is switched off and the transistor T2 which is switched off at this point in time is switched on after a dead time t _T (FIG. 4, lines e1 and e2) realized by the dead time element TZG. During this dead time t _T , the integrator is reset to its initial value at the same time. After the dead time t _{T has} elapsed, when the transistor T2 is switched on, the integrator starts integrating the resonance current again until its output voltage and the setpoint match again, the transistor T2 is switched off and the dead time expires again before T1 is switched on again and thus the cycle for the next and all subsequent oscillations of the load current is continued.

This self-oscillating sequence has the advantage that there is no need for an oscillator to excite the series resonant circuit in the control.

The actual value detection of the current I _L in the load circuit (FIG. 1), and thus its frequency, takes place in all operating phases of the lamp by means of the shunt resistor R2, the voltage drop U _Shunt at this resistor being fed to the input stage ES.

The input stage ES amplifies this voltage drop and processes it, for example, so that each half-wave of the load current can be processed individually by the current regulator circuit SR connected downstream of the input stage ES.

The current regulator circuit SR consists of an integrator (not shown in FIG. 2) and a comparator (not shown in FIG. 2).

(t = 0, wenn T1 bzw. T2 eingeschaltet werden;
t = t _Ende , wenn T1 bzw. T2 ausgeschaltet werden)
auf. In dieser Formel bezeichnen R_int und C_int einen Widerstand bzw. eine Kapazität, die zur schaltungstechnischen Realisierung einer Integrationsfunktion in SR erforderlich sind.The integrator integrates the output signal of the input stage ES, which is accepted at the input SRE1, based on a fixed, predeterminable starting voltage U _int (t = 0) according to $${\mathit{\text{U}}}_{\text{int}}\text{=}\frac{\text{1}}{{\mathit{\text{R}}}_{\text{int}}\text{·}{\mathit{\text{C.}}}_{\text{int}}}\text{·}\int_{\mathit{\text{t}}\text{= 0}}^{\mathit{\text{t}}\text{=}{\mathit{\text{t}}}_{\mathit{\text{The End}}}} {\mathit{\text{U}}}_{\mathit{\text{Shunt}}}\text{(}\mathit{\text{t}}\text{) ·}\mathit{\text{German}}\,d$$

(t = 0 if T1 or T2 are switched on;
t = t _end when T1 or T2 are switched off)
on. In this formula, R _int and C _int denote a resistance and a capacitance, respectively, which are required to implement an integration function in SR in terms of circuitry.

The comparator compares the output voltage U _{int of} the integrator with set values (SW1, SW2 (t), SW3, SW4 (t), SW5 in FIG. 4) of the load current which are generated by the current setpoint generation circuit SWE and which are supplied to the current regulator circuit SR via their input SRE2.

In the preheating phase TV (FIG. 4), the current setpoint generation circuit SWE generates a first time-constant setpoint SW1 (FIG. 4a) of the load current, which corresponds to the actual value of the preheating current desired in the preheating phase.

In the ignition phase TZ (FIG. 4), the current setpoint generation circuit SWE generates a time-variable setpoint SW2 (t) of the load current, which setpoint is led from the first time-constant setpoint SW1 of the load current to a predefinable value (for example SW2max in FIG. 4a).

In a first part TA1 of the start-up phase TA, the current setpoint generation circuit SWE generates a second time-constant setpoint SW3 of the load current, which setpoint corresponds to a desired actual value of the load current in the first part TA1 of the start-up phase TA.

In a subsequent second part TA2 of the start-up phase TA, the current setpoint generation circuit SWE generates a second time-variable setpoint SW4 (t) of the load current, which setpoint is led from the setpoint SW3 of the load current to a setpoint SW5 of the load current in the normal operating phase TN.

In the normal operating phase TN, the current setpoint generation circuit SWE generates the third time-constant setpoint SW5 of the load current, which setpoint corresponds to a desired actual value of the load current in the normal operating phase TN.

The current setpoint generation circuit SWE is controlled both by output signals of the counter Z (via the input SWEE1) and by output signals of the D / A converter DAW (via the input SWEE2).

As already mentioned, the current setpoint generation circuit SWE generates the setpoint corresponding to the respective operating phase for the current-time area of a half-wave of the current I _L in the load circuit. Via its input SWEE1, the current setpoint generation circuit SWE receives the information from the output ZA2 of the counter Z (FIG. 4h) whether the overall arrangement is in the preheating phase TV or in the ignition phase TZ (lamp EL does not burn) or in the start-up phase TA or normal operating phase TN (Lamp EL is on).

For both phase groups (1: lamp does not burn; 2: lamp burns), a time-constant setpoint that can be specified via an external resistor (R3, R4) is generated (see FIG. 4a: SW1 and SW5). If the D / A converter DAW now supplies an analog signal to the current setpoint generation circuit SWE via the input SWEE2, the time-constant setpoint SW1 (defined by R3, preheating / ignition phase) or that is determined depending on the state of the input signal at the input SWEE1 other time constant setpoint SW5 (defined by R4, start-up / normal operating phase) changed in accordance with the time profile and the size of the analog signal at the input SWEE2 of the current setpoint generation circuit SWE. This forms a first time-variable setpoint SW2 (t), a third time-constant setpoint SW3 and a second time-variable setpoint SW4 (t).

The comparator of the current regulator circuit SR always delivers a switching pulse (FIG. 4f) to the output stage AS via the SR output SRA1 when the integrated current-current time domain is a target current-time domain and thus the corresponding output voltage U _{int of} the current regulator circuit integrator exceeds the respective setpoint (SW1, SW2 (t), SW3, SW4 (t), SW5).

Furthermore, during each dead time t _T (FIGS. 4e1, 4e2) of the dead time element TZG, the integrator of the current regulator circuit SR is set to its initial state via its third input SRE3, which is connected to the output ASA2 of the output stage AS, in order to carry out the next integration process for the next one Half wave of the load current I _L to begin.

The clock generator TG consists of a timing element, which defines a period t _TG , after the expiration of which a time-limited output pulse (FIG. 4c) is generated at the clock generator output TGA2, and one Feedback network, which ensures that the period expires again after the generation of this output pulse. The resulting free-running multivibrator vibrates at the natural vibration frequency $${\mathit{\text{f}}}_{\mathit{\text{TG}}}\text{=}\frac{\mathit{\text{1}}}{{\mathit{\text{t}}}_{\mathit{\text{TG}}}}\text{.}$$

The period t _TG can be specified with the external resistor R6 (FIG. 1).

The clock generator TG has a control input TGE1 in order to be able to use it as a time measuring element: If a control signal is applied to this control input TGE1, the timing element - as long as the control signal is present - is put into the state in which it is in free-swinging operation at the beginning of everyone Period of oscillation.

It is thus possible with the clock generator to specify the start of a period of a vibration frequency deviating from the natural vibration frequency f _TG regardless of the current state of its timing element.

At the output TGA2, the clock generator TG always delivers switching pulses (FIG. 4d) when its timing element is reset by its feedback network after a period t _{TG has} elapsed to the state corresponding to the beginning of a period t _TG .

At the output TGA1 of the clock generator TG, the switching signals which set the timing element of the clock generator in its initial state are made available and are fed to the counter Z. Does the clock generator TG in the ignition phase TZ as a time measuring element, no signals are first generated at the output TGA2, switching signals are passed on to the counter Z via the output TGA1 with the frequency corresponding to the inverter frequency. In free-running mode TV, TA and TN, the clock generator TG generates signals of the same and same frequency at both outputs TGA1 and TGA2.

A pulse (FIG. 4d) is generated at the output TGA2 of the clock generator in the ignition phase (the ZE to be described is activated) if the duration between two successive switching pulses at the control input TGE1 of the clock generator is greater than the period by the timing element defined period t _{TG of} the natural oscillation frequency f _{TG of} the clock generator.

The counter Z is set to a defined initial count state by the undervoltage protection circuit USS via its input ZE1. Starting from this initial counting state, the counter Z counts the switching signals supplied by the clock generator TG via its input ZE2. When a predeterminable count is reached, which takes place after the desired duration TV (FIG. 4) of the preheating phase, the counter Z activates the ignition detection circuit ZE via its output ZA1, with which the ignition phase begins.

The end of the ignition phase is indicated to the counter Z via the counter input ZE3.

The counter Z indicates the ignition phase via the state of the signal available at the counter output ZA1. The counter Z indicates via the state of the signal available at output ZA2 whether the overall arrangement is in the preheating / ignition phase TV / TZ (lamp does not burn) or in the start-up / normal operating phase TA / TN (lamp burns) .

At its output ZA3, the counter Z provides certain individual sequences of predeterminable, consecutive count values (i.e. e.g. the counter readings 298 to 450), which are converted in the D / A converter DAW into analog signals corresponding to the current counter reading. These analog, time-varying signals enable the continuous changes in the setpoints SW2 (t) and SW4 (t) for the current-time area of a current half-wave in the load circuit, that of the current regulator circuit SR in the ignition phase TZ and in the part TA2 (FIG. 4) Start-up phase TA can be specified.

The D / A converter DAW converts the counter readings transferred to it from the counter Z into analog signals. If no counter readings are made available at the output ZA3 of the counter Z, DAW does not supply a signal to the current setpoint generation circuit SWE.

The output stage AS controls the downstream dead time element TZG with a binary signal such that after each switching signal that occurs at one of its inputs ASE2 (connected to the current regulator circuit SR) or ASE3 (connected to the ignition detection circuit ZE), this binary output signal ASA1 changes its state changes (function of a toggle flip-flop). The output stage can be brought into a defined state by the undervoltage protection circuit USS via input ASE1.

The dead time element TZG is acted upon by the output stage AS with a binary signal which indicates the state of the half-bridge (T1, T2 in FIG. 1). If the state of this signal changes at the output ASA1 of the output stage or at the input TZGE1 of the dead time element TZG, the dead time element TZG immediately deactivates the driver that has just been activated (eg TT1) and activates the last inactive driver (for example TT2) after the dead time t _T which can be predetermined by an external resistor R5 (FIG. 4e, 4e1, 4e2).

Two power drivers TT1, TT2 amplify the control signals of the dead time element TZG and control the half-bridge transistors T1, T2 (FIG. 1) directly via the IC connections 8 or LVG (low voltage gate) and 10 or HVG (high voltage gate).

The ignition detection circuit ZE works as a switching device for signal paths: If the counter Z indicates the start of the ignition phase TZ by a signal at its output ZA1 of the ignition detection circuit ZE (FIG. 4g), this applies the clock generator output TGA2 to the input ASE3 of the output stage AS and the output ASA1 the output stage AS to the clock generator input TGE1.

ZE thus enables signal paths from AS to TG, whereby the timing element of TG is set by control pulses from AS to its state corresponding to the start of a period of the timing element (connection path between ZEE2 and ZEA1) and the output stage AS has a control pulse from its input ASE3 Output TGA2 of the TG is fed (connection path between ZEE1 and ZEA2).

This makes it possible for the output stage AS to synchronize the clock generator output TGA1 with the frequency of the inverter in the ignition phase, with no switching pulse occurring at the clock generator output TGA2 as long as the inverter frequency f _Inv (FIG. 3) defined by the current regulator circuit SR is greater than the frequency f _{TG of} the free-running clock generator TG.

During the ignition phase TZ, the clock generator TG can determine the state of the output stage AS after the period t _TG impressed in the timing element change and thus indicate the ignition to the counter Z via its input ZE3, whereby the current setpoint generation circuit SWE sets the setpoint to the value SW3 corresponding to the start-up phase TA.

This is precisely the case if the time period between 2 switching pulses of the SR during the ignition phase is greater than the period t _{TG of} the TG.

The functions implemented by the control device IC shown in FIG. 2 can also be implemented by a differently structured control device, in particular also by a microprocessor.

FIG. 3 shows a schematic image of the frequency range of the working range of the overall arrangement. The frequency range in which the inverter operates is indicated on the abscissa and the current I _L in the load circuit or the voltage U _L across the discharge lamp EL is indicated on the ordinate.

• 1. Den Güteverlauf G1 des Lastkreises vor der Zündung der Lampe mit der Polstelle f_res1 mit dem zugehörigen Frequenzbereich f_TVmin ≤ f_Inv ≤ f_TVmax, der durch die Anforderungen an die Vorheizung der Wendeln der Lampe gegeben ist.
• 2. Den Güteverlauf G2 des Lastkreises mit gezündeter Lampe mit der Polstelle f_res2.

Figure 3 shows two quality curves:

• 1. The quality curve G1 of the load circuit before the ignition of the lamp with the pole point f _res1 with the associated frequency range f _TVmin f f _Inv f f _TVmax , which is given by the requirements for preheating the filaments of the lamp.
• 2. The quality curve G2 of the load circuit with the lamp ignited with the pole point f _res2 .

The upper limit f _TVmax for the inverter _frequency f _Inv during the preheating phase TV is given by the fact that for a given preheating time TV a minimum preheating current I _L for the lamp filaments used is not may be fallen below, otherwise the filaments are not sufficiently emissive.

The lower limit f _TVmin for the inverter _frequency f _Inv during the preheating phase TV is given by the fact that the voltage U _L across the lamp EL on the capacitor C5 (FIG. 1) during the preheating phase of the filaments must not exceed a maximum value defined by the lamp because otherwise ignition may occur before the preheating process (early ignition).

des Inverters und damit des Laststroms I_L so geregelt, daß sie mit der unteren Grenze f_TVmin des Frequenzbereichs nahezu übereinstimmt. Dadurch wird eine optimale Vorheizung der Wendeln in sehr kurzer Zeit erreicht. Neben diesem signifikanten Vorteil des erfindungsgemäßen Verfahrens bietet dieses den weiteren Vorteil, daß auf die der Erwärmung der Wendeln folgende Abnahme der Güte des Lastkreises (und damit des bei konstanter Frequenz abnehmenden Stroms) in der Weise reagiert werden kann, daß durch eine geregelte Abnahme der Inverterfrequenz f_Inv die Spannung über der Lampe und der Strom durch die Wendeln während der Vorheizung nahezu konstant bleibt.In the method according to the invention for operating a discharge lamp EL, the frequency ${\text{f}}_{\text{Inv}}{\text{= f}}_{\text{TV}}$

of the inverter and thus the load current I _L regulated so that it almost corresponds to the lower limit f _{TVmin of} the frequency range. This ensures optimal preheating of the filaments in a very short time. In addition to this significant advantage of the method according to the invention, this offers the further advantage that the decrease in the quality of the load circuit (and thus the current decreasing at a constant frequency) following the heating of the filaments can be reacted in such a way that by a regulated decrease in the inverter frequency f _Inv the voltage across the lamp and the current through the filaments remains almost constant during preheating.

des Inverters so reduziert, daß sie sich der Polstelle f_res1 des Lastkreises nähert und dadurch eine zur Zündung der Lampe ausreichende Spannung U_L über der Lampe (EL/C5) generiert wird.At the end of the preheating phase TV the frequency ${\text{f}}_{\text{Inv}}{\text{= f}}_{\text{TZ}}\text{(t)}$

of the inverter so reduced that it approaches the pole point f _{res1 of} the load circuit, thereby generating a voltage U _L sufficient to ignite the lamp across the lamp (EL / C5).

As already described, at the moment the lamp EL is ignited, the pole point of the load circuit jumps to the value f _res2 , since the lamp parallel capacity (C5 in FIG. 1) is now almost short-circuited by the lamp.

The load circuit has a significantly lower natural resonance frequency at and after the ignition compared to the natural resonance frequency before the ignition.

In the ignition detection according to the invention, this frequency jump is recognized, the duration which elapses to reach a desired current time area through the actual current time area being compared with the period t _{TG of} a clock generator.

The frequency f _TG (FIG. 3) of the clock generator is selected according to the invention in such a way that it is smaller than the pole position _frequency f _res1 and larger than the pole position _frequency f _res2 .

During the preheating, the frequency f _{TG of} the clock generator TG is lower than the inverter frequency f _Inv as long as the lamp has not ignited.

After the lamp EL has been ignited, the time interval in which the actual current-time area is integrated in the current regulator circuit SR to the value corresponding to the desired value is longer than the period t _{TG of} the clock generator TG. This means that the frequency t _{TG of} the clock generator TG after the ignition is greater than the inverter frequency f _Inv .

auf ${\text{f}}_{\text{Inv}}{\text{= f}}_{\text{TN}}$

.In the start-up phase TA and in the normal operating phase TN, the inverter frequency f _Inv is regulated such that the desired load current I _{L is} set when the quality of the load circuit G2 is given and the lamp is ignited. f _TA is the inverter frequency f _Inv in the start-up phase and f _TN is the inverter frequency f _Inv in the normal operating phase. The inverter frequency increases during the continuous transition from the start-up phase to the normal operating phase f _Inv corresponding to the decrease in the setpoint SW4 (t) from ${\text{f}}_{\text{Inv}}{\text{= f}}_{\text{TA}}$

on ${\text{f}}_{\text{Inv}}{\text{= f}}_{\text{TN}}$

.

Figure 4 shows a) the time course of the load current setpoints, b) the output voltage of the timing element of the clock generator TG, c) the voltage at the output TGA1 of the clock generator TG, d) the voltage at the output TGA2 of the clock generator TG, e) the voltage at the output ASA1 the output stage AS, e1) the voltage at the output TT1A1 of the driver TT1, e2) the voltage at the output TT2A1 of the driver TT2, f) the voltage at the output SRA1 of the current regulator circuit SR, g) the voltage at the output ZA1 of the counter Z, and h ) the voltage at the output ZA2 of the counter Z.

The voltage curves mentioned are shown for the preheating phase TV, the ignition phase TZ with the ignition point t _Z , the start-up phase TA and for normal operation TN.

4a shows the development of the setpoints SW1, SW2 (t), SW3, SW4 (t) and SW5. The value SW2 (t) increases until the ignition is recognized (time t _ZE ). SW3 is formed in period TA1. Subsequently (when the counter has reached a certain count), the setpoint SW4 (t) is formed in the period TA2 as a function of the analog signals formed by DAW. Finally (after the counter has reached a further specific count) the setpoint SW5 is formed in the period TN.

FIG. 4b shows the profile of the output voltage of the timing element of the clock generator TG. In the periods TV, TA (TA1 and TA2) and TN, the clock generator works in free-running mode with the period t _TG . From the beginning of the ignition phase TZ, the timer becomes the first and every further occurrence of a signal at the output SRA1 of the current regulator SR set in its initial state and thereby synchronized with the frequency f _{Inv of} the inverter. If no signal occurs at the output SRA1 due to the ignition of the lamp within the period t _TG , the ignition of the lamp which occurred at the time t _Z is thus recognized and the ignition phase is ended.

4c shows the signals at the output TGA1 of the clock generator TG. A switching pulse occurs whenever the timing element of the clock generator is set to its initial state (FIG. 4b). During the ignition phase TZ, the frequency of the switching pulses at TGA1 corresponds to the inverter frequency f _Inv (synchronized operation), except for the ignition phase of the frequency f _{TG of} the free-running clock generator.

FIG. 4d shows the signals at the output TGA2 of the clock generator TG. A switching pulse only occurs when the timing element of the clock generator is set to its initial state by the feedback network at the end of its period t _TG (FIG. 4b). No switching pulses occur during the ignition phase TZ, as long as the timer is reset by the signals at the input TGE1 before the period t _{TG has} expired.

Figure 4e shows the output signal ASA1 of the output stage AS. Depending on the value of the output signal, as shown in FIGS. 4e1 and 4e2, the two half-bridge switching elements T1, T2 are activated. Immediately after each change of state in which an activated switching element is deactivated, a dead time t _T begins, after which the previously inactive switching element is activated.

FIG. 4f shows the signals at the output SRA1 of the current regulator circuit SR. A switching pulse always occurs when the detected actual current time area becomes larger than the specified target current time area. The switching pulses cause a change in state of the output stage AS or the signal ASA1 (FIG. 4e). Immediately after the ignition point t _Z , no switching pulse occurs at the output SRA1 within a period t _{TG of} the clock generator TG.

Figure 4g shows the output signal ZA1 of the counter Z, which indicates the ignition phase TZ, for example by a signal "1".

Figure 4h shows the output signal ZA2 of the counter Z, which indicates the burning of the lamp EL (start-up phase TA and normal operating phase TN), for example by a signal "1".

Claims (30)

Method for operating a discharge lamp (EL), with a load circuit which contains the discharge lamp (EL), a capacitor (C5) connected in parallel to this, a choke (L2), at least one further capacitor (C6), and an element (R2) , which detects a load current (I _L ) flowing in the load circuit, and with an inverter, which can be designed as a half-bridge arrangement with two switching elements (T1, T2), which are externally controlled with a frequency (f _Inv ) of the inverter,
characterized in that the following process steps are carried out - in the preheating phase (TV) - Detection of the actual value of the load current (I _L ); - Forming a first time-constant setpoint (SW1) of the load current (I _L ), which corresponds to a desired actual value of a load current in the preheating phase; - Activation of a clock generator (TG) that freewheels with a frequency (f _TG ) that is lower than the pole position frequency (f _res1 ) of the load circuit when the lamp is not ignited and that is greater than the pole position _frequency (f _res2 ) of the load circuit when the lamp is ignited ; - End of the preheating phase after a first definable period (TV); - in the ignition phase (TZ) - Detection of the actual value of the load current (I _L ) in the load circuit; - Forming a time-variable setpoint (SW2 (t)) of the load current, which setpoint (SW2 (t)) is based on the time-constant setpoint (SW1) of the load current (I _L ) to a predeterminable value (SW2max); - Synchronizing the clock generator (TG) with the frequency (f _Inv ) of the inverter; - End of the ignition phase as soon as the target value of the load current (I _L ) reaches a value at which a duty cycle of a half-bridge switching element becomes longer than the period ( ${\text{t}}_{\text{TG}}{\text{= 1 / f}}_{\text{TG}}$

) of the free running clock generator (TG), - in normal operation (TN) - Detection of the actual value of the load current (I _L ); and - Forming a second time-constant setpoint (SW5) of the load current, which setpoint (SW5) corresponds to a desired actual value of the load current in normal operation. Method for operating a discharge lamp (EL), with a load circuit which contains the discharge lamp (EL), a capacitor (C5) connected in parallel to this, a choke (L2), at least one further capacitor (C6), and an element (R2) , which detects a load current (I _L ) flowing in the load circuit, and with an inverter which can be designed as a half-bridge arrangement with two switching elements (T1, T2) which are externally controlled with a frequency (f _Inv ) of the inverter, characterized in that in each operating phase of the lamp, each individual half-period of the load current is regulated to a predefinable setpoint. Method according to claim 2, characterized in that positive and negative half-waves of the load current (I _L ) are regulated to the same setpoint. Method according to Claim 2 or 3, characterized in that, in order to regulate the period of the load current, the actual value of the current-time area of a half oscillation or a full oscillation of the Load current is detected and that this area is compared with the target value of the current-time area of a half oscillation or a full oscillation of the load current in the current operating phase, that if the actual and target value of the load current match, the inverter is controlled in such a way that a just activated switching element (T2) is deactivated and a just not activated switching element (T1) is activated. Method according to Claim 4, characterized in that a predeterminable dead time (t _T , FIG. 4e) is realized between the deactivation of the switching element (T2) which has just been activated and the switching element (T1) which has just not been activated. Method according to one of the preceding claims, characterized in that in a first period (TA1) of a start-up phase (TA), immediately after the ignition phase has ended, a third time-constant setpoint (SW3, Fig. 4a) of the load current is formed. Method according to claim 6, characterized in that in a second period (TA2) of the start-up phase (TA) a second time-variable setpoint (SW4 (t)) is formed, which continuously starts from the third time-constant setpoint (SW3) in the second time-constant setpoint (SW5) is transferred. The method of claims 1 and 2. Method according to claim 8 and one of claims 3 to 7. Circuit arrangement for performing the method according to one of the preceding claims. Circuit arrangement according to Claim 10, characterized in that the circuit arrangement comprises a discharge lamp (EL), a load circuit which holds the discharge lamp (EL), a capacitor (C5) connected in parallel with it, a choke (L2), at least one further capacitor (C6), and contains an element (R2) which detects the load current, and an inverter which is designed as a half-bridge arrangement with externally controlled switching elements (T1, T2) and has a clock generator (TG). Circuit arrangement according to claim 11, characterized by a control circuit (IC) for controlling the externally controlled switching elements (T1, T2), wherein operating parameters of the control circuit (IC) can be predetermined by resistors (R3, R4, R5, R6). Circuit arrangement according to Claim 12, characterized in that the control circuit (IC) has the clock generator (TG), an ignition detection circuit (ZE) and a counter (Z). Circuit arrangement according to Claim 12 or 13, characterized in that the control circuit (IC) has a current setpoint generation circuit (SWE). Circuit arrangement according to Claim 14, characterized in that the control circuit (IC) has a current regulator circuit (SR). Circuit arrangement according to one of claims 12 to 15, characterized in that the control circuit (IC) has a dead time element (TZG) and a first and a second driver (TT1, TT2) for the externally controlled switching elements (T1, T2). Circuit arrangement according to one of claims 12 to 16, characterized in that the control circuit (IC) is implemented as an integrated circuit. Circuit arrangement according to one of Claims 13 to 17, characterized in that the clock generator (TG) has a time element which defines the period (t _TG ) of its natural oscillation frequency (f _TG ) and is designed in such a way that when the time element is reset to the State that it has at the beginning of a period, the counter (Z) provides a pulse. Circuit arrangement according to one of Claims 13 to 18, characterized in that the clock generator (TG) is connected to the counter (Z), which counts output signals from the clock generator (TG) and which, when predeterminable count values are reached, forms signals which are used to form the setpoints ( SW1, SW2 (t), SW3, SW4 (t), SW5) of the load current can be used. Circuit arrangement according to Claim 19, characterized in that the signals are operating phase-specific. Circuit arrangement according to one of Claims 18 to 20, characterized in that the clock generator (TG) has a control input (TGE1) with which the start of each period of a vibration frequency deviating from the natural vibration frequency (f _TG ) is predetermined, regardless of the current state of its timing element. Circuit arrangement according to one of claims 13 to 21, characterized in that the ignition detection circuit (ZE) by the Counter (Z) is activated when a predeterminable counter reading indicating the start of the ignition phase (TZ) is reached. Circuit arrangement according to one of Claims 18 to 22, characterized in that the ignition detection circuit (ZE) enables signal paths (ASA1 - TGE1; TGA2 - ASE3) from an output stage (AS) to the clock generator (TG) in such a way that the timing element of the clock generator ( TG) is set by control pulses of the output stage (AS) in its state corresponding to the beginning of a period of the timer, and that a control pulse is fed to an output (TGA2) of the clock generator (TG) of the output stage (AS). Circuit arrangement according to one of Claims 18 to 23, characterized in that a pulse is generated at an output (TGA2) of the clock generator (TG) in the ignition phase (TZ) if and only if the duration between two successive switching pulses at the control input (TGE1) of the Clock generator (TG) is greater than the period (t _TG ) of the period defined by the timing element of the natural oscillation frequency (f _TG ) of the clock generator (TG). Circuit arrangement according to Claim 24, characterized in that when a switching pulse occurs for the first time at the output (TGA2) of the clock generator (TG) in the ignition phase (TZ), the ignition detection circuit (ZE) is deactivated and the ignition phase is ended. Circuit arrangement according to one of Claims 18 to 24, characterized in that the ignition phase (TZ) is ended at the latest when a predeterminable counter reading of the counter (Z) is reached. Circuit arrangement according to one of Claims 11 to 26, characterized in that nominal values for current-time areas of the load current (I _L ) for the operating phases in which the lamp is on and the operating phases before the lamp is ignited are separated by a respective resistor ( R3; R4) are adjustable. Circuit arrangement according to one of claims 16 to 27, characterized in that the dead time (t _T ; Fig. 4e, 4e1, 4e2) of the dead time element (TZG) is adjustable by a resistor (R5). Circuit arrangement according to one of Claims 11 to 28, characterized in that the frequency (f _TG ) with which the clock generator (TG) oscillates can be set via a resistor (R6). Use of a control circuit (IC) for a circuit arrangement according to claim 10.

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