Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
  • H05B41/14—Circuit arrangements
  • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
  • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
  • H05B41/288—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices and specially adapted for lamps without preheating electrodes, e.g. for high-intensity discharge lamps, high-pressure mercury or sodium lamps or low-pressure sodium lamps
  • H05B41/2885—Static converters especially adapted therefor; Control thereof
  • H05B41/2887—Static converters especially adapted therefor; Control thereof characterised by a controllable bridge in the final stage
  • H05B41/2888—Static converters especially adapted therefor; Control thereof characterised by a controllable bridge in the final stage the bridge being commutated at low frequency, e.g. 1kHz
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
  • H05B41/14—Circuit arrangements
  • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
  • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
  • H05B41/288—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices and specially adapted for lamps without preheating electrodes, e.g. for high-intensity discharge lamps, high-pressure mercury or sodium lamps or low-pressure sodium lamps
  • H05B41/292—Arrangements for protecting lamps or circuits against abnormal operating conditions
  • H05B41/2921—Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions
  • H05B41/2923—Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions against abnormal power supply conditions
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
  • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps

Definitions

• the present invention relates to a low frequency power converter and specifically to low frequency electronic ballasts for gas discharge devices. More specifically, the present invention relates to a low frequency square wave electronic ballast for high pressure sodium lamps.
• High frequency switchmode power converters An important application for high frequency switchmode power converters is supplying power to gas discharge devices, especially high pressure sodium (HPS) lamps.
• HPS high pressure sodium
• the high frequency ballast and the gas discharge lamp have a higher level of interaction than that which exists between a conventional low frequency ballast and gas discharge lamp.
• High frequency ballasts suffer from acoustic resonance which can cause various problems such as instability, high output fluctuation, or, in the worst case, cracked arc tubes. Therefore, an optimum solution to this problem is the use of a high frequency DC-to-DC switch- mode as a controlled current source connected to a low frequency DC-to-AC square wave inverter supplying the gas discharge lamp.
• this novel high frequency ballast with a low frequency output has significant advantages when compared with either the conventional low frequency ballasts and the usual high frequency electronic ballast. Additionally, a new, high sophisticated electronic ballast generation can be introduced to provide several special features, such as, for example, automatic or controlled dimming.
• a second object of the present invention is to provide a power controlled current source, wherein the power can be selected and/or continuously changed.
• Another object of the present invention is to provide a high efficiency square wave full-bridge inverter operation in a very wide frequency range including DC operation.
• a further object of the present invention is to provide a logic control circuit controlling a square wave full-bridge inverter implementing programmed transition between the high (or zero) and the low frequency operations.
• Another object of the present invention is to provide a low power stabilized logic supply voltage source connected to main voltage, wherein no electrolytic capacitors are used.
• a further object of the present invention is to provide a low power stabilized logic supply voltage source connected to main voltage, wherein no electrolytic capacitors are used.
• FIG. 1 illustrates a schematic diagram of the preferred electronic ballast for gas discharge devices including six basic units
• FIG. 2A, 2B and 2C show the voltage and current waveforms with respect to the schematic diagram of FIG. 1 ;
• FIG. 3A illustrates the ballast curve as a diagram of lamp power versus lamp voltage realized by the preferred electronic ballast of the present invention
• FIG. 3B shows the diagram of lamp current versus lamp voltage
• FIG. 4 shows the circuit diagram of a high power factor preregulator designated as UNIT-1 in FIG. 1 ;
• FIG. 5A shows the circuit diagram of a power control converter designated as UNIT-2 in FIG. 1 ;
• FIG. 5B illustrates a diagram of the inductor current with respect to UNIT-2
• FIG. 5C illustrates a diagram of the functional relationship between output and control voltages
• FIG. 6A shows the circuit diagram of a controlled full- bridge inverter and ignitor circuit designated as UNIT-3 and UNIT-4 in FIG. 1 ;
• FIG. 6B illustrates the four output control signals of a logic drive unit designated as LD-3 in FIG. 1 ;
• FIG. 6C illustrates a timing diagram with respect to UNIT-3 under no load condition
• FIG. 6D illustrates a timing diagram with respect to UNIT-3 under loaded condition
• FIG. 7 shows the circuit diagram of a logic supply and a monitor unit designated as UNIT-5 and UNIT-6 in FIG. 1.
• FIG. 1 illustrates a schematic diagram of the preferred electronic ballast for gas discharge devices including: a high power factor preregulator designated as UNIT-1 including a boost converter (PU-1), a MOSFET driver (MD-1) and a control unit (CU-1 ) ; a power controlled DC current source designated as UNIT-2 including a buck converter (PU-2) , a MOSFET driver (MD-2) and a control unit (CU-2) ; a low-frequency square wave DC-to-AC converter designated as UNIT-3 including a full-bridge square wave inverter (PU-3) , four MOSFET drivers (MD-3) , a logic driver (LD-3) and a frequency control unit (CU-3) ; a high voltage ignitor circuit designated as UNIT-4; a stabilized logic supply voltage source designated as UNIT-5 including a low power half-bridge square wave inverter (HB) and five linear regulators (LR-1 , LR-2, LR-3, LR-4 and LR- 5); a monitor unit designated as
• FIG. 2A, 2B and 2C show some characteristic voltage and current waveforms of the preferred electronic ballast with respect to schematic diagram of FIG. 1.
• FIG. 2A shows the nearly sinusoidal input current (I ⁇ ) of the high power factor preregulator.
• FIG. 2B shows the input (V,) and output (V 0 ) voltages of the power controlled DC current source.
• FIG. 3A illustrates the ballast curve as a diagram of the functional relationship between the lamp power (P L ) and the lamp voltage (V L ) .
• FIG. 3B shows the diagram of lamp current (I L ) versus lamp voltage (V L ) . Three different ranges can be distinguished, depending on the lamp voltage as it is shown in FIG.
• a constant lamp current range in the warming up period l O ⁇ V L ⁇ V Llain) ) a constant lamp power range is a certain range of lamp voltage ( V min) ⁇ V L ⁇ V Llmax) ) ; and a forbidden range ( V L > V L(max) ) , if the lamp voltage reaches V L(max) the ballast will automatically switch off.
• Two different nominal lamp power levels can be selected by the preferred ballast, for instance 200W or 250W. Further ⁇ more, the lamp power can be continuously changed providing dimming capability which can be significant from an energy saving viewpoint.
• UNIT-1 includes an input filter F10 and is shown in FIG. 4.
• the circuit is based on a standard boost converter configuration including a bridge rectifier B10, an inductor L10, a power MOSFET M10, a fast rectifier D10 and an output capacitor C10. Controlled on-time and zero current switching on techniques are applied. Therefore, the peak and average inductor current is sinusoidal as is the input voltage.
• the MOSFET driver designated as MD-1 in FIG. 1 is implemented by MOSFETs M11 and M12, the inputs of which are connected to the outputs of dual input NAND Schmitt-triggers IC10 and IC11 , respectively.
• the control unit designated as CU-1 in FIG. 1 includes: an error amplifier IC15; a saw-tooth generator implemented by a resistor R11 , a capacitor C11 , a MOSFET M13 and a NAND Schmitt-trigger IC13; a pulse width modulated (PWM) comparator IC1 ; and a zero current sensing comparator IC12 connected to a shunt resistor R10.
• Zener diode Z10 This solution is effective if the main switch
• M10 is switched on at zero inductor current level as in the preferred embodiment.
• a further difference between the preferred high power factor preregulator and standard regulators, is the utilization in the present invention, of a relatively small value film capacitor C10 instead of employing a large value electro- lytic capacitor as the output capacitor. In the case, the fluctuation (120Hz) of the output voltage V, is large as can be seen in FIG. 2B.
• UNIT-2 which is connected to the output capacitor C10 of UNIT-1 is shown in FIG. 5A.
• the power unit designated as PU-2 in FIG. 1 is based upon a standard buck converter configuration including a power MOSFET M20, a fast rectifier D20, an inductor L20 and an output (film) capacitor C20.
• the MOSFET driver designated as MD-2 in FIG. 1 is implemented by MOSFETs M21 and M22 controlled by dual input NAND Schmitt-triggers IC20 and IC21.
• the control unit designated as CU-2 in FIG. 1 is much different from the standard control methods.
• This control circuit will be described as follows: a) Floating control: The control unit is connected directly to the MOSFET-driver MD-2 (M21 and M22) and therefore to the main switch M20. b) Zero current sensing employing rectifiers: A fast rectifier D21 connected in series with a Schottky-rectifier D22 are connected in parallel to the main rectifier D20. If the main switch M20 is OFF, the main rectifier D20 is ON and an approxi ⁇ mately 200mV voltage drop occurs across the Schottky-rectifier D22.
• FIG. 5B illustrates the diagram of inductor current i L (t) .
• V c (t) Assuming the ON-state of M20 and a discharged initial condition for capacitor C21 , its voltage V c (t) can be calculated as follows:
• V, (t) -i—2 ⁇ RC
• L is the inductance of inductor L20.
• a low power P channel MOSFET M23 is connected to the output of the voltage comparator
• P A is the average output power
• I p (I a ) is limited to an appropriate value by a Zener diode Z22 as it is also shown in FIG. 5A.
• a low power P channel MOSFET M23 is connected to the output of the voltage comparator IC22, with capacitor C21 connected in parallel with the source and drain of this MOSFET.
• a continuous dimming of the output power (lamp power) can be achieved by a continuous decrease of the value of resistor R21 , which can be advantageous from an energy saving consideration.
• UNIT-3 which is connected to the output capacitor of UNIT-2 is shown in FIG. 6A.
• the power unit designated as PU-3 in FIG. 1 is based on a full-bridge configuration including MOSFETs M31 , M32, M33 and M34.
• the MOSFET drivers designated as MD-3 in FIG. 1 are implemented by four complementary MOSFETs CM31 , CM32, CM33 and CM34. Furthermore, complementary MOSFETs CM33 and CM34 are driven by optoisolators OC33 and OC34, respectively, providing isolation from the control level.
• the logic driver designated as LD-3 in FIG. 1 provides four logic signals ⁇ Q , ⁇ Q 2 , " Q 3 and ⁇ Q A controlling the MOSFET driver MD-3.
• the logic driver signal waveforms for ⁇ Q ,, ⁇ Q 2 , 7-? 3 and ⁇ Q are shown in FIG. 6B.
• the logic driver signals contain appropriate deadtimes avoiding cross conductions of the main switches.
• IC32/1 and the inverting input of IC32/2 are connected to the common point of the RC circuit containing R31 and C31.
• the inverting input of IC32/1 and the non-inverting input of IC32/2 are connected to the common point of a voltage divider pair including resistors R32 and R33.
• the four logic driver signals can be derived from the upper MOSFET driver as:
• ignitor unit UNIT-4
• Q low frequency symmetrical logic signal
• the control unit CU-3 including the following function ⁇ al circuits: a first voltage comparator (IC33/1) with a comparator level V,, where V, is somewhat smaller than V oia ⁇ X) ; a second voltage comparator (IC33/2) with a comparator level V 2 , where V 2 is somewhat smaller than V,; a first timer (IC34) having a timing period of t- ⁇ lOs; a second timer including a digital counter IC35 and a digital oscillator IC36 having a timing period of t 2 ⁇ 120s a low frequency digital oscillator IC37 where the frequency f x «2SHz and the duty cycle is arbitrary; a high frequency digital oscillator IC38 having a frequency f 2 *20kHz and the duty cycle being smaller than 0.5; a T flip-flop implemented by a D flip-flop IC39 having a clock input and a SET input providing the symmetrical signal Q; and two AND gates IC40/1 and IC40/2,
• FIG. 6A shows the timing diagram under no load condition including the case of an unsuccessful ignition.
• FIG. 6D shows the timing diagram in the case of a successful ignition (normal operation) .
• the ignited lamp operating quickly in a complicated plasma physical process (including the glow dis- charge) achieves the state of arc discharge, assuming that a sufficient high voltage and high current are provided.
• an important task of the circuit of the present invention is to stabilize the lamp in the arc discharge state. Since the discharge tube is cold, any slow zero current crossing can cause an extinction of arc discharge.
• the time period of short term starting operation is implemented by the first timer t ⁇ lOs) . After the short term starting period, the discharge becomes a normal low frequency
• the different starting operations can be selected by a switch S as it is shown in FIG. 6A, which switches between the high frequency (HF) or direct current (DC) mode.
• HF high frequency
• DC direct current
• the square wave full-bridge PU-3 can be completed with one of the standard current limiting methods connected together with the control unit which is not shown in FIG. 6A.
• UNIT-4 which is connected to the output of UNIT-3 is also shown in FIG. 6A. Additionally, resistor R42 is connected to the output capacitor C10 of the preregulator unit.
• the circuit is based on a pulse transformer configuration including a pulse transformer L41 , a thyristor Th41 , a capacitor C41 and an RC circuit (R41 and C42) connected to the gate of thyristor Th41.
• the capacitor C41 is charged by a resistor R42 connected to the output capacitor of UNIT-1.
• the capacitor C41 is discharged periodically by thyristor Th41 which is controlled by the digital counter of unit CU-3 with a repetition frequency of 2Hz.
• inductor L41 provides a continuous current flow through the lamp when the unit PU-3 changes the polarity of lamp voltage containing deadtimes.
• UNIT-5 which is connected to the sinusoidal AC power supply (more precisely to the common mode filter of UNIT-1) is shown in FIG. 7.
• UNIT-5 acting as a stabilized voltage source, includes a low power half-bridge square wave inverter designated as HB and five linear regulators designated as LR-1 , LR-2, LR-3, LR-4 and LR-5.
• the low power self-oscillating half-bridge inverter square wave oscillator
• the low power self-oscillating half-bridge inverter square wave oscillator
• the transformer has a primary winding N p , two feedback windings N f1 and N f2 , and five secondary windings N s1 , N s2 , N s3 , N s4 and N s5 providing appropriate (non-stabilized) voltage sources for the five linear regulators.
• the feedback windings connected in series with RC circuits (R51 , C54 and R52, C55) , are connected to the bases of transistors T51 and T52, providing decreasing base (diode) currents and therefore alternating switched ON or OFF states for the transistors.
• the self-oscillating feature is realized by the polarity change in the windings caused by the switched off magnetizing current of transformer L51.
• the circuit includes a self-switching off starter circuit implemented by a continuously charged capacitor C65, a DIAC S51 and a transistor T53 controlled by winding N f1 .
• the rectified output voltages are essentially DC voltages from a high frequency viewpoint. Therefore, only small value film capacitors can be used as smoothing elements. Stabilized output voltages (12V) can be obtained by the use of any standard linear regulation methods.
• UNIT-6 operates as a monitor unit including four
• Schmitt-triggers is also shown in FIG. 7. The Schmitt-triggers
• ST-1 , ST-2, ST-3 and ST-4 are implemented by four voltage comparators designated as IC61 , IC62, IC63 and IC64.
• the first Schmitt-trigger (IC61 ) is controlled by a photoresistor (PH) implementing a light controlled switch.
• the second Schmitt- trigger (IC62) is controlled by a thermistor (TH) implementing a temperature controlled switch.
• the third and fourth Schmitt- trigger (IC63 and IC64) are controlled by a voltage V x which is proportional to the input voltage implementing a window compara ⁇ tor.
• Transistor T61 is controlled by the common outputs of comparators (AND connection) resulting the monitor unit.

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• Circuit Arrangements For Discharge Lamps (AREA)
• Discharge Lamps And Accessories Thereof (AREA)

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Citations (6)

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• 1994
  • 1994-08-26 JP JP7514685A patent/JPH10504928A/ja active Pending
  • 1994-08-26 AU AU76359/94A patent/AU685843B2/en not_active Ceased
  • 1994-08-26 EP EP94926556A patent/EP0777872A4/de not_active Withdrawn

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