EP0774705A2 - Comparator with hysteresis for use in a voltage regulating circuit - Google Patents

Abstract

The comparator circuit has a differential stage (D) forming a component of a cascade circuit (L,D,S,G) which has on one side of the differential stage a load stage (L) with load transistors (MN1,MP2) and on the other side a negative feed back stage (G). A reference voltage is applied both to the control electrode of a first load transistor (MN1), which has a high impedance input and supplies the voltage to be compared, and to the control electrode of a second load transistor (MP2). The first transistor represents a constant load impedance and a third load transistor (MP2) is connected in parallel with the second transistor which is switched on or off depending on signals from the comparator circuit. The result is that a further load impedance is either connected or not connected in parallel with the second transistor.

Description

The invention relates to a hysteresis-related comparator circuit for use as a comparison stage and control signal generator of an electrical voltage control circuit with a voltage source that supplies the voltage to be regulated, and a control circuit with such a comparator circuit.

There are electrical circuits for which a potential must be provided which is above the potential of the supply voltage source. An example are circuits with NMOS transistors which are on the side of the high supply voltage potential of their circuit and whose gate electrode must be supplied with a gate potential which is above the high supply voltage potential if they are to be turned on. Examples are CMOS circuits. Booster circuits are used to provide such a high gate potential. Bootstrap circuits are used for AC circuits. Charge pumps or voltage pump circuits are used for DC applications.

Such voltage pump circuits have a charging voltage capacitor which is charged to approximately twice the value of the supply voltage source, with the aid of the alternating voltage of a pump oscillator, which is usually provided in the form of a rectangular pulse sequence. This leads to electromagnetic radiation (EMR), which can be quite annoying, especially in DC voltage applications. Measures are therefore required to counter such EMR.

A reduction in the EMR can be achieved by reducing the frequency of the pump pulse sequence and / or by deliberately reducing the slope of the pump pulses. However, the main disadvantage of these measures is that they only reduce the problem with the EMR, but not eliminate it.

DE 37 23 579 C1 discloses a series voltage regulator with a comparator circuit which contains a differential stage, which is preceded by a load stage and which is followed by a current mirror circuit. In this known series voltage regulator, the comparator circuit is used to compare the output voltage and the input voltage of the regulator in order to switch off a control transistor acting on the series regulator branch when the input voltage of the regulator drops below a nominal regulator output voltage, in order to thereby mitigate malfunctions caused by voltage drops on the input side.

Electronics, Sept. 16, 1976, pages 42 and 44, discloses a voltage pump circuit in which the pump voltage is adjusted to a predetermined value, for which purpose a pump oscillator is switched on and off depending on the output signal of a comparator.

The object of the present invention is therefore to make available a circuit arrangement with which the problem of EMR can be completely eliminated in such pump circuits.

The basic idea for solving this task is as follows:
When the gate of the NMOS transistor mentioned is charged to the required pump voltage, the pumping process is ended, so that from then on the pumping frequency causing EMR no longer occurs. Since a MOS transistor has a very high gate input resistance, the pump voltage can be maintained for a relatively long time. In order not to counteract this, it is necessary to make the regulation of the pump voltage essentially loss-free, so that the capacitor holding the pump voltage is not burdened by the control circuit, that is to say, to discharge, which leads to the start of a new pumping process with the recurrence of EMR Episode.

This idea is realized with a comparator circuit which uses a differential stage for the virtually powerless detection of the voltage value to be subjected to a comparison, the one end of the load transistor and the other end a negative feedback stage and preferably a current mirror stage is used between the differential stage and the negative feedback stage. The control electrode of a first load transistor, which is a transistor with a high input impedance, for example a MOS transistor, is supplied with the voltage to be compared. A reference voltage is supplied to the control electrode of a second load transistor, on the basis of which this load transistor represents a constant load impedance. The second load transistor is connected in parallel with a third load transistor which conducts or blocks in dependence on the output signal of the comparator, so that the impedance of the second load transistor is connected in parallel or not in dependence on the output signal of the comparator.

To implement this idea in connection with a voltage control circuit, the invention makes available a hysteresis comparator circuit according to claim 3, which can be used in an electrical control circuit according to claim 15, in particular a control circuit for the pump voltage of a pump voltage circuit according to claim 16.

Developments of the comparator circuit according to the invention are specified in claims 2 and 4 to 14.

• Fig. 1 ein elektrisches Schaltbild, teilweise in Blockdarstellung, einer erfindungsgemäßen Pumpspannungsregelungsschaltung;
• Fig. 2 ein Schaltbild einer hysteresebehafteten Komparatorschaltung, die bei der Pumpspannungsregelungsschaltung der Figur 1 verwendbar ist; und
• Fig. 3 Spannungsverläufe, die bei der Komparatorschaltung nach Figur 2 auftreten.

The invention will now be explained in more detail by means of embodiments. In the accompanying drawings:

• 1 shows an electrical circuit diagram, partly in block form, of a pump voltage control circuit according to the invention;
• FIG. 2 shows a circuit diagram of a hysteresis comparator circuit which can be used in the pump voltage control circuit of FIG. 1; and
• Fig. 3 voltage waveforms that occur in the comparator circuit of Figure 2.

FIG. 1 shows a circuit diagram of a pump voltage control circuit with a supply voltage connection VA, to which the high potential VS of a supply voltage source is supplied. A series circuit comprising two diodes D1 and D2 is located between the supply voltage connection VA and a first input E1 of a comparator COM. The anode of D1 is connected to VA and the cathode of D2 is connected to E1. A second input E2 of the comparator COM is connected to a parallel circuit comprising two reference resistors RREF1 and RREF2. These are connected to ground potential at one end, while at the other end they are connected to E2, RREF1 directly and RREF2 via a first switch S1. A circuit node K between the two diodes D1 and D2 is connected to one side of a pump capacitor CP, the other side of which is connected to an output of an oscillator OSC, which supplies a pump pulse sequence with a pump frequency when a second switch S2 is switched on. Between the diode D2 and the first input E1 there is a parallel circuit comprising a load capacitor CL and a load resistor RL, which represent the input capacitance and the input resistance of the load to be fed with the pump voltage, in the case of the NMOS transistor mentioned, its gate capacitance or gate input resistance .

If the switch S2 is closed, the pump pulse sequence causes the pump capacitor CP to be charged in a manner known per se to a pump voltage VP which is approximately twice as large as the supply voltage VS. If, after reaching the desired pump voltage, switch S2 is opened to end the pumping process, the pump voltage is discharged via the load resistor RL. If the pump voltage VP has dropped below a predetermined threshold value, a new pumping process is started by closing, that is to say making the switch S2 conductive.

When a pumping process can be ended and when a new pumping process is required is determined with the aid of the comparator COM, on the output signal of which at a comparator output A it depends whether this output signal switches S2 switches conductive or non-conductive. In order to achieve two-point regulation with regard to the pump voltage VP, the comparator is designed with hysteresis behavior. For this purpose, the two reference resistors RREF1 and RREF2 are provided, of which, depending on the position of the switch S1, only the reference resistor RREF1 or the parallel connection of the two reference resistors RREF1 and RREF2 is effective. Since the input resistance RL of the NMOS transistor mentioned is very high, the time intervals between the times at which a pumping operation is carried out by closing the switch S2 can be very large if the input resistance of the input E1 of the comparator COM is also very large . No pump voltage operation takes place between these long time intervals, the pump oscillator can thus be switched off, so that no EMR occurs between these long time intervals.

An embodiment of a comparator according to the invention, which is subject to hysteresis and which loads the pump voltage source as little as possible, is shown in FIG. 2 and comprises the part of the circuit shown in FIG.

The hysteresis comparator COM according to FIG. 2 comprises, in cascade connection, between a supply voltage connection VA supplying the positive supply voltage VS and a ground connection GND forming the negative pole of the supply voltage source, a differential stage D, a load impedance stage L located on the high potential side of D, and a negative feedback stage located on the low potential side of D. G and between D and G a current mirror stage S.

The differential stage D has a first differential stage transistor QP1, a second differential stage transistor QP2 and a first current source I1. QP1 and QP2 are each designed as a bipolar PNP multi-collector transistor with two collectors. The base connections of QP1 and QP2 are jointly connected to GND via the first current source I1. One of the two collectors of each of the two differential stage transistors QP1 and QP2 is connected to the common base connection.

The current mirror stage S has a current mirror circuit with a current mirror diode QN1 in the form of a bipolar NPN transistor connected as a diode and a current mirror transistor QN2 in the form of a bipolar NPN transistor. The base connections of QN1 and QN2 are connected to one another in a manner customary for current mirrors.

The negative feedback stage G has a first negative feedback resistor R1 and a second negative feedback resistor R2.

The load impedance stage L has a first load transistor MN1 in the form of an N-channel MOS transistor, a second load transistor MP1 in the form of a P-channel MOS transistor and a third load transistor MP2 in the form of a P-channel MOS transistor. In addition, the load impedance stage L comprises a reference voltage source V1, which is connected between the gate of MP1 and VS, and a second current source, which is connected between the gate of MP2 and VS.

MN1, QP1, QN1 and R1 form a first series connection, while MP1, QP2, QN2 and R2 form a second series connection. R1 and R2 form negative feedback impedances for QP1 and QP2. MN1 forms a load impedance for QP1. The parallel connected load transistors MP1 and MP2 together form a load impedance for QP2.

Between QP2 and QN2 there is a circuit node SK to which the base of a bipolar NPN switching transistor QN3 is connected. Its emitter is connected to GND, while its collector is connected both to the gate of MP2 and to the second current source I2. A common connection point between current source I2, gate of MP2 and collector of QN3 forms the comparator output A.

The load impedance formed by the first load transistor MN1 depends on the pump voltage VP present at the first comparator input E1. The load impedance at the emitter of QP2 formed by the parallel connection of the two load transistors MP1 and MP2 depends on Potential at the comparator output. MP1 is kept permanently in a certain state of conduction by means of the reference voltage source VR, that is to say it permanently has a constant predetermined impedance, which is also referred to below as the first reference load impedance. The third load transistor MP2 is switched conductive or non-conductive depending on the potential occurring at the comparator output A. Its impedance, hereinafter also referred to as the second reference load impedance, depends on the potential at the comparator output A. If MP2 is switched non-conductive, the load impedance effective at the emitter of QP2 is practically only formed by the constant impedance of MP1. If MP2 is switched on, the load impedance effective at the emitter of QP2 is formed by connecting the first and second reference load impedance in parallel. Depending on the potential at the comparator output A, a lower or a higher load impedance acts on the emitter of QP2.

Between the supply voltage connection VA and the gate of MN1 there is a protective diode D3 for protecting the gate-source path of MN1 against overvoltages that could be supplied via the supply voltage connection VA.

In Figure 1, the impedance of the conductive load transistor MP2 is represented by RREF2, while the impedance of the permanently conductive load transistor MP1 is represented by RREF1. The switch S1 in FIG. 1 is indicated by the load transistor MP2 operated as a switch.

The mode of operation of the comparator circuit shown in FIG. 2 is now considered with the aid of FIG. 3. An operating state is initially assumed in which the pump voltage VP is below the desired voltage value, as is initially the case when the voltage supply is switched on. This time period is identified in FIG. 3 by T1.

In order to achieve an increase in the pump voltage VP, the pump pulse sequence must be able to reach the pump capacitor CP in FIG. 1.

A potential value must therefore be present at the comparator output A, which controls the switch S2 in FIG. 1 to the conductive state, and thus controls the oscillator to the switched-on state.

The impedance of the load transistor MN1 depends on the instantaneous voltage value of the pump voltage VP present at the comparator input E1. This pump voltage determines the value of the gate-source voltage VGS of MN1. Provided that VP is sufficiently large to drive the load transistor MN1 into the conductive state at all, the lower the pump voltage VP and the lower the higher the pump voltage VP, the greater the load impedance formed by MN1. The load impedance formed in each case by MN1 therefore represents a measure of the respectively existing value of the pump voltage VP. Since the pump voltage VP is applied to the gate of a MOS transistor, the instantaneous or actual value of the pump voltage VP is practically recorded and evaluated ineffective. The pump voltage source, namely the pump capacitor CP, is thus practically not loaded and discharged by this type of actual value detection.

The impedance value of MN1, which represents the respective actual value of the pump voltage, is compared with the reference impedance, as it is formed by the load impedance of MP1 alone or the parallel connection of the load impedances of MP1 and MP2, depending on the switching state of the third load transistor MP2. Since the pump voltage VP increases after switching on the supply voltage, the load impedance formed by MN1 accordingly decreases, the load impedance effective at the emitter of QP2 must be correspondingly lower than the impedance of MN1, which is available, as long as the pump voltage VP has the desired voltage value or setpoint has not yet reached. The comparator circuit therefore behaves asymmetrically in the phase in which the pump voltage VP is still below the desired value, since the two differential stage transistors QP1 and QP2 of differential stage D are offered differently sized load impedances. Since the load impedance acting on the emitter of QP2 is lower than the load impedance acting on the emitter of QP1, more current flows through QP2 than through QP1. The one on the SK circuit node from the collector Current supplied by QP2 is therefore higher than the current supplied by the collector of QP1 via the current mirror stage S to the circuit node SK. In addition, the voltage drop across the negative feedback resistor R2 is greater than the voltage drop across the negative feedback resistor R1, which leads to an increase in the potential at the circuit node SK. These two phenomena cause the switching transistor QN3 to be on, so that a low potential occurs at its collector, which leads to the conduction of the third load transistor MP2. The parallel connection of the first reference load impedance formed by MP1 and the second reference load impedance formed by the conductive MP2 thus takes effect at the emitter of QP2.

Since, in the state of pump voltage VP being too low, there is a low potential at the collector of QN3 and thus at comparator output A, the entire control circuit is to be designed such that a pump pulse sequence is applied to pump capacitor CP at comparator output A.

During its rise, the pump voltage VP eventually becomes so great that the value of the impedance of MN1 has dropped to that impedance value which results from the parallel connection of the first and second reference load impedances. At this moment the comparator circuit achieves symmetrical behavior. If this symmetrical behavior is lost again with a slight further increase in the pump voltage value, the comparator output A goes into the other of the two possible states: the comparator output A assumes high potential. This is because the load impedance value effective at the emitter of QP1 has become lower than the load impedance value effective at the emitter of QP2 and accordingly the current flowing through QP1 has become higher than the current flowing through QP2. The current balance at the circuit node SK reverses accordingly and because of the smaller current through QP2, the voltage drop across the negative feedback resistor R2 and thus the potential at the circuit node SK has dropped. As a result, the switching transistor QN3 turns off. This leads on the one hand to the already mentioned high potential value at the comparator output A and on the other hand to Block the third load transistor MP2. From this point on, only the constant first reference load impedance formed by MP1 is effective at the emitter of QP2.

Due to the transition of the potential at the comparator output A to a high potential value, the further application of the pump capacitor CP in FIG. 1 with pump pulses is prevented.

This state is reached at the end of time period T1 in FIG. 3. During the subsequent time period T2, no pump pulses occur, the pump voltage VP remains practically constant during a first section T2a of the time section T2 and the potential at the comparator output A, designated VSA in FIG. 3, is at a high value.

Since MOS transistors also do not have an infinitely high gate-source input resistance, and possibly due to other influences, the pump capacitor CP may gradually discharge and thus the pump voltage value may drop gradually. If the gate of a MOS transistor is controlled with the pump voltage and the actual value measurement of the pump voltage is carried out in accordance with the comparator circuit according to the invention by applying the pump voltage to the gate of a MOS transistor, the period of time during which the pump voltage value reached at the end of the period T1 has dropped appreciably is usually very long. However, in order to be able to use FIG. 3 to show what happens when the pump voltage value has dropped by a predetermined amount after reaching the desired value, it is assumed in the second subsection T2b in FIG. 3 that the pump voltage value drops rapidly. This leads to a corresponding increase in the load impedance formed by MN1. When this has risen to the first reference load impedance formed by MP1 and rises only slightly beyond it, the comparator circuit tilts back into the state initially considered, in which the potential at the comparator output A assumes a low potential value. This state is reached at the end of the time period T2 and leads to the pump capacitor CP now again pump impulses are applied. During a period of time, which is denoted by T3 in FIG. 3, the pump voltage value increases again due to this application of CP with pump pulses, until at the end of the period T3, in which the value of the load impedance formed by MN1 returns to the value of that of MP1 and the conductive MP2 jointly formed reference load impedance has dropped into the high potential state at the comparator output A, which leads to the blocking of the application of CP with further pump pulses. This state persists during the time period T4 in FIG. 3.

The pump voltage control circuit shown in FIG. 1 and containing the comparator circuit according to FIG. 2 thus effects two-point control between a high pump voltage threshold value and a low pump voltage threshold value, which are designated in FIG. 3 by VPH or VPL. The hysteresis leading to this two-point control is brought about by the controllable connection and disconnection of the impedance formed by MP2 to and from the permanent, constant load impedance formed by MP1.

The comparator circuit according to FIG. 2 was previously considered to be part of a pump voltage control circuit. However, this comparator circuit can also be used advantageously for other purposes. It is suitable for any application in which an input variable is to be compared with a hysterical reference variable with practically no performance. Because the variable to be measured is applied to the gate of a MOS transistor, such a practically powerless measurement of the variable of interest or to be monitored is possible.

With the comparator circuit according to the invention, not only can a practically powerless measurement of the voltage value to be monitored or regulated be achieved, but the threshold value determining the regulation process can be easily programmed by selecting the voltage value of the reference voltage source V1. In the case of a comparator circuit of this type designed as an integrated circuit, it would be possible to provide a plurality of reference voltage sources, which one each could be made programmable according to the threshold value required in the special case.

I_{D MN1}

= I_{D MP1}

V_{DS MN1}

= V_{DS MP1} = V_DS

V_{th MN1}

= V_{th MP1} = V_th

V_{GS MN1}

= a*V1

V_{GS MP1}

= V1

$$\begin{array}{c}\begin{array}{c}{\text{βMN1 V1 - V}}_{\text{th}}{\text{- V}}_{\text{DS}}\text{* 0,5}\\ {\text{βMP1 a * V1 - V}}_{\text{th}}{\text{- V}}_{\text{DS}}\text{* 0,5}\\ {\text{β = Const. *}}_{\text{L}}^{\text{W}}\end{array}\end{array}$$

The use of multi-collector transistors for QP1 and QP2, in each of which a collector is connected to the base, leads to a high transconductance or steepness due to the resulting non-linear diode behavior of each of the two differential transistors QP1 and QP2 at their emitters, so that by means of the difference stage D very small voltage differences can be determined, and thus very small differences in the load impedances that act on the emitter of QP1 or on the emitter of QP2. Therefore, with the same drain currents, the drain-source voltage of the first load transistor MN1 must be equal to the drain-source voltage of the second load transistor MP1 in order to achieve balanced conditions at the current mirror stage S. The gate-source voltage of MP1 is given by the reference voltage V1 of the reference voltage source. In simplified equations for unsaturated CMOS transistors, the threshold potential required to reach the high potential at the comparator output A can be calculated as a multiplier factor a of the reference voltage V1, with the assumptions listed below.

I _{D MN1}

= I _{D MP1}

V _{DS MN1}

= V _{DS MP1} = V _DS

V _{th MN1}

= V _{th MP1} = V _th

V _{GS MN1}

= a * V1

V _{GS MP1}

= V1

$$\begin{array}{c}\begin{array}{c}{\text{βMN1 V1 - V}}_{\text{th}}{\text{- V}}_{\text{DS}}\text{* 0.5}\\ {\text{βMP1 a * V1 - V}}_{\text{th}}{\text{- V}}_{\text{DS}}\text{* 0.5}\\ {\text{β = const. *}}_{\text{L}}^{\text{W}}\end{array}\end{array}$$

I_{D MN1}, I_{D MP1}

= Drainstrom von MN1 bzw. MP1

V_{DS MN1}, V_{DS MP1}

= Drain-Source-Spannung von MN1 bzw. MP1

V_{th MN1}, V_{th MP1}

= Schwellenspannung von MN1 bzw. MP1

V_{GS MN1}, V_{GS MP1}

= Gate-Source-Spannung von MN1 bzw. MP1

V1

= Referenzspannung der Referenzspannungsquelle

β

= Transkonduktanz (Steilheit) eines MOS-Transistors

β_MN1, β_MP1

= Transkonduktanz von MN1 bzw. MP1

W

= Kanalbreite

L

= Kanallänge

In the above formulas:

I _{D MN1} , I _{D MP1}

= Drain current of MN1 or MP1

V _{DS MN1} , V _{DS MP1}

= Drain-source voltage of MN1 or MP1

V _{th MN1} , V _{th MP1}

= Threshold voltage of MN1 or MP1

V _{GS MN1} , V _{GS MP1}

= Gate-source voltage of MN1 or MP1

V1

= Reference voltage of the reference voltage source

β

= Transconductance (slope) of a MOS transistor

β _MN1 , β _MP1

= Transconductance of MN1 or MP1

W

= Channel width

L

= Channel length

To determine the threshold value, the ratio of the transconductances of MN1 and MP1 must be set, using the respective W / L ratio. The threshold value can thus be selected as a function of the channel widths and the channel lengths of the two CMOS transistors MN1 and MP1.

A hysteresis can be achieved by connecting the third load transistor MP2 in parallel to the second load transistor MP1, the channel type of which is also opposite to that of MN1 and which is a transistor with a P-channel. The amount of hysteresis can also be selected by selecting the length and width of the channel.

In the context of the invention, it is not necessary to select the transistors of the comparator circuit all with the channel type or conductivity type, as are indicated in FIG. 2. If, instead of a positive pump voltage, which is assumed in FIG. 2, a negative pump voltage is required, the comparator circuit shown in FIG. 2 can be reversed in that the load transistors are shifted to the ground side (GND) and the opposite channel type is selected, whereby for the Transistors of the differential stage D and the current mirror stage S selects corresponding transistors of opposite conductivity type.

Claims (17)

Hysteresis comparator circuit for practically powerless detection of a voltage value to be subjected to a comparison, with a differential stage (D), which is part of a cascade circuit (L, D, S, G) that has a load stage (L) on one side of the differential stage (D) Load transistors (MN1, MP1) and on the other side of the differential stage (D) has a negative feedback stage (G), the control electrode of a first load transistor (MN1), which is a transistor with a high input impedance, the voltage to be supplied to the comparison delivered and the control electrode of a second load transistor (MP1) is supplied with a reference voltage, on the basis of which this second load transistor (MP1) represents a constant load impedance, and wherein the second load transistor (MP1) is connected in parallel with a third load transistor (MP2) which is dependent on conducts or blocks an output signal of the comparator circuit, so that the impedance of the second Load transistor (MP1), depending on the output signal of the comparator circuit, a further load impedance is connected in parallel or not. Comparator circuit according to Claim 1, in which a current mirror stage (S) is connected between the differential stage (D) and the negative feedback stage (G). Comparator circuit with hysteresis for use as a comparison stage and control signal generator of an electrical voltage control circuit with a voltage source (CP) supplying the voltage to be regulated, the output voltage (VP) of which can be changed by means of an actuating signal supplied by an output of the comparator circuit,
being the comparator circuit a) has a comparator input (E1) with the output voltage (VP) of the voltage source (CP) and a comparator output (A) providing the control signal; b) is fed by a supply voltage source with a first supply voltage pole (VS) and a second supply voltage pole (GND); c) a differential stage (D) with a first differential stage transistor (QP1) and a second differential stage transistor (QP2), each having a control electrode, a first main line electrode and a second main line electrode, c1) whose control electrodes are coupled together with the second supply voltage pole (GND), c2) whose first main line electrodes are each coupled to the first supply voltage pole (VS) via a first load impedance or via a second load impedance, and c3) whose second main line electrodes are each coupled via a negative feedback impedance to the second supply voltage pole (GND); and where d) the first load impedance is generated by a first load transistor (MN1), which is a transistor with a high input impedance and which has a control electrode coupled to the comparator input (E1), so that the first load impedance is dependent on the output voltage (VP) Voltage source (CP) depends, and e) the second load impedance has a parallel connection with a second load transistor (MP1) and a third load transistor (MP2), wherein e1) a reference voltage source (VR) is connected between a control electrode of the second load transistor (MP1) and the first supply voltage pole (VS), which controls the second load transistor (MP1) in such a way that it has a predetermined first reference load impedance, and e2) the third load transistor (MP2) can be switched on or off under control of the control signal at the comparator output (A), such that the third load transistor (MP2) with a control signal which is at the comparator output (A) occurs when the rising output voltage (VP) of the voltage source (CP) reaches an upper threshold value (VPH), blocking and with an actuating signal that occurs at the comparator output (A) when the falling output voltage (VP) of the voltage source (CP ) reaches a lower threshold value (VPL), is switched conductive, representing a predetermined second reference load impedance. Comparator circuit according to claim 1 or 2,
in which the first load transistor (MN1) is a MOS transistor. Comparator circuit according to one of Claims 1 to 4,
in which the three load transistors (MN1, MP1, MP2) are each formed by a MOS transostor, the gate electrodes of which form the control electrodes. Comparator circuit according to claim 5,
in which the first load transistor (MN1) on the one hand and the second (MP1) and the third load transistor (MP2) on the other hand are of different channel types. Comparator circuit according to claim 5 or 6,
in which the gate electrode of the third load transistor (MP2) is coupled to the comparator output (A). Comparator circuit according to one of Claims 1 to 7,
in which the two differential stage transistors (QP1, QP2) are each formed by a bipolar transistor. Comparator circuit according to Claim 8,
in which the two differential stage transistors (QP1, QP2) on the emitter side are each connected to the associated load impedance and on the collector side are each connected to the associated negative feedback impedance (R1, R2). Comparator circuit according to 8 or 9,
in which between the differential stage transistors (QP1, QP2) and the negative feedback impedances (R1, R2) a current mirror circuit (S) with a current mirror diode (QN1) connected between the first differential stage transistor (QP1) and its negative feedback impedance (R1) and one between the second differential stage transistor ( QP2) and its negative feedback impedance (R2) switched current mirror transistor (QN2) is arranged. Comparator circuit according to one of Claims 8 to 10,
in which the two differential stage transistors (QP1, QP2) are each formed by a multi-collector transistor, a first of the collectors being coupled to the associated negative feedback impedance (R1, R2) and a second one of the collectors being connected to the base of the respective differential stage transistor (QP1, QP2) is. Comparator circuit according to one of Claims 3 to 11,
in which the control electrodes of the two differential stage transistors (QP1, QP2) are coupled to the second supply voltage pole (GND) via a first current source (I1). Comparator circuit according to one of Claims 3 to 12,
at which the comparator output (A) with a connection point (SK) between the one differential stage transistor (QP2) and the associated negative feedback impedance (R2), in the case of the interposition of a current mirror circuit (S) between this differential stage transistor (QP2) and the associated current mirror element (QN2) , is coupled. Comparator circuit according to claim 13,
in which a switching transistor (QN3) is connected between the connection point (SK) and the comparator output (A), the control electrode of which is connected to the connection point (SK), the main path of which is between the control electrode of the third load transistor (MP2) and the second supply voltage pole (GND) is connected and the control electrode of the third load transistor (MP2) connected main line electrode is connected to the comparator output. Comparator circuit according to claim 14,
in which the switching transistor (QN3) is formed by a bipolar transistor, the conductivity type of which is opposite to the conductivity type of the bipolar differential stage transistors (QP1, QP2) and the one main line electrode on the one hand with the control electrode of the third load transistor (MP2) and on the other hand via a second current source (I2 ) is connected to the first supply voltage pole (VS). Electrical control circuit with a comparator circuit according to one of claims 1 to 15. Control circuit according to claim 16,
for regulating a pump voltage of a voltage pump circuit above the supply voltage value of the first supply voltage pole (VS) to a predetermined pump voltage value, wherein: a) the voltage pump circuit has a pump voltage accumulator (CP) which can be acted upon on the input side by a controllable pump circuit switch device (S2) with an alternating charge voltage (OSC), the accumulated pump voltage increasing when the pump circuit switch device (S2) is conductively controlled and when the pump circuit switch device is non-conductively controlled ( S2) reduced in accordance with a certain discharge time constant; and b) a switching control input of the pump circuit switch device (S2) is coupled to the comparator output (A) and an output of the pump voltage accumulator (CP) delivering the pump voltage (VP) is coupled to the comparator input (E1).

Images