EP0774705A2 - Comparateur à hystérésis pour utilisation dans un circuit régulateur de tension - Google Patents

Comparateur à hystérésis pour utilisation dans un circuit régulateur de tension Download PDF

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Publication number
EP0774705A2
EP0774705A2 EP96118126A EP96118126A EP0774705A2 EP 0774705 A2 EP0774705 A2 EP 0774705A2 EP 96118126 A EP96118126 A EP 96118126A EP 96118126 A EP96118126 A EP 96118126A EP 0774705 A2 EP0774705 A2 EP 0774705A2
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EP
European Patent Office
Prior art keywords
transistor
voltage
load
comparator
impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP96118126A
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German (de)
English (en)
Other versions
EP0774705A3 (fr
EP0774705B1 (fr
Inventor
Udo John
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics GmbH
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SGS Thomson Microelectronics GmbH
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Publication date
Application filed by SGS Thomson Microelectronics GmbH filed Critical SGS Thomson Microelectronics GmbH
Publication of EP0774705A2 publication Critical patent/EP0774705A2/fr
Publication of EP0774705A3 publication Critical patent/EP0774705A3/fr
Application granted granted Critical
Publication of EP0774705B1 publication Critical patent/EP0774705B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/267—Current mirrors using both bipolar and field-effect technology

Definitions

  • the invention relates to a hysteresis-related comparator circuit for use as a comparison stage and control signal generator of an electrical voltage control circuit with a voltage source that supplies the voltage to be regulated, and a control circuit with such a comparator circuit.
  • circuits for which a potential must be provided which is above the potential of the supply voltage source There are electrical circuits for which a potential must be provided which is above the potential of the supply voltage source.
  • An example are circuits with NMOS transistors which are on the side of the high supply voltage potential of their circuit and whose gate electrode must be supplied with a gate potential which is above the high supply voltage potential if they are to be turned on.
  • Examples are CMOS circuits.
  • Booster circuits are used to provide such a high gate potential. Bootstrap circuits are used for AC circuits.
  • Charge pumps or voltage pump circuits are used for DC applications.
  • Such voltage pump circuits have a charging voltage capacitor which is charged to approximately twice the value of the supply voltage source, with the aid of the alternating voltage of a pump oscillator, which is usually provided in the form of a rectangular pulse sequence.
  • EMR electromagnetic radiation
  • a reduction in the EMR can be achieved by reducing the frequency of the pump pulse sequence and / or by deliberately reducing the slope of the pump pulses.
  • the main disadvantage of these measures is that they only reduce the problem with the EMR, but not eliminate it.
  • DE 37 23 579 C1 discloses a series voltage regulator with a comparator circuit which contains a differential stage, which is preceded by a load stage and which is followed by a current mirror circuit.
  • the comparator circuit is used to compare the output voltage and the input voltage of the regulator in order to switch off a control transistor acting on the series regulator branch when the input voltage of the regulator drops below a nominal regulator output voltage, in order to thereby mitigate malfunctions caused by voltage drops on the input side.
  • the object of the present invention is therefore to make available a circuit arrangement with which the problem of EMR can be completely eliminated in such pump circuits.
  • the basic idea for solving this task is as follows: When the gate of the NMOS transistor mentioned is charged to the required pump voltage, the pumping process is ended, so that from then on the pumping frequency causing EMR no longer occurs. Since a MOS transistor has a very high gate input resistance, the pump voltage can be maintained for a relatively long time. In order not to counteract this, it is necessary to make the regulation of the pump voltage essentially loss-free, so that the capacitor holding the pump voltage is not burdened by the control circuit, that is to say, to discharge, which leads to the start of a new pumping process with the recurrence of EMR Episode.
  • a comparator circuit which uses a differential stage for the virtually powerless detection of the voltage value to be subjected to a comparison, the one end of the load transistor and the other end a negative feedback stage and preferably a current mirror stage is used between the differential stage and the negative feedback stage.
  • the control electrode of a first load transistor which is a transistor with a high input impedance, for example a MOS transistor, is supplied with the voltage to be compared.
  • a reference voltage is supplied to the control electrode of a second load transistor, on the basis of which this load transistor represents a constant load impedance.
  • the second load transistor is connected in parallel with a third load transistor which conducts or blocks in dependence on the output signal of the comparator, so that the impedance of the second load transistor is connected in parallel or not in dependence on the output signal of the comparator.
  • the invention makes available a hysteresis comparator circuit according to claim 3, which can be used in an electrical control circuit according to claim 15, in particular a control circuit for the pump voltage of a pump voltage circuit according to claim 16.
  • FIG. 1 shows a circuit diagram of a pump voltage control circuit with a supply voltage connection VA, to which the high potential VS of a supply voltage source is supplied.
  • a series circuit comprising two diodes D1 and D2 is located between the supply voltage connection VA and a first input E1 of a comparator COM.
  • the anode of D1 is connected to VA and the cathode of D2 is connected to E1.
  • a second input E2 of the comparator COM is connected to a parallel circuit comprising two reference resistors RREF1 and RREF2. These are connected to ground potential at one end, while at the other end they are connected to E2, RREF1 directly and RREF2 via a first switch S1.
  • a circuit node K between the two diodes D1 and D2 is connected to one side of a pump capacitor CP, the other side of which is connected to an output of an oscillator OSC, which supplies a pump pulse sequence with a pump frequency when a second switch S2 is switched on.
  • a parallel circuit comprising a load capacitor CL and a load resistor RL, which represent the input capacitance and the input resistance of the load to be fed with the pump voltage, in the case of the NMOS transistor mentioned, its gate capacitance or gate input resistance .
  • the pump pulse sequence causes the pump capacitor CP to be charged in a manner known per se to a pump voltage VP which is approximately twice as large as the supply voltage VS. If, after reaching the desired pump voltage, switch S2 is opened to end the pumping process, the pump voltage is discharged via the load resistor RL. If the pump voltage VP has dropped below a predetermined threshold value, a new pumping process is started by closing, that is to say making the switch S2 conductive.
  • the comparator COM When a pumping process can be ended and when a new pumping process is required is determined with the aid of the comparator COM, on the output signal of which at a comparator output A it depends whether this output signal switches S2 switches conductive or non-conductive.
  • the comparator In order to achieve two-point regulation with regard to the pump voltage VP, the comparator is designed with hysteresis behavior.
  • the two reference resistors RREF1 and RREF2 are provided, of which, depending on the position of the switch S1, only the reference resistor RREF1 or the parallel connection of the two reference resistors RREF1 and RREF2 is effective.
  • the time intervals between the times at which a pumping operation is carried out by closing the switch S2 can be very large if the input resistance of the input E1 of the comparator COM is also very large . No pump voltage operation takes place between these long time intervals, the pump oscillator can thus be switched off, so that no EMR occurs between these long time intervals.
  • FIG. 2 An embodiment of a comparator according to the invention, which is subject to hysteresis and which loads the pump voltage source as little as possible, is shown in FIG. 2 and comprises the part of the circuit shown in FIG.
  • the hysteresis comparator COM comprises, in cascade connection, between a supply voltage connection VA supplying the positive supply voltage VS and a ground connection GND forming the negative pole of the supply voltage source, a differential stage D, a load impedance stage L located on the high potential side of D, and a negative feedback stage located on the low potential side of D. G and between D and G a current mirror stage S.
  • the differential stage D has a first differential stage transistor QP1, a second differential stage transistor QP2 and a first current source I1.
  • QP1 and QP2 are each designed as a bipolar PNP multi-collector transistor with two collectors.
  • the base connections of QP1 and QP2 are jointly connected to GND via the first current source I1.
  • One of the two collectors of each of the two differential stage transistors QP1 and QP2 is connected to the common base connection.
  • the current mirror stage S has a current mirror circuit with a current mirror diode QN1 in the form of a bipolar NPN transistor connected as a diode and a current mirror transistor QN2 in the form of a bipolar NPN transistor.
  • the base connections of QN1 and QN2 are connected to one another in a manner customary for current mirrors.
  • the negative feedback stage G has a first negative feedback resistor R1 and a second negative feedback resistor R2.
  • the load impedance stage L has a first load transistor MN1 in the form of an N-channel MOS transistor, a second load transistor MP1 in the form of a P-channel MOS transistor and a third load transistor MP2 in the form of a P-channel MOS transistor.
  • the load impedance stage L comprises a reference voltage source V1, which is connected between the gate of MP1 and VS, and a second current source, which is connected between the gate of MP2 and VS.
  • MN1, QP1, QN1 and R1 form a first series connection, while MP1, QP2, QN2 and R2 form a second series connection.
  • R1 and R2 form negative feedback impedances for QP1 and QP2.
  • MN1 forms a load impedance for QP1.
  • the parallel connected load transistors MP1 and MP2 together form a load impedance for QP2.
  • circuit node SK Between QP2 and QN2 there is a circuit node SK to which the base of a bipolar NPN switching transistor QN3 is connected. Its emitter is connected to GND, while its collector is connected both to the gate of MP2 and to the second current source I2. A common connection point between current source I2, gate of MP2 and collector of QN3 forms the comparator output A.
  • the load impedance formed by the first load transistor MN1 depends on the pump voltage VP present at the first comparator input E1.
  • the load impedance at the emitter of QP2 formed by the parallel connection of the two load transistors MP1 and MP2 depends on Potential at the comparator output.
  • MP1 is kept permanently in a certain state of conduction by means of the reference voltage source VR, that is to say it permanently has a constant predetermined impedance, which is also referred to below as the first reference load impedance.
  • the third load transistor MP2 is switched conductive or non-conductive depending on the potential occurring at the comparator output A. Its impedance, hereinafter also referred to as the second reference load impedance, depends on the potential at the comparator output A.
  • the load impedance effective at the emitter of QP2 is practically only formed by the constant impedance of MP1. If MP2 is switched on, the load impedance effective at the emitter of QP2 is formed by connecting the first and second reference load impedance in parallel. Depending on the potential at the comparator output A, a lower or a higher load impedance acts on the emitter of QP2.
  • a protective diode D3 for protecting the gate-source path of MN1 against overvoltages that could be supplied via the supply voltage connection VA.
  • the impedance of the conductive load transistor MP2 is represented by RREF2, while the impedance of the permanently conductive load transistor MP1 is represented by RREF1.
  • the switch S1 in FIG. 1 is indicated by the load transistor MP2 operated as a switch.
  • the pump pulse sequence In order to achieve an increase in the pump voltage VP, the pump pulse sequence must be able to reach the pump capacitor CP in FIG. 1.
  • a potential value must therefore be present at the comparator output A, which controls the switch S2 in FIG. 1 to the conductive state, and thus controls the oscillator to the switched-on state.
  • the impedance of the load transistor MN1 depends on the instantaneous voltage value of the pump voltage VP present at the comparator input E1. This pump voltage determines the value of the gate-source voltage VGS of MN1. Provided that VP is sufficiently large to drive the load transistor MN1 into the conductive state at all, the lower the pump voltage VP and the lower the higher the pump voltage VP, the greater the load impedance formed by MN1.
  • the load impedance formed in each case by MN1 therefore represents a measure of the respectively existing value of the pump voltage VP. Since the pump voltage VP is applied to the gate of a MOS transistor, the instantaneous or actual value of the pump voltage VP is practically recorded and evaluated ineffective. The pump voltage source, namely the pump capacitor CP, is thus practically not loaded and discharged by this type of actual value detection.
  • the impedance value of MN1 which represents the respective actual value of the pump voltage, is compared with the reference impedance, as it is formed by the load impedance of MP1 alone or the parallel connection of the load impedances of MP1 and MP2, depending on the switching state of the third load transistor MP2. Since the pump voltage VP increases after switching on the supply voltage, the load impedance formed by MN1 accordingly decreases, the load impedance effective at the emitter of QP2 must be correspondingly lower than the impedance of MN1, which is available, as long as the pump voltage VP has the desired voltage value or setpoint has not yet reached.
  • the comparator circuit therefore behaves asymmetrically in the phase in which the pump voltage VP is still below the desired value, since the two differential stage transistors QP1 and QP2 of differential stage D are offered differently sized load impedances. Since the load impedance acting on the emitter of QP2 is lower than the load impedance acting on the emitter of QP1, more current flows through QP2 than through QP1. The one on the SK circuit node from the collector Current supplied by QP2 is therefore higher than the current supplied by the collector of QP1 via the current mirror stage S to the circuit node SK. In addition, the voltage drop across the negative feedback resistor R2 is greater than the voltage drop across the negative feedback resistor R1, which leads to an increase in the potential at the circuit node SK.
  • the entire control circuit is to be designed such that a pump pulse sequence is applied to pump capacitor CP at comparator output A.
  • the comparator circuit achieves symmetrical behavior. If this symmetrical behavior is lost again with a slight further increase in the pump voltage value, the comparator output A goes into the other of the two possible states: the comparator output A assumes high potential. This is because the load impedance value effective at the emitter of QP1 has become lower than the load impedance value effective at the emitter of QP2 and accordingly the current flowing through QP1 has become higher than the current flowing through QP2.
  • the pump capacitor CP may gradually discharge and thus the pump voltage value may drop gradually. If the gate of a MOS transistor is controlled with the pump voltage and the actual value measurement of the pump voltage is carried out in accordance with the comparator circuit according to the invention by applying the pump voltage to the gate of a MOS transistor, the period of time during which the pump voltage value reached at the end of the period T1 has dropped appreciably is usually very long. However, in order to be able to use FIG. 3 to show what happens when the pump voltage value has dropped by a predetermined amount after reaching the desired value, it is assumed in the second subsection T2b in FIG. 3 that the pump voltage value drops rapidly.
  • the pump voltage value increases again due to this application of CP with pump pulses, until at the end of the period T3, in which the value of the load impedance formed by MN1 returns to the value of that of MP1 and the conductive MP2 jointly formed reference load impedance has dropped into the high potential state at the comparator output A, which leads to the blocking of the application of CP with further pump pulses.
  • This state persists during the time period T4 in FIG. 3.
  • the pump voltage control circuit shown in FIG. 1 and containing the comparator circuit according to FIG. 2 thus effects two-point control between a high pump voltage threshold value and a low pump voltage threshold value, which are designated in FIG. 3 by VPH or VPL.
  • the hysteresis leading to this two-point control is brought about by the controllable connection and disconnection of the impedance formed by MP2 to and from the permanent, constant load impedance formed by MP1.
  • the comparator circuit according to FIG. 2 was previously considered to be part of a pump voltage control circuit. However, this comparator circuit can also be used advantageously for other purposes. It is suitable for any application in which an input variable is to be compared with a hysterical reference variable with practically no performance. Because the variable to be measured is applied to the gate of a MOS transistor, such a practically powerless measurement of the variable of interest or to be monitored is possible.
  • the threshold value determining the regulation process can be easily programmed by selecting the voltage value of the reference voltage source V1.
  • the comparator circuit of this type designed as an integrated circuit, it would be possible to provide a plurality of reference voltage sources, which one each could be made programmable according to the threshold value required in the special case.
  • the ratio of the transconductances of MN1 and MP1 must be set, using the respective W / L ratio.
  • the threshold value can thus be selected as a function of the channel widths and the channel lengths of the two CMOS transistors MN1 and MP1.
  • a hysteresis can be achieved by connecting the third load transistor MP2 in parallel to the second load transistor MP1, the channel type of which is also opposite to that of MN1 and which is a transistor with a P-channel.
  • the amount of hysteresis can also be selected by selecting the length and width of the channel.
  • the comparator circuit shown in FIG. 2 can be reversed in that the load transistors are shifted to the ground side (GND) and the opposite channel type is selected, whereby for the Transistors of the differential stage D and the current mirror stage S selects corresponding transistors of opposite conductivity type.
  • GND ground side

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Electronic Switches (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Dc-Dc Converters (AREA)
EP96118126A 1995-11-16 1996-11-12 Comparateur à hystérésis pour utilisation dans un circuit régulateur de tension Expired - Lifetime EP0774705B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19542823 1995-11-16
DE19542823A DE19542823C2 (de) 1995-11-16 1995-11-16 Hysteresebehaftete Komparatorschaltung zur Verwendung bei einer Spannungsregelungsschaltung

Publications (3)

Publication Number Publication Date
EP0774705A2 true EP0774705A2 (fr) 1997-05-21
EP0774705A3 EP0774705A3 (fr) 1998-01-28
EP0774705B1 EP0774705B1 (fr) 2003-07-23

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EP96118126A Expired - Lifetime EP0774705B1 (fr) 1995-11-16 1996-11-12 Comparateur à hystérésis pour utilisation dans un circuit régulateur de tension

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US (1) US5739705A (fr)
EP (1) EP0774705B1 (fr)
DE (1) DE19542823C2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1209793A1 (fr) * 2000-11-23 2002-05-29 Semiconductor Components Industries LLC Dispositif et procédé de commande d' une alimentation électrique
KR100433362B1 (ko) * 2002-07-11 2004-06-07 에이디반도체(주) 임피던스 비교 집적회로
US7646115B2 (en) * 2007-01-05 2010-01-12 Standard Microsystems Corporation Regulator circuit with multiple supply voltages
US9356587B2 (en) * 2014-02-19 2016-05-31 Stmicroelectronics S.R.L. High voltage comparison circuit
JP6498649B2 (ja) * 2016-10-17 2019-04-10 株式会社東海理化電機製作所 レベルシフタ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3723579C1 (de) 1987-07-16 1989-02-16 Sgs Halbleiterbauelemente Gmbh Laengsspannungsregler

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3938055A (en) * 1975-01-17 1976-02-10 Aeronutronic Ford Corporation (Formerly Philco-Ford Corporation) High performance differential amplifier
US4259601A (en) * 1978-12-08 1981-03-31 Motorola, Inc. Comparison circuit having bidirectional hysteresis
JPS55144437U (fr) * 1979-04-05 1980-10-16
CA1203290A (fr) * 1982-04-28 1986-04-15 Yoshio Shimizu Circuit comparateur de signaux
JPS58202613A (ja) * 1982-05-21 1983-11-25 Nec Corp 差動増幅回路
JPH03248616A (ja) * 1990-02-27 1991-11-06 Seiko Instr Inc コンパレータ回路
JPH04196812A (ja) * 1990-11-28 1992-07-16 Fujitsu Ltd レベル・コンバータ
DE69320326T2 (de) * 1993-05-07 1998-12-24 Sgs Thomson Microelectronics Mit niedriger Versorgungsspannung arbeitender, eine Hysteresis aufweisender Komparator
FR2719135B1 (fr) * 1994-04-21 1996-06-28 Sgs Thomson Microelectronics Circuit de limitation de tension avec comparateur à hystérésis.

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3723579C1 (de) 1987-07-16 1989-02-16 Sgs Halbleiterbauelemente Gmbh Laengsspannungsregler

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONICS, 16 September 1976 (1976-09-16), pages 42 - 44

Also Published As

Publication number Publication date
DE19542823A1 (de) 1997-05-22
EP0774705A3 (fr) 1998-01-28
DE19542823C2 (de) 1997-09-04
EP0774705B1 (fr) 2003-07-23
US5739705A (en) 1998-04-14

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