Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0491—Virtual ground arrays
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
  • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
  • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
  • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

Definitions

• the present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to a contactless flash EPROM cell array that utilizes a low current channel erase mechanism.
• EPROM electrically programmable read only memory
• FIG. 2 shows a cross-section of an individual ETOX cell 12 taken along line A-A (i.e. along polysilicon (poly 2) word line 16) in Fig. 1.
• Fig. 3 shows a cross-section of an ETOX cell 12 taken along line B-B (i.e. along buried N+ bit line 18) in Fig. l.
• the ETOX array 10 is based on the standard "T- shaped" ETOX cell. As shown in Figs. 2 and 3, the ETOX cell 12 is implemented utilizing a very thin gate oxide 20 (about 100A) and graded N+/N- source regions 22 to prevent disturbances due to junction breakdown when the cell 12 is being erased.
• the ETOX cell is written in the conventional EPROM manner. That is, hot electrons are injected from the graded source region 22 into the polysilicon (polyl) floating gate 24 when the poly 2 word line 16 and the N+ bit line (drain) 14 are both high.
• erasing the ETOX cell 12 is performed by Fowler-Nordheim tunneling of electrons from the floating gate 24 through the thin oxide 20 to the graded source region 22 when the source region 22 is high, the drain 14 is floating and the word line 16 is low.
• the source 22 is graded to prevent junction breakdown during the erase operation.
• the above-described ETOX array utilizes a cell architecture that requires one drain contact for every two cells in the array.
• the relatively large size of the contacts places a severe scaling limitation on the array.
• Eitan array 30 is the use of a "cross-point" EPROM cell that is defined by the crossing of perpendicular polyl floating gate lines 32 and poly2 word lines 34 in a virtual ground array.
• metal 36 contacts silicon every two N * bit lines 38 to define the drain lines of the array and the non-contacted N * bit lines 40 are connected to ground only via access transistors 42 driven by access select lines 44 to define the source lines of the array.
• each drain bit line 38 is contacted only once every 64 cells, each block of 64 cells on the same drain bit line 38 constituting one "segment.”
• each block of 64 cells on the same drain bit line 38 constituting one "segment.”
• the Bergemont array 50 differs from the Eitan array in two primary aspects.
• alternate N * bit lines receive an additional phosphorous implant to provide graded N * /N ' source bit lines 52 for the array cells.
• the N * /N ' graded source bit lines 52 rather than the N * drain bit lines 56, are contacted by metal 54 in segmented fashion; the intermediate node N * drain bit l nes 56 are non- contacted.
• the N * drain bit lines 56 of the Bergemont array can receive a boron ii ⁇ plant to provide N * /P " drain lines 56.
• the Bergemont array retains the basic "cross-point" cell architecture in that the cells of the array are defined by the perpendicular crossing of polyl floating gate lines 58 and poly2 word lines 60.
• the Bergemont cell includes polyl extensions over ield oxide (Fox) in the array in order to achieve a correct coupling from the control gate (i.e. word line 60) to the floating gate 58, particularly in flash applications wherein the thickness of the floating gate oxide is approximately 100A.
• the Bergemont architecture facilitates a flash erase mode, wherein an erase voltage is applied to each of the N * /N * source bit lines 52 while both access select lines 62 are held at ground. This causes Fowler-Nordheim tunneling of electrons from the floating gate 58 to the source side 52 of the cell.
• the graded N * /N * source junction prevents junction breakdown.
• the above-described Bergemont AMG flash EPROM array provides a significant advance over the conventional flash ETOX technology by achieving a contac less array.
• the double-diffused source lines place a scaling constraint on the effective channel length of the cell.
• the present invention provides a contactless flash EPROM array formed in a silicon substrate of P- type conductivity.
• thin tunnel oxide is formed between the substrate and the overlying polysilicon floating gate EPROM cells.
• the array is programmed in a conventional AMG EPROM cell array manner.
• the channel erase of a selected row of EPROM cells is accomplished by allowing all bit lines to float, applying a negative erase voltage to the word line of the selected row and holding the substrate at the supply voltage.
• Fig. 1 is layout illustrating a portion off a conventional T-shaped ETOX EPROM cell array.
• Fig. 2 is a cross-sectional view illustrating an individual ETOX cell taken along line A-A of Fig. 1.
• Fig. 3 is a cross-sectional view illustrating an individual ETOX cell taken along line B-B of Fig. 1.
• Fig. 4A is a cross-sectional view illustrating conventional ETOX cell programming by hot electron injection to the cell's floating gate.
• Fig. 4B is a cross-sectional view illustrating
• Fig. 5 is a layout drawing illustrating a portion of a conventional cross-point AMG EPROM cell array.
• Fig. 6 is a schematic diagram illustrating an equivalent circuit for the Fig. 5 layout.
• Fig. 7 is a layout drawing illustrating a portion of a cross-point contactless flash EPROM cell array that utilizes source-side erase from the cell's floating gate to a contacted, graded source bit line.
• Fig. 8 is a cross-section drawing taken along a word line in the Fig. 7 layout.
• Fig. 9 is a schematic diagram illustrating an equivalent circuit for the Fig. 7 layout.
• Fig. 10a is a cross-section drawing illustrating a triple-well structure utilizable in fabricating a contactless flash EPROM array in accordance with the present invention.
• Fig. 10b is a cross-section drawing illustrating an alternative or triple-well structure utilizable in fabricating a contactless flash EPROM array in accordance with the present invention.
• Fig. 11 is a cross-section drawing illustrating formation of field oxide structure in the P-well memory cell array portion of the triple-well structure shown in Fig. 10a or Fig. 10b.
• Figs. 12-15 illustrate a process flow for fabricating an contactless flash EPROM array in accordance with the present invention.
• Fig. 16 is a schematic diagram illustrating the bias conditions for programming a selected cell in an a contactless flash EPROM array in accordance with the present invention.
• Fig. 17 is a layout drawing illustrating two EPROM cells in a contactless flash EPROM array in accordance with the present invention.
• Fig. 18 is a cross-section drawing of a Fig. 16 flash EPROM cell taken along line A-A in Fig. 16.
• Fig. 19 is a cross-section drawing of a Fig. 16 flash EPROM cell taken along line B-B in Fig. 16.
• Fig. 20 is a schematic diagram illustrating the bias conditions for erasing the cells on a selected word line in a contactless flash EPROM array in accordance with the present invention.
• Fig. 21 is a timing diagram illustrating the waveforms of the selected word line voltage and of the P-well voltage for erasing the cells on the selected word line in a flash EPROM array in accordance with the present invention.
• Fig. 22 is a cross-section drawing illustrating the erase mechanism in a flash EPROM array in accordance with the present invention. Detailed Description of the Invention
• the fabrication process begins with a silicon substrate 100 of N-type conductivity.
• an initial oxide layer (notpshown) is grown over the substrate 100.
• Aj notoresist£mask$ is then formed over the initial oxide layer and patterned to define selected surface areas of the N-type substrate 100.
• the exposed surface areas of the substrate 100 are then implanted with a P-type dopant to form P- well regions 102.
• the photoresist mask is then stripped from the surface of the oxide and a thermal drive-in step is performed to further define the P- well regions 102.
• the initial oxide layer is then removed from the substrate 100 and a second oxide layer (not shown) is
• the substrate 100 is photoresist, which is patterned to define substrate surface areas within those P-well regions 102 which will ultimately contain the peripheral P-channel circuitry.
• N-type dopant is implanted into the exposed substrate surface areas of the peripheral P- wells 102 to define N-well regions 104.
• the photoresist is then stripped and a further drive-in step for both the N-well regions 104 and the P-well regions 102 is performed. Following the drive-in step, the second oxide layer is removed, resulting in the structure shown in Fig. 10a.
• the initial processing steps result in the formation of a triple-well structure.
• the N-well regions 104 in the periphery will be utilized for the fabrication of PMOS devices.
• the P-well regions 102 in the periphery will be utilized for the formation of NMOS devices.
• the P-well regions 102 in the memory cell array portion of the substrate 10 will be utilized for formation of EPROM storage cell devices and the access transistors.
• the intermediate substrate region is maintained at the supply voltage (Vcc) to keep the P-well/N junctions reversed biased.
• Fig. 10b shows in alternate triple well structure that can also be utilized for fabrication of a contactless flash EPROM array in accordance with the invention. In the Fig.
• the P- well is formed in an N-well which, in turn, is formed in a silicon substrate of P-type conductivity.
• the important feature of the triple-well structure shown in each of Fig. 10a and Fig. 10b is the provision of a P-well formed in N-type silicon, such that, as described in greater detail below, the P-well can be maintained at the supply voltage to facilitate channel erase of the EPROM array fabricated in the P-well.
• a pad oxide is first grown on the surface of the substrate 100, followed by deposition of an overlying nitride layer.
• the pad oxide/nitride composite is ⁇ aaskedjwith photoresist, which is then patterned to expose regions of underlying nitride; these regions will ultimately define field oxide (FOX) regions.
• the nitride is then etched photoresist is stripped.
• a P-type field mask implant is performed to define P-well field regions.
• a boron field ion implant is then performed through exposed regions.
• the field implant mask is then stripped and field oxide regions (FOX) 106 are formed, as shown in Fig. 11.
• FIGs. 12-15 illustrate the subsequent sequential steps in the process flow.
• Each of Figs. 12-15 includes a plan view of the structure at that stage of the process flow and the following three cross- sectional views in the corresponding structure: (l) in the word line direction in the EPROM cell array (designated "A/A"), (2) in the word line direction in the access transistor area (designated "B/B”), and (3) in the polyl direction perpendicular to the word line in both the cell array and the access transistor area (designated "C/C” ) .
• the process flow continues with conventional steps common to this type of process and then, with the formation of a 100A floating gate tunnel oxide 108 on the surface substrate 100.
• a layer of polysilicon (polyl) 110 is then deposited to a thickness of about 1500A and doped with phosphorus at a dose of 2-5xl0 15 at low implant energy.
• a composite dielectric layer of oxide/nitride/oxide 112, commonly called "ONO" is formed on the polyl 110.
• ONO oxide/nitride/oxide
• a photoresist mask 114 is used to define spaced-apart parallel stripes on the ONO 112.
• the ONO 112 and underlying polyl 110 are then plasma etched to form spaced-apart parallel stacks 116 of ONO/polyl.
• an arsenic implant self- aligned to polyl, is then performed to define N * bit lines 120.
• the photoresist is then stripped and a "differential" oxide is grown over the N * bit line areas to provide substantial latitude in subsequent ONO and/or poly plasma etch steps. If, for example, a poly plasma etch is performed without formation of the differential oxide, then the poly plasma etch step could lead to the "trenching" of silicon in the exposed N * bit lines areas. For this reason, this step contributes to the equivalent oxide loss during ONO etch and is, hence, called differential oxidation. Following the differential oxidation step, a mask step called "protect array" is performed.
• This mask is used to etch the ONO/polyl layer (the polyl mask is a dark field mask) leaving ONO/polyl out of the array. This avoids the use of an extra mask to protect the periphery during the subsequent N * bit line arsenic implant.
• the arsenic implant is then performed on the full wafer with no mask.
• the ONO/polyl layers are plasma etched and the underlying floating gate oxide is removed in a wet chemistry etch utilizing diluted HF. Then, the photoresist is stripped.
• the next step in the process involves the growth of 200A gate oxide everywhere in the gate channel regions out of the array.
• a threshold voltage mask (V tp mask) is then performed and P-channel regions are boron implanted to provide the right threshold voltage.
• a second layer 122 of 2000A polysilicon (poly2) is deposited and doped with phosphorous.
• a 2500A tungsten suicide layer 124 is deposited and a poly2 mask is performed.
• the poly2 mask 126 has three functions: defining the gates of the transistors in the periphery, defining the gates of the access transistors in the array, and defining the word lines of the EPROM cells.
• -li ⁇ the tungsten suicide layer 122 and the poly2 layer 124 are plasma etched. It is noted that the access transistors are flash EPROM cells with larger width than the array flash EPROM cells to drive larger current than the array cells.
• the photoresist is not stripped.
• a second photoresist is spun on and a new masking step is performed.
• This new mask called self-aligned etch, maintains the integrity of the photoresist of the preceding poly2 mask in order to allow self-aligned etch to poly2 of the residual ONO/poly 1 layer between the lines in the flash EPROM cell array, this etch ends the construction of the flash EPROM cell.
• the above-described array is programmed in the conventional AMG manner. That is, to program cell A, the source bit line N of cell A held at an intermediate voltage Vd (approx 5-7V) , source bit line N+l is held at ground, and source bit line N-l is allowed to float. Select line 1 is biased to the supply voltage Vcc (approx. 5V) and select line 2 is held at ground. The word line WC1 associated with cell A is taken to the programming voltage Vpp (approx. 12-13V0, while the remaining word lines (WC2/WL3) are grounded. These bias conditions result in current flow as shown by the arrow in Fig. 16, which results in electron injection from the drain of cell A to the floating gate of cell A, thus programming cell A.
• the source and drain bit lines are kept open, i.e. floating.
• the remaining rows are "erase inhibited” by applying the supply voltage Vcc to their associated word lines.
• These bias conditions cause Fowler-Nordheim current to flow from the floating gates of the cells in the selected rows to the p-well.
• the erase operation requires low current, thus allowing the use of a high voltage negative charge pump.
• the band-to-band tunneling and the large erase currents inherent to the conventional source erase operation are eliminated, suggesting a larger cycling endurance for the channel erase device.
• the select transistors are flash cells with a W_ 2 times the of a cell in the array in order to pull down Vss on the intermediate node.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Semiconductor Memories (AREA)
• Non-Volatile Memory (AREA)

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• 1995
  • 1995-11-27 EP EP95942910A patent/EP0742956A1/de not_active Withdrawn
  • 1995-11-27 WO PCT/US1995/015395 patent/WO1996017384A1/en not_active Application Discontinuation
  • 1995-11-27 KR KR1019960704077A patent/KR970700943A/ko not_active IP Right Cessation

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