EP0740438A1 - Verfahren und vorrichtung zur detektion zyklischer codes - Google Patents

Verfahren und vorrichtung zur detektion zyklischer codes Download PDF

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Publication number
EP0740438A1
EP0740438A1 EP94918549A EP94918549A EP0740438A1 EP 0740438 A1 EP0740438 A1 EP 0740438A1 EP 94918549 A EP94918549 A EP 94918549A EP 94918549 A EP94918549 A EP 94918549A EP 0740438 A1 EP0740438 A1 EP 0740438A1
Authority
EP
European Patent Office
Prior art keywords
bit
cyclic code
division
remainder
divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94918549A
Other languages
English (en)
French (fr)
Other versions
EP0740438A4 (de
Inventor
Shigeki Toyo Comm. Equipment Co. Ltd. YANAGISAWA
Tetsuya Toyo Comm. Equipment Co.Ltd. MORIZUMI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Communication Equipment Co Ltd
Original Assignee
Toyo Communication Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Communication Equipment Co Ltd filed Critical Toyo Communication Equipment Co Ltd
Publication of EP0740438A1 publication Critical patent/EP0740438A1/de
Publication of EP0740438A4 publication Critical patent/EP0740438A4/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/33—Synchronisation based on error coding or decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5673—Coding or scrambling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment

Definitions

  • This invention relates to a method and device for detecting a cyclic code, and more specifically to means for establishing cell synchronization in the ATM communication system which uses a cyclic code for coding data.
  • ATM Asynchronous Transmission Mode
  • ISDN Integrated Services Digital Network
  • a cell used for transmitting data consists of 5 bytes for the header and 48 bytes for the information field, 53 bytes in total, for example.
  • the 5 bytes or 40 bits of the header is a shortened cyclic code which consists of a 32-bit information point and an 8-bit check point called HEC (Header Error Control).
  • HEC Header Error Control
  • the generating polynominal of the shortened cyclic code is X 8 + X 2 + X + 1, and the header is formed by adding X 6 + X 4 + X 2 + 1 (bit pattern 01010101) to the shortened cyclic code.
  • breakpoints between cells must be detected to correctly receive cells continuously transmitted on a transmission line at the receiving side. This process is called cell synchronization and generally performed by utilizing the header of cells.
  • X 6 + X 4 + X 2 + 1 added to the header at the transmitting side is obtained as the remainder of division of the 40 bits of the header by the generating polynominal at the receiving side as described above, and this principle is utilized.
  • the receiver When the receiver is completely out of synchronization with receive data (hunting state), it takes the latest 40 bits out of the received data shifting by one bit, performs the division, and enters the pre-synchronized state (quasi-synchronized state) considering that 40 input bits to be the header of a cell if the remainder of the division is X 6 + X 4 + X 2 + 1.
  • the receiver performs the same test on the next 40 bits at the position shifted by one bit. The receiver repeats this test until it enters the pre-synchronized state. After the receiver has entered the pre-synchronized state, it tests HEC at the position expected to be the header of the next cell a predetermined times, and determines that a complete synchronization has been established.
  • the first method is to form a 40-bit shift register by connecting a 32-bit shift register and the divider 1 in series, load this 40-bit shift register with the latest 40 bits in parallel each time one bit of data is input, perform the division on the 40 bits, and detect the output, as shown in Figure 4.
  • the shift register is required to operate 32 times as fast as the transmission rate on transmission line.
  • Such a high speed operation is very difficult especially in wide-band ISDN which uses a high speed transmission.
  • Another method is to connect 40 dividers, each constructed so as to be cleared every time when 40 bits are input, in parallel, input data serially to these 40 dividers clearing them at the timing staggered by one bit from each other in turn, and test the output of the divider the data fed to which has reached 40 bits, as shown in Figure 5.
  • This ATM cell synchronization method has a problem that 40 dividers are needed and hence the size of the circuit becomes large.
  • Data transmission using a cyclic code or shortened cyclic code is used not only in ATM, but also in various fields, and there is also the same problem in the detection of a cyclic code or certain portions in data bit sequence by utilizing a cyclic code.
  • This invention was made to solve the above described problem in conventional cyclic code detection and ATM cell synchronization, and the object of this invention is to provide a method and device for detecting the position of an n-bit cyclic code or shortened cyclic code by a simple circuitry without need of high-speed circuits and further an ATM cell synchronization system using a cyclic code.
  • the first invention of this application is a method which performs the operation of division on a serially input continuous bit sequence by a generating polynominal successively and detects an n-bit cyclic code or shortened cyclic code contained in the bit sequence by using the result, characterized by subtracting the remainder of division by the generating polynomial before performing the division in advance.
  • the second invention of this application is a method for detecting an n-bit cyclic code or shortened cyclic code based on a predetermined degree-m generating polynomial G(X), characterized by subtracting the remainder of division of the (n+1)th bit X n by said generating polynomial G(X) (remainder of X n /G(X)) from the remainder of division of the latest n bits (candidate n bits for the bit sequence of the cyclic code) by G(X) if the coefficient of X n is not 0 each time one bit is input, and determining that the candidate n bits is the cyclic code or shortened cyclic code when the result of the subtraction is zero or a predetermined bit pattern added to the cyclic code.
  • the third invention of this application is a device for detecting n-bit unit data sequences decoded as a cyclic code or shortened cyclic code based on a degree-m generating polynominal G(X), characterized by comprising
  • FIG. 1 is the structural diagram of an embodiment into which the ATM cell synchronization of this invention is realized.
  • Figure 2 is the structural diagram of an 8-bit feedback shift register which functions as a divider.
  • Figure 3 is the structural diagram for explanation of the problem to be solved.
  • Figure 4 is the structural diagram of the first method for solving the problem illustrated by Figure 3.
  • Figure 5 is the structural diagram of the second method for solving the problem illustrated by Figure 3.
  • the present invention is described below in detail, taking for example an embodiment of the present invention applied to the cell synchronization for ATM.
  • This embodiment supposes that the generating polynominal G(X) is 8-bit X 8 + X 2 + X + 1, that a cell consists of 5 bytes of header and 48 bytes of information field, 53 bytes in total, and that the header consists of 32-bit information point and 8-bit of HEC.
  • FIG. 1 is the structural diagram of the principal part of an embodiment of a cyclic code detecting device for implementing the ATM cell synchronization of this invention.
  • This device has the aforementioned divider 1 with exclusive OR circuits 12 added between the 1st and 2nd stages, the 5th and 6th stages, and the 6th and 7th stages.
  • the output of the last stage of the aforementioned 40-bit shift register 10 is input to the newly added exclusive OR circuits 12, 12, 12.
  • the device comprises a decoder (DEC) 11 for detecting when the values of bits on the divider 1 are all zero or form a predetermined bit pattern.
  • DEC decoder
  • the bit sequence held at that time is the header of the cell.
  • this invention can be widely used as a method for detecting a predetermined length of cyclic code or shortened cyclic code or a code with a predetermined bit pattern added to them in a continuous bit sequence without being limited to ATM.
  • this embodiment makes it possible to implement a method for detecting the position of an n-bit cyclic code or shortened cyclic code in a continuous bit sequence by means of a simple circuitry without need of high-speed circuits by subtracting the remainder of division of X n by the generating polynominal from the divider.
  • this invention Since this invention has the construction and performs the function as described above, it has a remarkable effect of making it possible to detect an n-bit cyclic code or shortened cyclic code in a continuous bit sequence by means of a simple circuitry.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Algebra (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
EP94918549A 1993-06-30 1994-06-22 Verfahren und vorrichtung zur detektion zyklischer codes Withdrawn EP0740438A4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP5186622A JPH0787090A (ja) 1993-06-30 1993-06-30 巡回符号検出方法及び装置
JP186622/93 1993-06-30
PCT/JP1994/000998 WO1995001683A1 (fr) 1993-06-30 1994-06-22 Procede et appareil de detection d'un code cyclique

Publications (2)

Publication Number Publication Date
EP0740438A1 true EP0740438A1 (de) 1996-10-30
EP0740438A4 EP0740438A4 (de) 1998-04-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP94918549A Withdrawn EP0740438A4 (de) 1993-06-30 1994-06-22 Verfahren und vorrichtung zur detektion zyklischer codes

Country Status (7)

Country Link
US (1) US5764876A (de)
EP (1) EP0740438A4 (de)
JP (1) JPH0787090A (de)
KR (1) KR960701537A (de)
SG (1) SG82556A1 (de)
TW (1) TW257908B (de)
WO (1) WO1995001683A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2293738B (en) * 1994-09-30 1999-03-31 Plessey Telecomm Cyclic redundancy code checking

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5935249A (en) * 1997-02-26 1999-08-10 Sun Microsystems, Inc. Mechanism for embedding network based control systems in a local network interface device
US7126950B2 (en) * 2000-02-14 2006-10-24 Nec Corporation Method and system for transmission and reception of asynchronously multiplexed signals
US6928608B2 (en) * 2001-08-14 2005-08-09 Optix Networks Ltd. Apparatus and method for accelerating cyclic redundancy check calculations
JP2003078421A (ja) * 2001-09-04 2003-03-14 Canon Inc 符号系列の先頭位置検出方法とその装置、それを用いた復号方法とその装置
US7484160B2 (en) * 2005-03-04 2009-01-27 Tellabs Operations, Inc. Systems and methods for delineating a cell in a communications network

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2533091A1 (fr) * 1982-09-13 1984-03-16 Cii Honeywell Bull Systeme de detection et de correction d'erreurs de transmission d'un message binaire utilisant un code cyclique detecteur et correcteur d'erreurs de type reed-solomon entrelace
US4677623A (en) * 1983-11-11 1987-06-30 Hitachi, Ltd. Decoding method and apparatus for cyclic codes
DE3785211T2 (de) * 1987-10-30 1993-10-07 Ibm Mittel für Datenintegritätssicherung.
JPH03272224A (ja) * 1990-03-20 1991-12-03 Canon Inc 情報信号処理方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DODDS D E ET AL: "ATM FRAMING ACQUISITION" COMMUNICATIONS, COMPUTERS AND POWER IN THE MODERN ENVIRONMENT, SASKATOON, 17 May 1993, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 56-60, XP000380229 *
See also references of WO9501683A1 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2293738B (en) * 1994-09-30 1999-03-31 Plessey Telecomm Cyclic redundancy code checking

Also Published As

Publication number Publication date
SG82556A1 (en) 2001-08-21
US5764876A (en) 1998-06-09
JPH0787090A (ja) 1995-03-31
TW257908B (de) 1995-09-21
EP0740438A4 (de) 1998-04-22
WO1995001683A1 (fr) 1995-01-12
KR960701537A (ko) 1996-02-24

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