EP0735779B1 - Démodulateur de signal couleur applicable pour télévision PAL et SECAM - Google Patents

Démodulateur de signal couleur applicable pour télévision PAL et SECAM Download PDF

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Publication number
EP0735779B1
EP0735779B1 EP96104608A EP96104608A EP0735779B1 EP 0735779 B1 EP0735779 B1 EP 0735779B1 EP 96104608 A EP96104608 A EP 96104608A EP 96104608 A EP96104608 A EP 96104608A EP 0735779 B1 EP0735779 B1 EP 0735779B1
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Prior art keywords
signal
signals
color
pulse
level
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German (de)
English (en)
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EP0735779A1 (fr
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Ikuo Osawa
Keijiro Ueki
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority claimed from JP07198495A external-priority patent/JP3244398B2/ja
Priority claimed from JP07198595A external-priority patent/JP3253482B2/ja
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Publication of EP0735779A1 publication Critical patent/EP0735779A1/fr
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/642—Multi-standard receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N11/00—Colour television systems
    • H04N11/06—Transmission systems characterised by the manner in which the individual colour picture signal components are combined
    • H04N11/12—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous signals only
    • H04N11/14—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous signals only in which one signal, modulated in phase and amplitude, conveys colour information and a second signal conveys brightness information, e.g. NTSC-system
    • H04N11/16—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous signals only in which one signal, modulated in phase and amplitude, conveys colour information and a second signal conveys brightness information, e.g. NTSC-system the chrominance signal alternating in phase, e.g. PAL-system

Definitions

  • the present invention relates to a color signal demodulator circuit suitable for use in PAL (Phase Alternation by Line) type and SECAM (Sequential Coulours A Memoire) type TV receivers.
  • PAL Phase Alternation by Line
  • SECAM Sequential Coulours A Memoire
  • a PAL system is adapted to invert the phase of the R-Y signal for every 1H and to send it with a B-Y signal which has a predetermined phase. Variations in hue caused by phase distortion in a transmission system can be reduced by summing the color signals in adjacent horizontal lines in the TV receiver.
  • the PAL type color signal demodulator circuit in the prior art performs said summing function for the color signals, including R-Y and B-Y signals, before they have been demodulated.
  • a delay glass line was used for the 1H delay.
  • a CCD Charge Coupled Device
  • color signals will be delayed by 1H after they have been demodulated.
  • Fig. 1 shows part of a TV receiver which includes such a PAL type color signal demodulator circuit.
  • a chrominance signal is input from input terminal 1 to B-Y and R-Y demodulators 2, 3.
  • the B-Y and R-Y demodulators 2, 3 also receive different carrier waves and demodulate the B-Y and R-Y signals.
  • CCDIC 7 is designed to delay the demodulated color-difference signal by a 1H period and comprises first and second CCD circuits 8, 9 for performing such a delay.
  • the output signals of the first and second CCD circuits 8, 9 are returned back to IC 6 wherein they are clamped by first and second clamp circuits 10, 11.
  • the output signals of the first and second clamp circuits 10, 11 are passed through LPFs 12 and 13 to remove any unnecessary components resulting from the transfer clocks in the first and second CCD circuits 8, 9 and thereafter applied to first and second adders 14, 15.
  • the first and second adders 14, 15 also receive the color-difference signals (B-Y and R-Y signals) directly from LPFs 4 and 5, thereby adding the input signal and the 1H delayed signal. Such an addition can reduce the phase distortion created by the transmission system and thereby avoid variations in the color phase.
  • the B-Y demodulator 2 of Fig. 1 receives a carrier wave (CW) having a given phase as shown in Fig. 2(b) while the R-Y demodulator 3 receives a carrier wave having its phase inverted every 1H as shown in Fig. 2(c).
  • the B-Y demodulator 2 uses the carrier wave of Fig. 2(b) to demodulate the B-Y signal component of Fig. 2(a).
  • a B-Y as shown in Fig. 2(d) is then output from the B-Y demodulator 2 of Fig. 1.
  • the R-Y demodulator 3 demodulates the R-Y signal.
  • a similar procedure is performed for 2H (next horizontal period) and 3H (the following horizontal period), resulting in provision of such demodulated outputs as shown in Figs. 2(d) and 2(e).
  • the signals, having a 1H difference, shown in Figs. 2(d) and 2(e) When the signals, having a 1H difference, shown in Figs. 2(d) and 2(e) are added, it creates a demodulated signal. More particularly, if the signals for 1H and 2H in Fig. 2(d) are summed, a B-Y signal at zero degrees as shown in Fig. 2(f) can be provided since the 1H and 2H signals are at zero degrees. Similarly, if the signals for 1H and 2H in Fig. 2(e) are summed, an R-Y signal at 90 degrees as shown in Fig. 2(g) can be provided since the 1H and 2H signals are at 90 degrees.
  • the B-Y demodulator 2 of Fig. 1 uses the carrier wave of Fig. 2(b) to demodulate such a B-Y' signal component as shown in Fig. 2(a) and delivers such a B-Y' signal as shown in Fig. 2(d).
  • the carrier wave of Fig. 2(b) will demodulate the B-Y axis component in such an R-Y' signal component as shown in Fig. 2(a) and also demodulate such an R-Y' signal (distortion component) as shown in Fig. 2(d).
  • the signal for 2H is also demodulated.
  • a signal as shown in Fig. 2(f) will be provided.
  • the R-Y signal (distortion component) for 1H is canceled by the R-Y' signal (distortion component) for 2H.
  • the B-Y' signal can be detected as the necessary B-Y axis component.
  • the R-Y demodulator 3 of Fig. 1 uses the carrier wave of Fig. 2(c) to demodulate such an R-Y' signal component as shown in Fig. 2(a) and delivers such an R-Y' signal as shown in Fig. 2(e).
  • the carrier wave of Fig. 2(c) will demodulate the R-Y axis component in such a B-Y' signal component as shown in Fig. 2(a) and also demodulate such a B-Y' signal as shown in Fig. 2(e).
  • the signal for 2H is also demodulated.
  • the signals for 1H and 2H in Fig. 2(e) are summed, a signal as shown in Fig. 2(g) is provided. In this case, the B-Y' signal, which is an unnecessary distortion component is canceled.
  • phase distortion created by the transmission system can be reduced to prevent variations in color phase through the addition of the first and second adders 14, 15.
  • the demodulated R-Y and B-Y signals from the first and second adders 14, 15 are then matrixed by a matrix circuit 16 which in turn delivers R-Y, B-Y and G-Y signals through its output terminals 17 and 19.
  • the circuit shown in Fig. 1 can demodulate PAL type color signals.
  • the R-Y' signal vector at zero degrees in Fig. 2(f) will not always be equal to the R-Y' signal vector at 180 degrees from the previous 1H. Even if these signal vectors are summed, a distortion component will remain.
  • R-Y and B-Y signals are alternately received by the color signal demodulator circuit every 1H. Therefore, 1H delayed signals are necessary to interpolate the B-Y and R-Y signals during the time when no B-Y or R-Y signal respectively is being received by the circuit.
  • the 1H delay circuit is thus used.
  • the delay circuit is formed by CCD, it raises the problem that attenuation is created by the delay circuit such that a differential level is created between the delayed B-Y and R-Y signals and the original R-Y and B-Y signals.
  • the present invention adds an additional pulse having a given signal level to a demodulated signal at a given location.
  • Level regulating means is adapted to regulate the level of the additional pulse in the delay signal into a level which is same as before the additional pulse was added. If a non-delayed demodulated signal is added to the level regulated delay signal, the level of both the signals is more equal to provide a more accurate output signal.
  • the phase of the R-Y signal (first color-difference signal) is inverted for every horizontal line period (1H).
  • the demodulator means uses a carrier signal which is alternately inverted in phase to demodulate the R-Y signal.
  • the demodulator means uses a carrier signal which always has the same phase to demodulate the B-Y signal. If the phase of the carrier signal is different from that of an input signal, the other (unnecessary) components are respectively superimposed on the demodulated R-Y and B-Y signals due to the differential phase. However, such superimposed unnecessary components are then canceled when the adder means adds the signals delayed by one horizontal line period (1H) to the non-delayed signals.
  • the unnecessary components can be reliably removed since the delayed and non-delayed signals are equalized in level.
  • the SECAM type system contains R-Y and B-Y signals alternated for every one horizontal line period (1H).
  • the R-Y and B-Y signals are alternately provided to form two different demodulated signals which are in turn used to form two different delay signals (delayed by one horizontal line period (1H)). These delay signals are added to the non-delayed signal to provide the normal R-Y and B-Y signals.
  • the present invention can equalize the signal level for every horizontal line since the delayed and non-delayed signals are equalized in level.
  • the present invention can reliably compensate for attenuation.
  • the attenuation due to the delay for each color-difference signal is normally the same. If an additional pulse is added to one of the two color-difference signals to provide a signal corresponding to the attenuation, the two delay signals can be regulated in level by using the level of the additional pulse.
  • the additional pulse is set at a given period before the burst gate pulse which is used to gate the color burst signal.
  • the additional pulse is formed based on a sand castle pulse which is formed by superimposing the burst gate pulse on a fly-back pulse.
  • the color burst gate pulse superimposed on the sand castle pulse has a slightly longer length generated with an earlier timing, unlike the conventional burst gate pulse.
  • the conventional burst gate pulse can be used to stagger the clamp timing in a clamp means for clamping a pedestal level from the additional pulse addition timing.
  • Fig. 1 is a block diagram of a PAL type color signal demodulator circuit according to the prior art.
  • Figs. 2(a) - 2(g) are vector diagrams illustrating the operation of the color signal demodulator circuit shown in Fig. 1.
  • Fig. 3 is a block diagram of a color signal demodulator circuit according to the present invention.
  • Figs. 4(a) - 4(d) show waveforms illustrating the operation of the color signal demodulator circuit shown in Fig. 3.
  • Figs. 5(a) - 5(c) show waveforms illustrating the operation of the color signal demodulator circuit shown in Fig. 3.
  • Fig. 6 is a circuit diagram of the detector 32 and comparator 35.
  • Figs. 7(a) - 7(d) show waveforms illustrating the operation of the color signal demodulator circuit shown in Fig. 3.
  • Fig. 8 is a circuit diagram of the SCP discriminator 103 shown in Fig. 3.
  • Figs. 9(a) - 9(e) are vector diagrams for illustrating the operation of the color signal demodulator circuit shown in Fig. 3.
  • Fig. 3 shows a color signal demodulator circuit according to the present invention, in which reference numeral 20 denotes an input terminal to which a color image signal is applied; 21 a synchronous separation circuit for separating a horizontal synchronous signal; 22 a horizontal AFC (Automated Frequency Control) for generating a horizontal synchronous signal and a divided output having a frequency 32f H (wherein f H is the frequency of a horizontal synchronous signal) which is synchronous with the horizontal synchronous signal; 23 a divider circuit for dividing the 32f H signal into clock signals, the divider being reset by the horizontal synchronous signal to generate a BGP (Burst Gate Pulse) and an addition timing pulse; 24 a chrominance signal extracting circuit; 25 a burst extracting circuit for extracting a burst signal; 26 a carrier wave forming circuit for forming a carrier wave depending on the burst signal; 27 an addition circuit for adding an ALC additional pulse to the output signal of the B-Y demodulator 2 at its given location
  • a PAL type color image signal (TV signal) input through the input terminal 20 contains a chrominance signal which is extracted by the chrominance signal extracting circuit 24.
  • the extracted chrominance signal is then applied to the B-Y and R-Y demodulators 2, 3.
  • a burst signal (color burst signal) is also extracted from the PAL type color image signal by the burst extracting circuit 25.
  • the extracted burst signal is then applied to the carrier wave forming circuit 26.
  • B-Y and R-Y carrier waves synchronized in phase with a corresponding B-Y or R-Y signal are respectively applied from the carrier wave forming circuit 26 to the B-Y and R-Y demodulators 2, 3 by which B-Y and R-Y signals are demodulated.
  • a horizontal synchronous signal is also extracted from the PAL type color image signal by the synchronous separation circuit 21, the extracted signal is then applied to the horizontal AFC circuit 22.
  • the horizontal AFC circuit 22 is a PLL (Phase Locked Loop) for locking the horizontal synchronous signal in phase.
  • the phase locked 32f H signal is then applied to the divider circuit 23 as a clock signal while the horizontal synchronous signal is also applied to the same divider circuit 23 as a reset signal.
  • the divider circuit 23 is adapted to generate a logical output of the divided signal in addition to the dividing function.
  • the divider circuit 23 is reset by the horizontal synchronous signal to divide the 32f H signal for forming various signals at a desired timing.
  • the divider circuit 23 generates a BGP at a terminal 40, which is indicative of the timing at which the burst signal is generated, and an addition timing pulse at a terminal 41, for controlling the addition timing of the ALC additional pulse.
  • the BGP is applied from terminal 40 to terminal 31 while the addition timing pulse is applied from terminal 41 to terminal 33.
  • the switch 28 of the addition circuit 27 is switched by the addition timing pulse from terminal 41 to add the ALC aadditional pulse of 0.2V of the reference power source 36 to the B-Y signal.
  • Fig. 4(a) shows the B-Y signal from the B-Y demodulator 2. Concerning this signal, a signal having the phase shown in Fig. 4(d) is formed as an addition timing pulse.
  • An ALC additional pulse having a constant voltage is added to the signal of Fig. 4(a) in synchronization with the signal of Fig. 4(d) to form such a signal as shown in Fig. 4(b).
  • the hatched portion in the Fig. 4(b) signal is an ALC additional pulse which is always constant irrespective of the content of the image signal.
  • the B-Y signal, including the ALC additional pulse is then applied to the CCD. If the level of the ALC additional pulse is varied, such variation is returned to its original magnitude. As a result, the B-Y signal will also be returned to its original magnitude.
  • Figs. 5(a)-(c) show a position in which the ALC additional pulse can be generated.
  • Fig. 5(a) shows a video signal (TV signal) while
  • Fig. 5(b) shows the BGP.
  • the ALC additional pulse is generated within a period A shown in Fig. 5(a). Such a period A is from termination of the content of the image signal to initiation of the burst signal in the next 1H.
  • Fig. 5(c) shows the ALC additional pulse within the period A.
  • the signal in Fig. 4(b) is applied to CCDIC 7.
  • the signal will be attenuated as shown in Fig. 4(c) when it is output from CCDIC 7.
  • the attenuated signal is then applied to the first clamp circuit 10, LPF 13 and first ALC circuit 38.
  • the R-Y signal will be similarly attenuated since it is transmitted in the same manner as the B-Y signal.
  • the clamp detector circuit 29 compares the level of the B-Y signal from LPF 13 with the reference voltage V ref of reference power source 30 through a BGP period from the terminal 31 (i.e., a period in which the BGP is at High level) to generate a detection output for regulating the level of the BGP period of the B-Y signal to the level of the reference voltage V ref . Such a detection output is then applied to the first clamp circuit 10.
  • the first clamp circuit 10 thus generates a B-Y signal in which the pedestal level is clamped to the reference voltage V ref .
  • the output of the clamp detector circuit 29 is also applied to the second clamp circuit 11 wherein the pedestal level of the R-Y signal is regulated to the reference voltage V ref similar to the B-Y signal.
  • the output signal of the first ALC circuit 38 is applied to the sensor circuit 32.
  • the sensor circuit 32 closes the switch 34 depending on the addition timing pulse from terminal 33 to take the ALC additional pulse added by addition circuit 27.
  • the ALC additional pulse was 0.2V when it was added. At this point, however, the level of the ALC additional pulse will have been lowered due to the influence of CCDIC 7 or LPF 12 and 13.
  • the sensor circuit 32 then senses the amount which the ALC additional pulse has lowered from a reference voltage, which is provided by adding the reference voltage V ref of the reference power source 30 to the voltage 0.2V of reference power source 36a of addition circuit 27.
  • the resulting detection signal is supplied to the first and second ALC circuits 38, 39 in which the image signal is returned to its original level.
  • the comparator 35 applies its detection output to the hold capacitor 37, the output voltage of which is in turn used to regulate and increase the output levels of the first and second ALC circuits 38, 39.
  • the output ends of the first and second ALC circuits 38, 39 will have B-Y and R-Y signals which have had their levels adjusted to be equal to that before input to the CCDIC 7.
  • the first and second ALC circuits 38, 39 are formed by amplifiers which are controlled in gain by the output voltage of capacitor 37.
  • the signals which have their level equalized with before the 1H delay can be applied to the first and second adders 14, 15 which can in turn reduce the phase distortion due to the transmission system and avoid variations in color phase.
  • the demodulated R-Y and B-Y signals from the first and second adders 14, 15 are matrixed by the matrix circuit 16.
  • the R-Y, B-Y and G-Y signals are thus output from the matrix circuit 16 through the output terminals 17 to 19.
  • the circuit of Fig. 3 can demodulate a PAL type color signal.
  • Fig. 6 is a detailed circuit diagram of the sensor 32 and comparator 35 shown in Fig. 3.
  • the B-Y signal is applied to a terminal 50 while the reference voltage V ref of the reference power source 30 is applied to a terminal 51.
  • the value obtained by multiplying the current of a constant-current source 52 by a resistance 53 has been set to be 0.2V.
  • the comparison between transistors 54 and 55 becomes the comparison between (B-Y signal voltage - 1V BE ) and ( V ref - 1V BE + 0.2V) ) which is carried out by the comparator 35.
  • a switch 56 is thus opened or closed depending on the addition timing pulse.
  • the comparison is performed to output the comparison output through an output terminal 57 only when the addition timing pulse is being received by the comparator 35.
  • switches 111 and 112 are closed while switches 109 and 110 are opened.
  • switches 111 and 112 are opened while switches 109 and 110 are closed.
  • These switches can be opened or closed, for example, in interlock with a manual change-over switch.
  • An SCP produced at terminal 100 is applied to the SCP discriminating circuit 103.
  • Various waveforms in the SCP discriminating circuit 103 are shown in Fig. 7.
  • the SCP has the waveform shown in Fig. 7(c), which waveform is formed by superimposing BGP2 on FBP.
  • the waveform of FBP is saturated with a voltage of 4V in every horizontal blanking period.
  • the waveform of BGP 2 is saturated with a voltage of 6V.
  • the SCP (Fig. 7) contains a vertical synchronous signal of 2V, it will not directly influence the operation of the Fig. 3 circuit.
  • Fig. 8 shows the details of the SCP discriminating circuit 103.
  • the SCP of Fig. 7(c) is applied to an input terminal 113.
  • the reference voltages of first and second comparators 114, 115 are set to be 3V and 5V, respectively.
  • an "H" level pulse is generated on the output end of the first comparator 114 at a time t1 and on the output end of the comparator 115 at another time t2.
  • the edges of these pulses are detected by edge detecting circuits 116 and 117. Therefore, such an addition timing pulse as shown in Fig. 7(d) is provided on the Q output of R-SFF (R-S flip-flop) 118.
  • Such a BGB2 as shown in Fig. 7(b) is provided on the output terminal 119 of the second comparator 115.
  • BGP2 is used in addition to BGP.
  • BGP2 is a signal having its leading edge earlier than that of BGP. Therefore, the timing of Fig. 7(a) is different from that of Fig. 7(b).
  • BGP2 of Fig. 7(b) is also used, for example, to form transfer clocks for the first and second CCD's 8, 9 in the CCDIC 7.
  • the BGP2 is also generated in the divider circuit 23.
  • the ID circuit 105 detects the frequency of the burst signal in accordance with the BGP 2 signal and identifies whether the currect input chrominance signal is a B-Y or an R-Y signal.
  • the ID circuit 105 controls switching of the separation circuit 107 to output B-Y signals to switch 108 and R-Y signals to switch 109.
  • the separation circuit 107 operates to provide a signal as shown in Fig. 9(c) (R-Y signal) to switch 109 and a signal as shown in Fig. 9(b) (B-Y signal) to switch 110 via switch 108.
  • the ALC additional pulse is added to the B-Y signal at the timing shown in Fig. 7(d) through the ALC additional pulse generating circuit 106 and switch 108.
  • the B-Y signal is increased by the ALC additional pulse only during the period in which the addition timing pulse is being generated.
  • the details for such an addition are similar to the PAL system. It is performed by switch 108 selecting the reference power source 36b of 0.2V only during the period in which the addition timing pulse is being generated.
  • Signals from switches 109 and 110 are applied to the CCDIC 7 wherein they are delayed by 1H. These signals are also applied to IC 6 and its first and second adders 14, 15 through terminals 120 and 121.
  • the B-Y signal also passes through the first clamp circuit 10, LPF 13 and first ALC circuit 38 and is returned to its signal level before it was applied to the CCDIC 7 according to the signal level of the ALC additional pulse as in the PAL system. Therefore, the two signal levels applied to the first adder 14, being different from each other by 1H, are equalized.
  • the equalized B-Y signals are alternately applied to the first adder 14 every 1H. The output thereof provides a continuous B-Y signal as shown in Fig. 9(d).
  • the second adder 15 similarly operates since the output of the comparator 35 is applied to the second ALC circuit 39.
  • the output of the second adder 15 provides a continuous R-Y signal as shown in Fig. 9(e).
  • the circuit of Fig. 3 can connect SECAM type discontinuous chrominance signals into a continuous signal which is in turn transformed into color signals having their level equalized. Therefore, the CCDIC 7 can be used to compensate for PAL distortion and also to interpolate the SECAM signals. This provides an accurate distortion compensation and an interpolation of signals equalized in level.
  • the synchronous separation circuit 21, horizontal AFC 22 and divider circuit 23 are also used for PAL and SECAM signals.
  • the output level is one-half that of the PAL system. If it is assumed that the input PAL signal has its level equal to 1V, that of the SECAM system should be set to 2V. Thus, the other color signal processing circuits subsequent to the first and second adders 14, 15 can be used for both systems. This can greatly reduce the number of circuit elements.
  • the present invention can form the ALC additional pulse simply since SCP is used as the SECAM type ALC additional pulse. If there is no SCP, the ALC additional pulse must be formed in a manner similar to the PAL system. This would greatly increase the number of circuit components.
  • BGP of Fig. 7(a) is produced by divider circuit 23 and can be used to extract the burst signal in both the PAL and SECAM type systems.
  • BGP 2 of Fig. 7(b), output from IC 6, has an earlier leading edge.
  • the BGP applied to terminal 31 will not be superimposed in timing on the ALC additional pulse. Therefore, the clamp timing in the first and second clamp circuits will not contain any ALC additional pulse.

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Claims (12)

  1. Circuit de traitement de signaux, utilisable pour assurer la régulation des niveaux de signaux retardés dans un circuit démodulateur de signaux d'image en couleur, comprenant des moyens démodulateurs, servant à démoduler des premier et second signaux de chrominance d'entrée de façon à fournir des premier et second signaux démodulés, des moyens de retard, servant à retarder les premier et second signaux démodulés d'une période de balayage ligne de façon à fournir des premier et second signaux retardés, et des moyens additionneurs, servant à ajouter les premier et second signaux retardés provenant des premier et second moyens de retard aux premier et second signaux démodulés provenant des moyens démodulateurs, les signaux retardés d'une période de balayage ligne étant utilisés pour reproduire les premier et second signaux de chrominance, le circuit de traitement de signaux comprenant :
    des moyens d'addition servant à ajouter une impulsion additionnelle ayant un niveau de signal donné à au moins l'un des premier et second signaux démodulés provenant des moyens démodulateurs, ledit signal démodulé auquel l'impulsion additionnelle est ajoutée étant alors envoyé aux moyens de retard ;
    des moyens de régulation de niveau servant à assurer la régulation des niveaux des premier et second signaux retardés provenant des moyens de retard, de façon à rendre le niveau de signal de l'impulsion additionnelle contenue dans au moins l'un des premier et second signaux retardés provenant des moyens de retard égal au niveau de signal de l'impulsion additionnelle lorsqu'elle est ajoutée à au moins l'un des premier et second signaux démodulés par les moyens d'addition ;
    les moyens additionneurs servant à ajouter les premier et second signaux retardés, dont la régulation des niveaux est assurée par les moyens de régulation de niveau, respectivement aux premier et second signaux démodulés provenant des moyens démodulateurs.
  2. Circuit de traitement de signaux tel que défini à la revendication 1, dans lequel les moyens de retard utilisent un dispositif à couplage de charge (CCD), les signaux retardés par ledit CCD étant envoyés aux moyens de régulation de niveau.
  3. Circuit de traitement de signaux tel que défini à la revendication 2, dans lequel le circuit de traitement de signaux est disposé dans un circuit intégré à semi-conducteur unique comprenant les moyens démodulateurs et moyens additionneurs, les moyens de retard étant réalisés sous forme d'un composant extérieur au circuit intégré à semi-conducteur.
  4. Circuit de traitement de signaux tel que défini dans l'une quelconque des revendications 1 à 3, dans lequel les moyens d'addition ajoutent l'impulsion additionnelle uniquement à l'un des premier et second signaux de chrominance et dans lequel les moyens de régulation de niveau assurent la régulation du niveau de signal des signaux retardés de sortie provenant des moyens de retard, en fonction du niveau de signal de l'impulsion additionnelle dans l'un des signaux retardés.
  5. Circuit de traitement de signaux tel que défini à la revendication 4, dans lequel les moyens de régulation de niveau comprennent :
    des moyens de blocage servant à bloquer un niveau de suppression qui est le niveau de signal de chacun des premier et second signaux retardés dans une partie donnée de signal n'appartenant pas à l'image sur un niveau de blocage donné ;
    des moyens comparateurs servant à comparer le niveau de l'impulsion additionnelle contenue dans l'un des signaux de sortie provenant des moyens de blocage au niveau d'un signal obtenu en ajoutant les niveaux de blocage au niveau de l'impulsion additionnelle ajoutée par les moyens d'addition ; et
    des moyens amplificateurs servant à amplifier le taux d'amplification dans les sorties des moyens de blocage en fonction de la sortie de comparaison des moyens comparateurs.
  6. Circuit de traitement de signaux tel que défini dans l'une quelconque des revendications 1 à 5, dans lequel les signaux d'entrée sont des signaux de télévision de type PAL et dans lequel les moyens démodulateurs démodulent en parallèle les premier et second signaux de chrominance et les moyens additionneurs ajoutent l'un à l'autre les premiers signaux de chrominance dans deux périodes de balayage ligne adjacentes et ajoutent aussi l'un à l'autre les seconds signaux de chrominance dans deux périodes de balayage ligne adjacentes.
  7. Circuit de traitement de signaux tel que défini à la revendication 6, dans lequel les moyens d'addition ajoutent l'impulsion additionnelle pendant une période s'étendant de la fin d'un signal d'image dans une première période de balayage ligne pour des signaux de télévision au début d'une salve de signaux de couleur dans la période suivante de balayage ligne.
  8. Circuit de traitement de signaux tel que défini à la revendication 7, dans lequel les moyens d'addition réagissant à une impulsion de déclenchement de salve de signaux couleur indiquant une période pendant laquelle la salve de signaux couleur est produite pour produire une impulsion de synchronisation antérieure, avancée d'une période donnée, ajoutant ainsi l'impulsion additionnelle sur la base de l'impulsion de synchronisation.
  9. Circuit de traitement de signaux tel que défini à l'une quelconque des revendications 1 à 5, dans lequel les signaux d'entrée sont des signaux de télévision du type SECAM et dans lequel les moyens démodulateurs comprennent une unité démodulatrice SECAM, servant à démoduler d'une manière alternée des premier et second signaux de chrominance contenus d'une manière alternée dans les signaux de télévision pour chaque période de balayage ligne, fournissant ainsi un signal contenant les premier et second signaux de chrominance pour chaque période de ligne, et une unité de séparation servant à commuter les sorties de l'unité démodulatrice SECAM sur leur chemin respectif pour chaque période de ligne, produisant ainsi des premier et second signaux démodulés ne contenant chacun que le premier ou le second signal de chrominance.
  10. Circuit de traitement de signaux tel que défini à la revendication 9, dans lequel les moyens d'addition ajoutent l'impulsion additionnelle sur la base d'une impulsion de synchronisation qui réagit à une impulsion de château de sable formée en superposant une seconde salve de signaux de couleur et une impulsion de retour de balayage horizontal, dans lequel la seconde salve de signaux de couleur présente une synchronisation de début de signal qui est avancée d'une période donnée par rapport à une première salve de signaux de couleur qui indique la période pendant laquelle la salve de signaux de couleur dans les signaux de télévision, et une synchronisation de fin de signal qui est la même que celle de la première salve de signaux de couleur.
  11. Circuit de traitement de signaux tel que défini à la revendication 10, dans lequel les moyens d'addition servent à comparer l'impulsion de château de sable à une première tension de référence pour faire débuter la production de ladite impulsion de synchronisation et à comparer l'impulsion de château de sable à une seconde tension de référence pour faire finir la production de ladite impulsion de synchronisation, produisant ainsi une impulsion de synchronisation qui finit au début de la seconde salve de signaux de couleur.
  12. Circuit de traitement de signaux tel que défini à l'une quelconque des revendications 1 à 5, dans lequel le signal d'entrée est un signal de télévision du type PAL ou SECAM et dans lequel les moyens démodulateurs comprennent des moyens démodulateurs PAL, servant à démoduler des premier et second signaux de chrominance contenus dans le signal d'entrée de type PAL afin de fournir des premier et second signaux démodulés PAL, et des moyens démodulateurs SECAM servant à démoduler d'une manière alternée des premier et second signaux de chrominance contenus d'une manière alternée dans le signal d'entrée de type SECAM, les premier et second signaux de chrominance démodulés étant, d'une manière séquentielle et séparée, commutés et délivrés en sortie pour produire des premier et second signaux démodulés SECAM, ne contenant chacun que le premier ou le second signal de chrominance, les moyens d'addition comprenant séparément des moyens d'addition PAL et des moyens d'addition SECAM, les moyens d'addition PAL servant à produire une impulsion additionnelle sur la base d'une première impulsion de déclenchement de salve de signaux de couleur indiquant la période pendant laquelle la salve de signaux de couleur est produite, les moyens d'addition SECAM servant à produire une impulsion additionnelle sur la base d'une impulsion de château de sable formée en superposant une seconde impulsion de déclenchement de salve de signaux de couleur sur une impulsion de retour de balayage horizontal, les moyens de retard et de régulation de niveau servant à traiter les premier et second signaux démodulés PAL ou SECAM.
EP96104608A 1995-03-29 1996-03-22 Démodulateur de signal couleur applicable pour télévision PAL et SECAM Expired - Lifetime EP0735779B1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP7198495 1995-03-29
JP07198495A JP3244398B2 (ja) 1995-03-29 1995-03-29 Ｐａｌ方式の色信号復調回路
JP71985/95 1995-03-29
JP07198595A JP3253482B2 (ja) 1995-03-29 1995-03-29 色信号復調回路
JP7198595 1995-03-29
JP71984/95 1995-03-29

Publications (2)

Publication Number Publication Date
EP0735779A1 EP0735779A1 (fr) 1996-10-02
EP0735779B1 true EP0735779B1 (fr) 1999-09-08

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EP96104608A Expired - Lifetime EP0735779B1 (fr) 1995-03-29 1996-03-22 Démodulateur de signal couleur applicable pour télévision PAL et SECAM

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EP (1) EP0735779B1 (fr)
KR (1) KR100406451B1 (fr)
CN (1) CN1100445C (fr)
DE (1) DE69604107T2 (fr)
ES (1) ES2136336T3 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1953330B (zh) * 2005-09-30 2010-09-08 三洋电机株式会社 延迟电路和使用它的视频信号处理电路

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007097020A (ja) * 2005-09-30 2007-04-12 Sanyo Electric Co Ltd 遅延回路及びそれを用いた映像信号処理回路
CN106855583B (zh) * 2015-12-09 2020-02-21 比亚迪股份有限公司 用于图像传感器的方法和装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0364225B1 (fr) * 1988-10-12 1996-03-27 Canon Kabushiki Kaisha Appareil pour le traitement d'un signal de couleur
US5272522A (en) * 1990-04-30 1993-12-21 Thomson Consumer Electronics, Inc. Video signal processing circuits
KR940001436B1 (ko) * 1991-08-20 1994-02-23 삼성전자 주식회사 색상조절회로

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1953330B (zh) * 2005-09-30 2010-09-08 三洋电机株式会社 延迟电路和使用它的视频信号处理电路

Also Published As

Publication number Publication date
EP0735779A1 (fr) 1996-10-02
DE69604107D1 (de) 1999-10-14
CN1100445C (zh) 2003-01-29
KR100406451B1 (ko) 2004-03-18
ES2136336T3 (es) 1999-11-16
CN1139863A (zh) 1997-01-08
KR960036811A (ko) 1996-10-28
DE69604107T2 (de) 2000-04-13

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