EP0729128A2 - Dispositif d'adressage d'une électrode d'écran plat de visualisation à micropointes - Google Patents

Dispositif d'adressage d'une électrode d'écran plat de visualisation à micropointes Download PDF

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Publication number
EP0729128A2
EP0729128A2 EP96410011A EP96410011A EP0729128A2 EP 0729128 A2 EP0729128 A2 EP 0729128A2 EP 96410011 A EP96410011 A EP 96410011A EP 96410011 A EP96410011 A EP 96410011A EP 0729128 A2 EP0729128 A2 EP 0729128A2
Authority
EP
European Patent Office
Prior art keywords
column
voltage
potential
control device
cathode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96410011A
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German (de)
English (en)
French (fr)
Other versions
EP0729128A3 (enrdf_load_stackoverflow
Inventor
Bernard Bancal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pixtech SA
Original Assignee
Commissariat a lEnergie Atomique CEA
Pixtech SA
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Publication date
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Publication of EP0729128A2 publication Critical patent/EP0729128A2/fr
Publication of EP0729128A3 publication Critical patent/EP0729128A3/xx
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • the present invention relates to a flat display screen. It applies more particularly to the control, or addressing, of an electrode of a microtip screen.
  • Figure 1 shows the functional structure of a conventional microtip flat screen.
  • Such a microtip screen essentially consists of a cathode 1 with microtips 2 and a grid 3 provided with holes 4 corresponding to the locations of the microtips.
  • the cathode 1 is placed opposite a cathode-luminescent anode 5 including one glass substrate 6 constitutes the surface of the screen.
  • the cathode 1 is organized in columns and consists, on a substrate 10 for example of glass, of cathode conductors organized in meshes from a conductive layer.
  • the microtips 2 are produced on a resistive layer 11 deposited on the cathode conductors and are arranged inside the meshes defined by the cathode conductors.
  • FIG. 1 partially represents the interior of a mesh, the cathode conductors do not appear in this figure.
  • the cathode 1 is associated with the grid 3 which is it organized in rows, an insulating layer (not shown) being interposed between the cathode conductors and the grid 3. The intersection of a row of the grid 3 and a column of cathode 1 defines a pixel.
  • This device uses the electric field created between the cathode 1 and the grid 3 so that electrons are extracted from the microtips 2 towards phosphor elements 7 of the anode 5.
  • the anode 5 is provided with alternating bands d 'phosphor elements 7, each corresponding to a color (Blue, Red, Green).
  • the strips are separated from each other by an insulator 8.
  • the phosphor elements 7 are deposited on electrodes 9, consisting of corresponding strips of a transparent conductive layer such as indium tin oxide (ITO) .
  • ITO indium tin oxide
  • the width of a group of bands of the anode 5 corresponds to the width of a pixel.
  • the sets of blue, red and green bands are alternately polarized with respect to the cathode 1, so that the electrons extracted from the microtips 2 of a pixel of the cathode / grid are alternately directed towards the phosphor elements 7 opposite each other colors crossing an empty space 12.
  • FIG. 2 illustrates schematically and in perspective, an example of conventional addressing of a microtip screen.
  • the mesh of the columns K of the cathode has not been shown.
  • the cathode 1 has been shown separated from the grid 3 while in practice the vertices of the microtips 2 arrive at the holes 4 made in the grid 3.
  • only nine microtips 2 per pixel have been represented. In practice, microtips are several thousand per pixel of screen and the grid 3 has a hole 4 plumb with each microtip 2.
  • the display of an image takes place during an image time (for example 20 ms for a frequency of 50 Hz) by suitably polarizing the anode 5, the cathode 1 and the grid 3 by means of an control electronics (not shown).
  • the bands R, G, and B of phosphor elements of the anode are sequentially polarized by a set of bands of the same color during a frame time (for example 6.6 ms) corresponding to one third of the reduced image time times required for switching.
  • the display is carried out line by line, sequentially polarizing the rows L of the grid 3 during a "line time" during which each column K of the cathode is brought to a potential which is a function of the brightness of the pixel to be displayed along the current row (for example L j ) in the color considered.
  • the polarization of the columns K of the cathode 1 changes with each new row of the line scanning.
  • a "line time" (for example 10 ms) corresponds to the duration of a frame divided by the number of rows L of the grid 3.
  • FIG. 2 illustrates the path of the electrons emitted by the microtips of the columns K i-1 , K i and K i + 1 brought to potentials which are a function of the desired brightness in the green color, respectively for the pixels P (i- 1, j) , P (i, j) and P (i + 1, j) , during a "line time" during which the row L j is polarized.
  • the areas of the pixels P are shown in phantom.
  • FIG. 3 represents the equivalent simplified electrical diagram of a microtip screen as shown in FIG. 2.
  • the resistive layer 11 is symbolized by a resistance R K of access to each microtip 2.
  • Each column K of cathode and each row The grid is individually connected to the control electronics (not shown).
  • each set of bands of phosphor elements 7 of the same color is connected to a terminal of polarization, respectively A R , A G or A B of the control electronics. From the electrical point of view, each band R, G, or B behaves like a capacitive load with an access resistance R A.
  • the sets of bands of phosphor elements 7 are therefore sequentially brought to a potential making it possible to attract the electrons emitted by the microtips 2.
  • This potential is chosen by the user taking into account, in particular, the distance between the cathode / grid of the anode and is for example of the order of 300 to 400 volts.
  • the rows L of the grid 3 are sequentially polarized during a frame. A given row (for example L j ) is brought to a potential (for example 80 volts) while the other rows are at a zero potential during the "line time" of the current row.
  • a disadvantage of conventional screens is that the technological dispersions resulting from the production of the microdots result in that all the microdots of the screen do not have the same emissivity. In other words, for an identical potential V K representing a given luminance setpoint, there are disparities in the brightness of the pixels.
  • Another drawback lies in the fact that the electrons emitted by microtips of a given column K of the cathode tend to excite the bands of phosphor elements of the same color which are opposite the two neighboring columns K. Indeed, although two bands of the same color are separated by two bands of another color, the distance (of the order of 0.2 mm) between the phosphor elements 7 and the microtips 2 leads to the fact that the electrons have tendency to deviate to the nearest bands of the same color.
  • FIG. 3 This phenomenon of illumination of the neighboring pixels is illustrated in FIG. 3. It is assumed that there is a red frame time where all the bands R i of the anode are addressed. The electrons emitted by certain microtips of a column K i of the cathode tend to be attracted by the columns R i , R i + 1 of the anode. This parasitic bombardment is shown in dotted lines in FIG. 3.
  • Such a phenomenon is increased in the event of misalignment of the groups of bands of phosphor elements with respect to the columns K of the cathode, which can occur during assembly of the screen.
  • the invention aims to overcome these drawbacks by proposing a device for controlling a flat display screen electrode which ensures uniform brightness of the screen pixels for a given luminance setpoint.
  • the invention proposes to carry out the control, or addressing, of an electrode of the screen based on a measurement of the charges of the columns of this electrode.
  • the present invention provides a device for controlling a flat screen display electrode of the type comprising a first electrode constituting a microtip cathode, a second electrode constituting an anode provided with phosphor elements and an organized grid. in rows, at least one of said electrodes being organized in columns and the device comprising means for individually addressing each column and for cutting the polarization of a column as soon as its charge reaches a threshold determined according to a luminance setpoint.
  • said means consist, for each column, of a control cell comprising a block for switching the polarization of the column between a positive supply potential and a negative supply potential , and a load detection block for this column.
  • said anode consists of at least two sets of alternating strips of phosphor elements organized in columns, and said cathode consists of a plane of microtips covering the entire surface of the screen .
  • each switching block comprises two switches connected in series between the negative supply potential and, via a sensor of the detection block with which it is associated, the positive potential d power supply, and a comparator receiving on two inputs, respectively a luminance setpoint voltage and a voltage delivered by said detection block and indicator of the quantity of charges received by said column, said switches constituting a polarization stage of the controlled column by said comparator, the output of which controls a first switch via an inverter while it directly controls a second switch.
  • each detection block includes a first operational amplifier, a non-inverting input of which receives the voltage across a detection resistor constituting said sensor, an inverting input of which receives the voltage across its terminals. a load resistor and the output of which is sent to the gate of a first N-channel MOS transistor placed between said load resistor and a storage capacitor, the voltage across said capacitor constituting said voltage indicative of the quantity of charges received by the column.
  • each control cell further comprises means for discharging said capacitor before each addressing of a new row of said grid.
  • said first switch consists of a first N-channel power MOS transistor whose source is connected to said negative supply potential and whose drain is connected to a connection terminal of said column as well as the drain of a second P-channel power MOS transistor, constituting said second switch and the source of which is connected to said positive supply potential via said sensor.
  • said comparator consists of a second operational amplifier, an inverting input of which receives said voltage indicative of the quantity of charges received, a non-inverting input of which receives said setpoint voltage and whose output is sent to the gates of said power transistors of the bias stage.
  • the output of said comparator is connected to the gate of said first transistor of the bias stage via a delay element and a voltage shifter while it is directly connected to the gate of said second transistor of the bias stage, said positive supply potential being constituted by ground.
  • said setpoint voltage is supplied by a digital-analog converter receiving, as input, a luminance setpoint in digital form.
  • the device according to the invention is based on an individual measurement of the charges in each column of the electrode with which the device is associated.
  • the device is associated with the bands, or columns, of the anode.
  • the quantity of charges received by each column of phosphor elements bombarded by the microtips of the cathode is then measured at each "line time". As soon as this quantity corresponds to the quantity required to obtain the desired brightness of the pixel in the color considered, the polarization of the column is cut.
  • FIG. 4 illustrates such an embodiment.
  • each strip of phosphor elements 7 of the anode is controlled individually.
  • the columns R, G, B of the anode are individually addressed by electronic control of the screen in which the device according to the invention is integrated.
  • Each column is associated with a control cell comprising a switching block 21 and a counting block 22 (SENSE) of the charges received by the phosphor elements 7 of the column.
  • the purpose of block 21 is to switch the polarization of the column between a positive supply potential + V A and a negative supply potential, here the mass M.
  • the potential difference between the two positive and negative supply potentials represents the addressing voltage of columns R, G, B of phosphor elements 7, for example of the order of 300 to 400 volts.
  • the switching is carried out on the basis of a luminance set point LUM of the pixel in the color of the column and is controlled by the quantity of charges received by the column which is detected by means of block 22.
  • the display is always made, frame by frame, by addressing all the columns (for example red) of the same color simultaneously during a frame time, for example of approximately 6.6 ms for an image frequency of 50 Hz.
  • Grid 3 is always addressed sequentially by row L by means of a line scan.
  • the cathode no longer needs to be addressed by column insofar as the control of the anode fulfills this role.
  • the luminance setpoints LUM (R i-1 ), LUM (R i ), LUM (R i + 1 ), etc.
  • the invention thus makes it possible, according to this embodiment, to simplify the constitution of the cathode by dispensing with the mesh and the organization in columns of the cathode conductors.
  • the cathode 1 is, according to the invention, made up of a microtip plane 2 covering the entire surface of the screen and polarized at a fixed value V K.
  • the beginning of the addressing of all the columns, respectively R, G or B of the same color occurs at the same instant at each beginning of addressing of a row L of the grid.
  • the end of the addressing of these columns is individualized by means of the device according to the invention. It occurs, in the interval of each "line time", at the instant when the quantity of charges received by a given column corresponds to the desired luminance for the pixel defined by the intersection of this column and the row of the grid in the frame considered.
  • block 21 cuts off the addressing of this column which is therefore no longer bombarded.
  • An advantage of the present invention is that, for the same luminance setpoint, the brightness of the pixels will be regular over the entire surface of the screen. Indeed, it no longer depends on the emission capacity of the microtips of each pixel.
  • FIG. 4 Another advantage of the embodiment shown in FIG. 4 is that it simplifies the positioning of the plates supporting the anode and the cathode / grid respectively during assembly of the screen. Indeed, the columns of the anode no longer need to be aligned with columns of the cathode which here consists of a plane of microtips covering the entire surface of the screen.
  • Another advantage of this embodiment is that in the event of a deficiency of certain microtips of the cathode, even in an area reaching the size of a pixel of the screen, the brightness of the pixel considered will not suffer from it. Indeed, assuming that the column located opposite this pixel has not received its charge account, its excitation is continued by the microtips of the neighboring pixels, as soon as a column of the same color which is close to it is brought back to the mass for having been correctly charged.
  • FIG. 5 represents an embodiment of a control cell constituting the device represented in FIG. 4.
  • the switching block 21 consists of two switches K1 and K2 connected in series between earth and a sensor of the detection block 22. These switches K1 and K2 constitute a stage of polarization of the column, designated here by the reference A, d 'phosphor elements 7 with which the cell is associated.
  • the sensor of the detection block 22 creates a negligible voltage drop so that it can be considered that the switches K1 and K2 are connected in series between the ground and the potential + V A.
  • Column A is electrically connected to a terminal D corresponding to the midpoint of the association of switches K1 and K2.
  • the block 21 also includes a comparator 23 responsible for enabling the switching of the switches K1 and K2.
  • a first input of the comparator 23 receives a voltage V CE indicative of the quantity of charges received by the column A. This voltage is delivered by the block 22 from the current drawn by the column A from the supply.
  • a second input of comparator 23 receives a setpoint voltage Vref corresponding to the luminance setpoint LUM of the pixel in the color of column A.
  • the output of comparator 23 is sent, via an inverter 24, to the command input from first switch K1 while it is sent directly to the control input of the second switch K2.
  • the voltage Vref is supplied by a digital-analog converter (DAC) 25 responsible for delivering the voltage level Vref corresponding to the desired luminance LUM setpoint for the pixel in the color considered.
  • the DAC 25 receives from the control electronics (not shown) digital signals, for example on eight bits D0 to D7 whose values correspond to the desired luminance level LUM. If the control electronics directly provide a luminance level in the form of an analog signal, the use of such a converter is not necessary.
  • a reduced number of digital-analog converter can be used to supply the setpoint voltages Vref to all the columns being associated with elements for storing these voltages (one element per anode column).
  • FIG. 6 is an electrical diagram of a control cell illustrating an embodiment of the switches K1 and K2 and of the detection unit 22.
  • the positive supply voltage is constituted by the mass M and the negative supply voltage is constituted by a potential -V A.
  • the choice of mass as a positive supply potential allows, as will be seen below, to have a reference uniform and stable and simplify the polarization of all components of the cell that are used to measure the amount of charge received by column A.
  • the potential -V A is for example -400 V
  • the potential -V L for biasing the rows L of the grid 3 is for example -320 V
  • the potential -V K of the cathode 1 is for example - 400 V.
  • the detection block 22 includes a detection resistor Rs placed between the ground and the switch K2.
  • the role of the resistor Rs which constitutes the sensor of the detection block is to measure the current Is taken from column A.
  • the voltage across the resistor Rs is sent to the non-inverting input of a first operational amplifier AP 26.
  • the positive bias potential of this amplifier corresponds to the positive supply potential (ground) and its negative bias potential is a potential -Vcc which is a function of the operating range in bias voltage of the amplifier 26, for example of the order of 15 volts.
  • the inverting input of amplifier 26 is connected to a first terminal of a load resistor Rch, a second terminal of which is connected to ground.
  • the first terminal of the resistor Rch is also connected to the drain of a first N-channel MOS transistor MN1.
  • the source of this transistor MN1 is connected to the negative bias potential -Vcc via a storage capacitor C.
  • the gate of transistor MN1 is connected to the output of amplifier 26.
  • the role of amplifier 26 is to copy the voltage Vs, across the resistor Rch.
  • the current Ich in the resistor Rch is proportional to the current in the resistor Rs.
  • the switches K1 and K2 constituting the polarization stage of the column A are made up of power MOS transistors.
  • the polarization stage thus consists of two power MOS transistors, respectively with N channel ML and with P channel MH.
  • the source of a first transistor ML is connected to the negative supply potential -V A and its drain is connected to the terminal D for connection of the column A.
  • Terminal D is also connected to the drain of a second transistor MH whose the source is connected to ground via the detection resistor Rs.
  • the addressing of column A is carried out by an appropriate control of the gates of the transistors MH and ML.
  • the gates of these transistors are controlled by means of the comparator 23 consisting, for example, of a second operational amplifier.
  • the comparator 23 receives on its two inputs, respectively the voltage Vref supplied by the DAC 25 and the voltage V CE across the capacitor C.
  • the inverting input of the operational amplifier 23 is connected to the drain of the transistor MN1, its non-inverting input receives the voltage Vref and its output controls the gates of the transistors MH and ML.
  • Comparator 23 and DAC 25 are, like amplifier 26, polarized between ground and -Vcc.
  • the output of the comparator 23 is connected to the gate of the transistor ML, via a delay element 27 and a voltage shifter 28 , while it is directly connected to the gate of transistor MH.
  • the delay element 27 has the effect of delaying the control of the transistor ML relative to the control of the transistor MH and thus avoids their simultaneous switching.
  • the role of the voltage shifter 28 is to allow the switching of the ML transistor by relating the low-voltage output level of the comparator 23 to a level allowing the switching of the ML transistor, that is to say a potential, respectively lower than the potential -V A increased by the threshold voltage Vgs of this transistor or greater than the potential -V A increased by the voltage Vgs.
  • the capacitor C is discharged by means of a second N-channel MOS transistor MN2.
  • the source of this transistor MN2 is connected to the potential -Vcc, its drain is connected to the drain of the transistor MN1 and its gate is controlled by a RESET signal supplied by the control electronics.
  • the duration of a "line time” corresponds, as before, to the frame time divided by the number of rows L of the grid 3. For example, for a screen of 288 rows, the “line time” is approximately 25 ms.
  • the discharge of the parasitic capacitances which exist between this column and its two neighboring columns must be very rapid compared to the "line time".
  • Such a condition which depends on the drain-source resistance in the on state Rds ON of the transistor ML, is perfectly respected. Indeed, the resistance Rds ON of a power MOS transistor is generally of the order of 1 k ⁇ . However, the value of the stray capacitances is generally around 10 pF which leads to a discharge time of the order of 10 ns.
  • the positive supply potential of the columns and the positive bias potential of the operational amplifiers and of the DAC is a potential + V A.
  • the negative bias potential of the operational amplifiers and the DAC must then correspond to V A - Vcc so that the bias voltage of these components is Vcc.
  • the implementation of such a variant requires that the low-voltage components used do not require a connection to the ground of the circuit. Otherwise, these components are biased between + Vcc and ground, but an additional voltage shifter must then be provided to allow the device to operate.
  • the shifter 28 is here associated with the gate of the transistor MH and the additional shifter is, as has been seen above, associated with the non-inverting input of the amplifier 26.
  • the potentials + V A and + Vcc must be stable according to the operating conditions of the screen, or at least evolve in the same proportions so as not to distort the load detection.
  • the device according to the invention as set out in relation to FIGS. 4 to 6 can be transposed to the individual control of the columns of a cathode with microtips by carrying out the measurement of the charges emitted by the microtips of each column.
  • the quantity of charges (of electrons) emitted by each line scan is measured. each column of microtips.
  • the polarization, therefore the emission of this column is cut. If such an embodiment makes the screen brightness independent of the technological dispersions resulting from the production of the microtips, it does not make it possible to overcome the deficiency of a large area of microtips and it requires maintaining an organization in columns of the cathode.
  • the parasitic capacitances which exist between the grid and the microtips are of the order of 5 pF which leads, for the entire screen, to a greater energy dissipation during the discharge of these parasitic capacitors.
  • the invention also applies to the control of a monochrome screen.
  • the anode of such a screen is organized into two sets of alternating columns of the same color, it is preferable to carry out the addressing by an individual control of the columns of the anode. If, on the other hand, the anode consists of a plane of phosphor elements covering the entire surface of the screen, addressing will be carried out by individual control of the columns of the cathode associated with a measurement of the charges emitted by these columns .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Transforming Electric Information Into Light Information (AREA)
EP96410011A 1995-02-17 1996-02-08 Dispositif d'adressage d'une électrode d'écran plat de visualisation à micropointes Withdrawn EP0729128A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9502066A FR2730843B1 (fr) 1995-02-17 1995-02-17 Dispositif d'adressage d'une electrode d'ecran plat de visualisation a micropointes
FR9502066 1995-02-17

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Publication Number Publication Date
EP0729128A2 true EP0729128A2 (fr) 1996-08-28
EP0729128A3 EP0729128A3 (enrdf_load_stackoverflow) 1996-09-11

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US (1) US6020864A (enrdf_load_stackoverflow)
EP (1) EP0729128A2 (enrdf_load_stackoverflow)
JP (1) JPH08265674A (enrdf_load_stackoverflow)
FR (1) FR2730843B1 (enrdf_load_stackoverflow)

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US7663618B2 (en) 1998-09-03 2010-02-16 University Of Southern California Power-efficient, pulsed driving of capacitive loads to controllable voltage levels

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FR2832537B1 (fr) 2001-11-16 2003-12-19 Commissariat Energie Atomique Procede et dispositif de commande en tension d'une source d'electrons a structure matricielle, avec regulation de la charge emise
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JP4504655B2 (ja) * 2003-10-15 2010-07-14 日本放送協会 電子放射装置、駆動装置およびディスプレイ
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998031000A1 (en) * 1997-01-07 1998-07-16 Micron Display Technology, Inc. Matrix addressable display having pulsed current control
US5945968A (en) * 1997-01-07 1999-08-31 Micron Technology, Inc. Matrix addressable display having pulsed current control
WO2000014708A3 (en) * 1998-09-03 2001-01-11 Univ Southern California Power-efficient, pulsed driving of liquid crystal display capacitive loads to controllable voltage levels
US7663618B2 (en) 1998-09-03 2010-02-16 University Of Southern California Power-efficient, pulsed driving of capacitive loads to controllable voltage levels

Also Published As

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US6020864A (en) 2000-02-01
JPH08265674A (ja) 1996-10-11
FR2730843A1 (fr) 1996-08-23
FR2730843B1 (fr) 1997-05-09
EP0729128A3 (enrdf_load_stackoverflow) 1996-09-11

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