EP0713236A1 - Dispositif émitteur d'électrons - Google Patents

Dispositif émitteur d'électrons Download PDF

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Publication number
EP0713236A1
EP0713236A1 EP95117883A EP95117883A EP0713236A1 EP 0713236 A1 EP0713236 A1 EP 0713236A1 EP 95117883 A EP95117883 A EP 95117883A EP 95117883 A EP95117883 A EP 95117883A EP 0713236 A1 EP0713236 A1 EP 0713236A1
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EP
European Patent Office
Prior art keywords
conductive
accordance
layer
electron emission
emission apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95117883A
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German (de)
English (en)
Inventor
Robert H. Taylor
Jules D. Levine
Kenneth G. Vickers
Bruce E. Gnade
Arthur M. Wilson
Charles E. Primm
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Texas Instruments Inc
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Texas Instruments Inc
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Publication date
Priority claimed from US08/341,829 external-priority patent/US5541466A/en
Priority claimed from US08/341,740 external-priority patent/US5557159A/en
Priority claimed from US08/378,331 external-priority patent/US5536993A/en
Priority claimed from US08/378,328 external-priority patent/US5569975A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of EP0713236A1 publication Critical patent/EP0713236A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H01J1/304—Field-emissive cathodes
    • H01J1/3042—Field-emissive cathodes microengineered, e.g. Spindt-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/319—Circuit elements associated with the emitters by direct integration

Definitions

  • the present invention relates generally to flat panel displays and, more particularly, to an arrangement of electron-emissive microtip structures, wherein a cluster of microtips are formed on or closely spaced from a conductive plate which is laterally spaced apart from a conductive mesh structure by a resistive medium.
  • liquid crystal displays are used almost universally for laptop and notebook computers. In comparison to a CRT, these displays provide poor contrast, only a limited range of viewing angles is possible, and, in color versions, they consume power at rates which are incompatible with extended battery operation. In addition, color screens tend to be far more costly than CRT's of equal screen size.
  • Patent No. 5,194,780 "Electron Source with Microtip Emissive Cathodes,” issued 16 March 1993 to Robert Meyer; and U.S. Patent No. 5,225,820, “Microtip Trichromatic Fluorescent Screen,” issued 6 July 1993, to Jean-Frédéric Clerc.
  • the present invention relates to the use of a resistive layer to provide a ballast against excessive current drawn by the electron emitters.
  • a vertical resistor approach is disclosed in the Borel et al. ('916) patent and discussed in relation to FIG. 1 herein;
  • a lateral resistor approach is disclosed in the Meyer ('780) patent and discussed in relation to FIGS. 2A and 2B herein.
  • the field emission device comprises an anode plate having an cathodoluminescent phosphor coating facing an emitter plate, the phosphor coating being observed from the side opposite to its excitation.
  • the illustrative prior art vertical resistor field emission device of FIG. 1 comprises a cathodoluminescent anode plate 10 and an electron emitter (or cathode) plate 12.
  • the cathode portion of emitter plate 12 includes conductive layer 15 formed on an insulating substrate 18, a resistive layer 16 formed over conductive layer 15, and a multiplicity of electrically conductive microtips 14 formed on resistive layer 16.
  • a gate electrode comprises a layer of an electrically conductive material 22 which is deposited on an insulating layer 20 which overlays resistive layer 16.
  • Microtip emitters 14 are in the shape of cones which are formed within apertures 34 through conductive layer 22 and insulating layer 20.
  • the thicknesses of gate electrode layer 22 and insulating layer 20 are chosen in such a way that the apex of each microtip 14 is substantially level with the electrically conductive gate electrode layer 22.
  • Conductive layer 22 is arranged as rows of conductive bands across the surface of emitter plate 12, and conductive layer 15 is arranged as columns of conductive bands across the surface of emitter plate 12, the rows of conductive layer 22 being orthogonal to the columns of conductive layer 15, thereby permitting matrix-addressed selection of microtips 14 at the intersection of a row and column corresponding to a pixel.
  • Anode plate 10 comprises an electrically conductive film 28 deposited on a transparent planar support 26, which is positioned facing gate electrode 22 and parallel thereto, the conductive film 28 being deposited on the surface of support 26 directly facing gate electrode 22.
  • Conductive film 28 may be in the form of a continuous coating across the surface of support 26; alternatively, it may be in the form of electrically isolated stripes comprising three series of parallel conductive bands across the surface of support 26, as taught in U.S. Patent No. 5,225,820, to Clerc.
  • Anode plate 10 also comprises a cathodoluminescent phosphor coating 24, deposited over conductive film 28 so as to be directly facing and immediately adjacent gate electrode 22. In the Clerc patent, the conductive bands of each series are covered with a phosphor coating which luminesces in one of the three primary colors, red, blue and green.
  • One or more microtip emitters 14 of the above-described structure are energized by applying a negative potential to conductive layer 15, functioning as the cathode electrode, relative to the gate electrode 22, via voltage supply 30, thereby inducing an electric field which draws electrons from the apexes of microtips 14.
  • the freed electrons are accelerated toward the anode plate 10 which is positively biased by the application of a substantially larger positive voltage from voltage supply 32 coupled between the gate electrode 22 and conductive film 28, functioning as the anode electrode.
  • Energy from the electrons attracted to the anode conductor 28 is transferred to the phosphor coating 24, resulting in luminescence.
  • the electron charge is transferred from phosphor coating 24 to conductive film 28, completing the electrical circuit to voltage supply 32.
  • the purpose of the resistive layer is to provide a ballast against excessive current in each microtip emitter and consequently homogenize the electron emission.
  • the resistive layer makes it possible to eliminate excessively bright spots.
  • the resistive layer also makes it possible to reduce breakdown risk at the microtips by limiting the current and thus prevent the appearance of short circuits between rows and columns.
  • the resistive layer allows the short-circuiting of a few microtip emitters with a gate conductor; the very limited leakage current (a few ⁇ amperes) in the short circuits will not affect the operation of the remainder of the cathode conductor.
  • Borel et al. ('916) recommend a material for use as the resistive layer having a resistivity of between approximately 102 and 106 ohms ⁇ cm. More particularly, they recommend forming the resistive layer from a material chosen from the group including In2O3, SnO2, Fe2O3, ZnO and silicon in doped form.
  • FIGS. 2A and 2B An improved prior art lateral resistor cathode structure for a field emission device, which may be of the type disclosed in the Meyer ('780) patent, is illustrated in cross-sectional and plan views in FIGS. 2A and 2B, respectively.
  • a microtip emissive cathode electron source is disclosed in this reference including cathode and/or gate conductors which are formed in a mesh structure, the microtip emitters being formed on the resistive layer in a matrix arrangement within the mesh spacings.
  • the illustrative field emission structure 40 of FIGS. 2A and 2B includes a cathode conductor 42 having a mesh-like structure formed on an optional thin silica insulating layer 44 on a glass substrate 46.
  • a resistive layer 48 formed over conductor 42 and insulating layer 44 supports a multiplicity of electrically conductive microtip emitters 50.
  • a gate electrode, comprising a layer of an electrically conductive material 52, is deposited on an insulating layer 54 which overlays resistive layer 48.
  • Microtip emitters 50 are in the shape of cones which are formed on resistive layer 48 within apertures 56 through conductive layer 52 and insulating layer 54.
  • Conductive layer 52 is arranged as rows of conductive bands across the surface of field emission structure 40, and the mesh-like structure comprising cathode conductor 42 is arranged as columns of conductive bands across the surface of field emission structure 40, thereby permitting matrix-addressed selection of microtips 50 at the intersection of a row and column corresponding to a pixel.
  • This arrangement provides an improvement in breakdown resistance of a field effect microtip emissive device, without requiring an increase in the thickness of the resistive layer.
  • the disclosed mesh-like structure of the cathode conductor (and/or the gate conductor) permits the cathode conductors and the resistive coating of the Meyer patent to lie substantially in the same plane.
  • the breakdown resistance is no longer susceptible to defects in the thickness of the resistive coating; rather, the resistive coating which laterally separates the cathode conductor from the microtip provides a ballast against excessive current. It is therefore sufficient to maintain a distance between the cathode conductor and the microtip which is adequate to prevent breakdown, while still retaining a homogenization effect for which the resistive coating is supplied.
  • each microtip is positioned over a resistive layer.
  • the thickness, or vertical dimension, of the resistive layer provides a ballast against excessive current; in the Meyer reference, the lateral spacing along the resistive layer provides the ballast.
  • the ballast is in the form of a resistive drop such that those microtips drawing the most current have the most resistive drop, thus acting in such a way as to reduce the current per tip.
  • An equivalent circuit of the ballast arrangements of both references would have each tip in series with an individual buffer resistor to limit the field emission current.
  • the ballast resistance between microtips 50 and cathode mesh structure 42 varies with the position of the individual microtip 50 within the array.
  • microtip 50 C in the corner of the array, will have a lower ballast resistance than microtip 50 S , at a side of the array, which, in turn, will have a lower ballast resistance than microtip 50 I , in the interior of the array.
  • ballast resistance among the microtips becomes even more pronounced as the size of the array increases, to the point where, in a five-by-five or a six-by-six array, it is believed that the potential at one or more interior microtips will be insufficient to stimulate substantial electron emission.
  • an arrangement is desired which will permit all of the microtips to be at a substantially equal potential.
  • Opposing the need for equal distances from each microtip to the conductive mesh is the need to pack as many microtips as possible into a small area to thereby reduce the emission current from each microtip.
  • This need for dense packing can best be realized by having large clusters of microtips, with the extreme case being a complete array of microtips the size of the final display pixel.
  • the larger the cluster the greater the variation in tip to tip emissions due to resistive path differences to the conductive cathode mesh.
  • electron emission apparatus comprising, a conductive plate, a microtip electron emitter occupying a region substantially overlying the conductive plate.
  • a stripe conductor laterally spaced from the conductive plate; and a resistive layer in electrical contact with the stripe conductor and the conductive plate.
  • electron emission apparatus comprising, a conductive plate, a microtip electron emitter occupying a region substantially overlying the conductive plate; and a stripe conductor laterally spaced from the conductive plate.
  • an electron emission apparatus which comprises a conductive mesh structure, and a conductive plate laterally spaced from the mesh structure and occupying a central region within a space in the mesh structure.
  • the apparatus further comprises a resistive layer in electrical contact with the mesh structure and the conductive plate, and a plurality of microtip emitters located in the central region.
  • an electron emission apparatus which comprises an insulating substrate, a conductor formed as a mesh structure on the substrate, the mesh structure defining mesh spaces, and conductive plates on the insulating substrate occupying areas within the mesh spaces.
  • the apparatus also comprises a layer of an electrically resistive material on the substrate overlaying the mesh structure and the conductive plates.
  • the apparatus further comprises an electrically insulating layer on the resistive layer, and a conductive layer on the insulating layer, the conductive layer having a plurality of apertures formed therein and extending through the insulating layer.
  • the apparatus comprises microtip emitters on the resistive layer, each emitter formed within a corresponding one of the apertures in the conductive layer.
  • the present invention also provides a method of fabricating electron emission apparatus comprising, forming a conductive plate on a substrate, forming a stripe conductor laterally spaced from the plate, forming a microtip electron emitter occupying a region substantially overlaying the conductive plate; and forming a resistive layer in electrical contact with the stripe conductor and the conductive plate.
  • a mesh structure on a substrate, forming a conductive plate laterally spaced from the mesh structure and occupying a central region within a space in the mesh structure, forming a resistive layer in electrical contact with the mesh structure and the conductive plate; and forming a microtip emitter in the central region.
  • the method comprises the following steps: providing an insulating substrate; depositing a first layer of conductive material on the substrate and forming a mesh structure and conductive plates therefrom, the conductive plates being formed within mesh spaces defined by the mesh structure; forming a layer of an electrically resistive material on the substrate overlaying the mesh structure and the conductive plates; forming an electrically insulating layer on the resistive layer; forming a second conductive layer on the insulating layer; forming apertures in the second conductive layer over the conductive plates, the apertures extending through the insulating layer; and forming microtip emitters on the resistive layer, each emitter formed within a corresponding one of the apertures in the second conductive layer.
  • the emitter plate 60 of an illustrative field emission flat panel display device in accordance with a first embodiment of the present invention. More specifically, the emitter plate 60 of FIG. 3 comprises a substrate 66 having an optional thin insulating layer 64 overlaid thereon. Insulating layer 64 may be included to enhance the adhesion of a subsequent layer to substrate 66 and to limit diffusion of impurities from substrate 66 to the subsequent layer.
  • a coating 68 of a resistive material overlays insulating layer 64, and a mesh-like structure 62 of an electrically conductive material, which may be similar to the type described in the Meyer ('780) patent, is formed over coating 68, the arrangement of the conductive meshes of structure 62 defining spaces enclosed therein.
  • a conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62.
  • An insulating layer 74 covers resistive coating 68, conductive mesh structure 62 and conductive plate 78, and a conductive layer 72 overlays insulating layer 74.
  • Microtip emitters 70 illustratively in the shape of cones, are formed on the upper surface of conductive plate 78 within apertures 76, which extend through conductive layer 72 and insulating layer 74 down to plate 78.
  • Electron emission from microtips 70 is stimulated by the application of a first potential to the conductors of mesh structure 62, functioning as a cathode, and the application of a second, more positive potential to conductive layer 72, functioning as a gate electrode.
  • a first potential to the conductors of mesh structure 62, functioning as a cathode
  • a second, more positive potential to conductive layer 72 functioning as a gate electrode.
  • microtip emitters 70 are preferably configured in arrays, typically of the type shown in FIG. 2B; furthermore, emitter plate 60 is preferably arranged in a row-and-column matrix for purposes of selecting individual pixels of the display.
  • the conductive layer 72 comprising the gate electrode may be arranged as rows of conductive bands across the surface of emitter plate 60, and the conductive mesh structure 62 comprising the cathode conductor may be arranged as columns of conductive bands across the surface of emitter plate 60, the rows of conductive layer 72 typically being orthogonal to the columns of conductive mesh structure 62, thereby permitting matrix-addressed selection of the microtips 70 at the intersection of a row and column corresponding to a pixel.
  • substrate 66 may comprise glass, and insulating layer 64 may comprise silicon dioxide (SiO2) having a thickness of approximately 50 nanometers.
  • Resistive layer 68 may comprise amorphous silicon (a-Si) having a thickness of approximately 0.5 to 2.0 microns, and insulating layer 74 may comprise SiO2, having a thickness of approximately 1.0 micron.
  • Conductive mesh 62 may be made of aluminum, molybdenum, chromium, niobium or the like, and have a width of approximately 4 microns and a thickness of approximately 0.2 microns.
  • Conductive plate 78 may comprise any of the aforementioned metal conductors, and have a thickness of approximately 0.2 micron.
  • Conductive layer 72 may be made of niobium and have a thickness of approximately 0.4 micron; the diameters of apertures 76 in conductive layer 72 may typically be 1.4 microns.
  • Microtips 70 are typically made of molybdenum and are formed such that their apexes are substantially level with the top surface of conductive layer 72.
  • a method for fabricating emitter plate 60 may comprise the following steps: providing an insulating substrate 66; depositing a layer 64 of SiO2 on substrate 66; forming a layer 68 of an electrically resistive material over layer 64; depositing a layer of conductive material on resistive layer 68 and forming conductive mesh structure 62 and conductive plates 78 within the spaces defined by the conductors of structure 62 therefrom, typically by photolithographic and etching processes; forming an electrically insulating layer 74 overlaying resistive layer 68, mesh structure 62 and conductive plates 78; forming a conductive layer 72 on insulating layer 74; forming a plurality of apertures 76 in conductive layer 72 over conductive plates 78, the apertures 76 extending through insulating layer 74 down to conductive plates 78; and forming microtip emitters 70 on conductive plates 78, each emitter 70 formed within one of the apertures 76 in conductive layer 72.
  • a glass substrate 66 is coated with a thin insulating layer 64, typically SiO2, which may be sputter deposited to a thickness of 50 nm.
  • a resistive layer 68 is added by sputtering amorphous silicon (a-Si) onto the SiO2 layer 64 to a thickness of approximately 500-2000 nm; alternatively the amorphous silicon may be deposited by a chemical vapor deposition (CVD) process.
  • a-Si amorphous silicon
  • a layer of a conductive material which may typically comprise aluminum, molybdenum, chromium or niobium, is deposited over resistive layer 68 to a thickness of approximately 200 nm.
  • a layer of photoresist is spun on over the conductive layer to a thickness of approximately 1000 nm.
  • a patterned mask is disposed over the light-sensitive photoresist layer, exposing desired regions of the photoresist to light, thereby defining the cathode mesh structure 62 and the conductive plates 78.
  • the exposed regions are removed during a developing step, which may comprise soaking the assembly in a caustic or basic chemical developer.
  • the developer removes the unwanted photoresist regions which were exposed to light
  • the exposed regions of the conductive layer are then removed, typically by a reactive ion etch (RIE) process using sulfur hexafluoride (SF6).
  • RIE reactive ion etch
  • the etchant may comprise boron trichloride (BCl3).
  • the remaining photoresist is removed by dry ashing in oxygen plasma or stripping solutions known in semiconductor manufacturing processes, leaving the cathode mesh structure 62 and the conductive plates 78 over resistive layer 68.
  • An electrically insulating layer 74 is deposited over resistive layer 68, cathode mesh structure 62 and the conductive plates 78 to a thickness of approximately 1000 nm.
  • a second layer 72 of a conductive material which may typically comprise aluminum, molybdenum, chromium or niobium, is deposited over insulating layer 74, typically by e-beam evaporation, to a thickness of approximately 400 nm.
  • a layer of photoresist is spun on over this second conductive layer 72 to a thickness of approximately 1000 nm.
  • a patterned mask is disposed over the light-sensitive photoresist layer, exposing desired regions of the photoresist to light, thereby defining an array of apertures 76 which are positioned directly over conductive plate 78.
  • the regions of photoresist which were exposed to light are removed during a developing step.
  • the uncovered regions of the second conductive layer 72, comprising apertures 76, are then removed, typically by a reactive ion etch (RIE) process using sulfur hexafluoride (SF6).
  • RIE reactive ion etch
  • the etchant may comprise boron trichloride (BCl3).
  • Conductive layer 72 may then be used as a mask to dry etch apertures 76 in insulating layer 74 down to conductive plate 78 with an etchant such as CF4. Insulating layer 74 may then be undercut by a subsequent wet etch process using diluted (buffered) HF. This undercutting of insulating layer 74 helps eliminate shorts between microtip emitters 70 (the cathode electrodes) and conductive layer 72 (the gate electrode), and it may facilitate better microtip formation at a subsequent process step in the manufacture of the flat panel display. The remaining photoresist layer 54 may then be removed by a dry etch process using oxygen plasma or a commercial stripper solution.
  • microtip emitters 70 may follow the method described in the Borel et al. ('161) patent.
  • the microtip emitters 70 are formed by first depositing a parting layer comprising, e.g., nickel, by vacuum evaporation at a glancing angle with respect to the surface of the structure, thus ensuring that the parting layer material is not deposited on the apertured inner walls of insulating layer 74.
  • a conductive coating comprising, e.g., molybdenum
  • the nickel parting layer is then selectively dissolved by an electrochemical process so as to expose the apertured conductive layer 72 and bring about the appearance of the electron emitting microtips 70.
  • the emitter plate 60' of an illustrative field emission flat panel display device in accordance with a second embodiment of the present invention. More specifically, the emitter plate 60' of FIG. 4 comprises a substrate 66 having an optional thin insulating layer 64 overlaid thereon. A mesh-like structure 62' of an electrically conductive material, which may be similar to the type described in the Meyer ('780) patent, is formed over insulating layer 64, the arrangement of the meshes of structure 62' defining spaces enclosed therein. A coating 68' of a resistive material overlays insulating layer 64 and conductive mesh structure 62'.
  • a conductive plate 78 is formed on top of resistive coating 68' within the spacing defined by the meshes of conductor 62'.
  • An insulating layer 74' covers resistive coating 68' and conductive plate 78, and a conductive layer 72 overlays insulating layer 74'.
  • Microtip emitters 70 illustratively in the shape of cones, are formed on the upper surface of conductive plate 78 within apertures 76, which extend through conductive layer 72 and insulating layer 74' down to plate 78.
  • a method for fabricating emitter plate 60' may comprise the following steps: providing an insulating substrate 66; depositing a layer 64 of SiO2 on substrate 66; depositing a layer of conductive material on layer 64 and forming conductive mesh structure 62' therefrom, typically by photolithographic and etching processes; forming a layer 68' of an electrically resistive material over layer 64 and over conductive mesh structure 62'; depositing a layer of conductive material on resistive layer 68' and forming conductive plates 78 therefrom within the spaces defined by conductor 62', typically by photolithographic and etching processes; forming an electrically insulating layer 74' on resistive layer 68' and on conductive plates 78; forming a conductive layer 72 on insulating layer 74'; forming a plurality of apertures 76 in conductive layer 72 over conductive plates 78, the apertures 76 extending through insulating layer 74' down to conductive plates 78; and forming micro
  • the emitter plate 60'' of an illustrative field emission flat panel display device in accordance with a third embodiment of the present invention. More specifically, the emitter plate 60'' of FIG. 5 comprises a substrate 66 having an optional thin insulating layer 64 overlaid thereon.
  • a mesh-like structure 62'' of an electrically conductive material which may be similar to the type described in the Meyer ('780) patent, is formed on insulating layer 64, the arrangement of conductive meshes of structure 62'' defining spaces enclosed therein.
  • a conductive plate 78'' is also formed on insulating layer 64 within the spacing defined by the meshes of conductor 62''.
  • a coating 68'' of a resistive material overlays insulating layer 64 in the regions separating mesh structure 62'' and conductive plate 78''.
  • An insulating layer 74'' covers resistive coating 68'', conductive mesh structure 62'' and conductive plate 78'', and a conductive layer 72 overlays insulating layer 742.
  • Microtip emitters 70 illustratively in the shape of cones, are formed on the upper surface of conductive plate 78'' within apertures 76, which extend through conductive layer 72 and insulating layer 74'' down to plate 78''.
  • a method for fabricating emitter plate 60'' may comprise the following steps: providing an insulating substrate 66; depositing a layer 64 of SiO2 on substrate 66; depositing a layer of conductive material on layer 64 and forming conductive mesh structure 62'' and conductive plates 78'' within the spaces defined by the conductors of structure 62'' therefrom, typically by photolithographic and etching processes; forming a layer 68'' of an electrically resistive material on layer 64 in the regions separating mesh structure 62'' and conductive plates 78''; forming an electrically insulating layer 74'' on resistive layer 68'', mesh structure 62'' and conductive plates 78''; forming a conductive layer 72 on insulating layer 74''; forming a plurality of apertures 76 in conductive layer 72 over conductive plates 78'', the apertures 76 extending through insulating layer 74'' down to conductive plates 78'';
  • the emitter plate 61 of an illustrative field emission flat panel display device in accordance with a fourth embodiment of the present invention. More specifically, the emitter plate 61 of FIG. 10 comprises a substrate 66 having an optional thin insulating layer 64 overlaid thereon. A mesh-like structure 63 of an electrically conductive material, which may be similar to the type described in the Meyer ('780) patent, is formed on insulating layer 64, the arrangement of conductive meshes of structure 63 defining spaces enclosed therein.
  • a conductive plate 79 is also formed on insulating layer 64 within a space defined by the mesh of conductor 63.
  • a coating 69 of a resistive material overlays insulating layer 64, conductive mesh structure 63 and conductive plate 79.
  • An insulating layer 75 covers resistive coating 69, and a conductive layer 72 overlays insulating layer 75.
  • Apertures 76 are formed through conductive layer 72 and insulating layer 75 down to the upper surface of resistive layer 69. Apertures 76 are formed within the space of mesh structure 63 directly above conductive plate 79.
  • Microtip emitters 70 illustratively in the shape of cones, are formed on the upper surface of resistive layer 69 within apertures 76.
  • conductive mesh structure 63 comprises the cathode electrode
  • conductive layer 72 comprises the gate electrode of field emission device 61. Electron emission from microtip emitters 70 is effected by the application of a potential at conductive mesh structure 63 which is positive with respect to the potential on conductive layer 72.
  • the structure shown in FIG. 10 may include a typical thickness dimension of resistive layer 69 between microtip emitters 70 and conductive plate 79 of one micron, and a typical lateral spacing between each conductive plate 79 and the conductive mesh structure 63 of five microns.
  • the arrangement of FIG. 10 provides a relatively small vertical ballast resistance between each microtip emitter 70 and the conductive plate 79 thereunder, and a considerably larger lateral ballast resistance between each conductive plate 79 and the conductive mesh structure 63.
  • a method for fabricating emitter plate 61 may comprise the following steps: providing an insulating substrate 66; depositing a layer 64 of SiO2 on substrate 66; depositing a layer of conductive material, illustratively aluminum, chromium, molybdenum or niobium, on layer 64 and forming conductive mesh structure 63 and conductive plates 79 within the spaces defined by the conductors of structure 63 therefrom, typically by photolithographic and etching processes; forming a layer 69 of an electrically resistive material, illustratively amorphous silicon, on layer 64 overlaying mesh structure 63 and conductive plates 79; forming an electrically insulating layer 75 on resistive layer 69; depositing a layer of conductive material, illustratively niobium, on insulating layer 75 and forming row conductors 72 therefrom, typically by photolithographic and etching processes; forming a plurality of apertures 76 in conductive layer 72 over conductive
  • FIG. 6 there is shown a plan view of a first arrangement of emitter clusters according to the embodiments of the present invention as illustrated in FIGS. 3, 4 and 5.
  • the view shown by FIG. 6 is similar to that which would be presented by the embodiment of FIG. 3 with conductive layer 72 and insulating layer 74 removed.
  • FIG. 6 depicts a mesh structure 80 of conductors, conductive plates 82 within the spaces formed by mesh structure 80, a plurality of microtips 84 on each of the conductive plates 82, and regions 86 of resistive material in the spacings between mesh conductor 80 and conductive plates 82.
  • microtips 84 are formed as a four-by-four array on conductive plates 82, all of the plates 82 including an equal number of microtips 84.
  • each microtip 84 on a single plate 82 is at an equal potential, regardless of its position on the plate, and should display substantially equal emission and degradation characteristics.
  • FIG. 7 there is shown a plan view of a second arrangement of emitter clusters according to the present invention.
  • the view of FIG. 7 illustrates a mesh structure 90 of conductors, four conductive plates 92 within each of the spaces formed by mesh structure 90, a plurality of microtips 94 on each of the conductive plates 92, and regions 96 of resistive material in the spacings between mesh conductor 90 and conductive plates 92.
  • microtips 94 are formed as a four-by-four array on conductive plates 92, all of the plates 92 including an equal number of microtips 94.
  • conductive plates 92 may be positioned symmetrically within the spacings of mesh conductor 90 such that plates 92 have an equal resistance path from conductor 90. Hence, there will be an equal resistance between conductor 90 and each microtip 94 on a conductive plate 92, regardless of the number of microtips 94 on a plate 92, the resistance value being determined generally by the lengths of the sides of plates 92 adjacent conductor 90, the distances between plates 92 and conductor 90, and the sheet resistance of the material in region 96. Hence, each microtip 94 on a plate 92 is at an equal potential, regardless of its position on the plate, and should display equal emission and degradation characteristics.
  • FIG. 7 provides an advantage of increased density of microtips over the embodiment of FIG. 6. Because of symmetry considerations, all of the conductive plates 92 within each mesh spacing have an equal resistance path to mesh conductor 90. Thus, although the voltage levels of conductive plates 92 float, they are substantially equal, differing only as a result of variations in the emission characteristics of microtips 94.
  • the inter-plate spacings s1 and s2 can be minimal, and significantly less than the spacings s3 and s4 between plates 92 and mesh conductor 90, the latter spacings establishing the ballast resistance of microtips 94.
  • the number of clustered microtips on conductive plate 82 (of FIG. 6) and conductive plate 92 (of (FIG. 7) is a design choice.
  • An upper limit is determined in part by the small probability of a failed microtip, recognizing that the relatively rare occurrence of a microtip shorted to the gate electrode effectively causes a short circuit of all microtips in that cluster, resulting in no emission of electrons from any of the microtips of that cluster.
  • a large number of microtips clustered on each conductive plate is desirable from a standpoint of reducing the total emission required by each microtip, as well as minimizing the effects of variations in emission characteristics among the clustered microtips.
  • FIGS. 6 and 7 represent two configurations in which conductive plates are positioned within the spacings of a conductive mesh structure so as to provide equal resistance paths between the conductive mesh and each of the conductive plates, it is anticipated that many more such configurations may be envisioned, e.g., differences in the shapes of the conductive plates and differences in the positional relationships between the plates and the conductive mesh, all of which provide the same or similar advantages as the illustrated embodiments, and all of which accord with the principles of the present invention.
  • configurations of the mesh structure, other than the square spacings illustrated herein may be used without departing from the principles of the present invention, e.g., rectangular, triangular or hexagonal (honeycomb) spacings.
  • FIG. 8 there is shown a plan view of an arrangement of emitter clusters in relation to a conductive column line in accordance with the present invention.
  • the view of FIG. 8 illustrates a striped structure 100 of conductors, a plurality of conductive plates 102, each adjacent and laterally spaced from a corresponding stripe conductor 100, a plurality of microtips 104 on each of the conductive plates 102, and regions 106 of resistive material in the spacings between conductive stripes 100 and conductive plates 102.
  • conductive stripes 100 are substantially parallel to each other, and are spaced from one another by two conductive plates 102.
  • microtips 104 are formed as a five-by-four array on conductive plates 102, all of the plates 102 including an equal number of microtips 104.
  • the current carried to the cluster of microtips 104 on each of the conductive plates 102 is a function of the resistance value of the thin film resistor formed by resistive layer 106 between column stripe conductor 100 and conductive plate 102.
  • this resistance value is directly related to the sheet resistance of layer 106 and dimension L, the distance between conductive plate 102 and stripe conductor 100, and inversely related to dimension W, the width of conductive plate 102 adjacent conductor 100.
  • the effect of small spacings s5 and s6 between adjacent conductive plates 102 is similar to that discussed in relation to the embodiment of FIG. 7, but with the additional advantages provided by the increased density of conductive plates 102 offered by the embodiment of FIG. 8.
  • the cluster spacings i.e., the spacings s1 through s6, can be made to exceed 2 microns to allow use of projection printing techniques, or may be made smaller than 2 microns to maximize the cluster packing through use of stepper printing techniques.
  • the cluster spacings can be made to exceed 2 microns to facilitate etching of their conductive layer by wet chemical means, or may be made smaller than 2 microns to maximize the cluster packing through use of plasma etching technologies.
  • the cluster spacings may be set to zero value, creating a continuous array that is limited only by the dimensions of the pixel.
  • the length of the cluster resistor, dimension L, the distance between conductive plate 102 and stripe conductor 100 in FIG. 8, may be reduced without affecting the resistance value by use of a resistive layer with higher sheet resistance, e.g., a thinner layer or a more lightly doped material. Reduction in the length of dimension L is limited, of course, by the breakdown field between stripe conductor 100 and conductive plate 102.
  • the cluster resistor value can be reduced without affecting length of the cluster resistor, dimension L, by enlarging dimension W, the width of conductive plate 102 adjacent conductor 100 in FIG. 8, while holding the sheet resistance value of the resistive layer 106 constant.
  • FIG. 9 there is shown a plan view of an arrangement of pixels including the emitter clusters and conductive column lines of the present invention.
  • This arrangement illustrates column conductors comprising stripes 100 and a plurality of conductive plates 102, each adjacent and laterally spaced from a corresponding stripe conductor 100.
  • conductive stripes 100 are substantially parallel to each other, and are spaced from one another by two conductive plates 102.
  • Stripe conductors 100 are joined at their upper and lower extremities (outside the active region of the display) by conductive bus regions 110.
  • Region 114 comprising the intersection of the striped column conductors 100 which are joined by a single bus region 110 at each end thereof (the cathode electrode) and a single row conductor (the gate electrode) may represent a single display pixel.
  • Optional cross-line conductors 116 in the inactive area between display pixels may be added for redundancy and current spreading.
  • FIGS. 8 and 9 represent a typical configuration in which conductive plates are positioned adjacent a stripe conductor structure so as to provide equal resistance paths between the conductive stripes and each of the conductive plates, it is anticipated that many more such configurations may be envisioned, e.g., differences in the shapes of the conductive plates and differences in the positional relationships between the plates and the stripes, all of which provide the same or similar advantages as the illustrated embodiments, and all of which accord with the principles of the present invention.
  • a method for fabricating an emitter plate of the embodiment of FIGS. 8 and 9, in accordance with the present invention, may comprise the following steps: providing an insulating substrate; depositing a layer of SiO2 on the substrate; forming a layer 106 of an electrically resistive material over the SiO2 layer; depositing a layer of conductive material on resistive layer 106 and forming therefrom conductive plates 102, conductive column stripes 100, bus regions 110 and (optionally) cross-line conductors 116, typically by photolithographic and etching processes; forming an electrically insulating layer overlaying resistive layer 106, conductive plates 102 and conductive column stripes 100; depositing a layer of conductive material on the insulating layer and forming row conductors 112 therefrom, typically by photolithographic and etching processes; forming a plurality of apertures in row conductors 112 over conductive plates 102, the apertures extending through the insulating layer down to conductive plates 102; and forming microtip emitters 104 on
  • another method for fabricating an emitter plate of the embodiment of FIGS. 8 and 9, in accordance with the present invention may comprise the following steps: providing an insulating substrate; depositing a layer of SiO2 on the substrate; depositing a layer of conductive material on the SiO2 layer and forming therefrom conductive column stripes 100, bus regions 110 and (optionally) cross-line conductors 116, typically by photolithographic and etching processes; forming a layer 106 of an electrically resistive material over the SiO2 layer and conductive column stripes 100; depositing a layer of conductive material on resistive layer 106 and forming therefrom conductive plates 102, typically by photolithographic and etching processes; forming an electrically insulating layer overlaying resistive layer 106 and conductive plates 102; depositing a layer of conductive material on the insulating layer and forming row conductors 112 therefrom, typically by photolithographic and etching processes; forming a plurality of apertures in row conductors 112 over conductive plates
  • FIG. 11 there is shown a cross-sectional view of an emitter plate 118 embodying a second arrangement of emitter clusters adjacent conductive column lines in accordance with the present invention.
  • the view of FIG. 11 illustrates a substrate 120 having an optional thin insulating layer 122 overlaid thereon.
  • a plurality of stripe conductors 124, extending perpendicular to the drawing sheet, are located on layer 122, as are a plurality of conductive plates 128.
  • the relative positioning of stripe conductors 124 and conductive plates 128, is the same as for FIG. 8, wherein plates 128 are each adjacent and laterally spaced from a corresponding stripe conductor 124.
  • a coating 126 of a resistive material overlays insulating layer 122, stripe conductors 126 and conductive plates 128.
  • An insulating layer 130 covers resistive coating 126, and a conductive layer 132 overlays insulating layer 130.
  • Apertures 136 are formed through conductive layer 132 and insulating layer 130 down to the upper surface of resistive layer 126. Apertures 136 are formed directly above conductive plates 128.
  • Microtip emitters 134 illustratively in the shape of cones, are formed on the upper surface of resistive layer 126 within apertures 136.
  • stripe conductors 124 comprise the cathode electrode
  • conductive layer 132 comprises the gate electrode of field emission device 118. Electron emission from microtip emitters 134 is effected by the application of a potential at stripe conductors 124 which is positive with respect to the potential on conductive layer 132.
  • the structure shown in FIG. 11 may include a typical thickness dimension of resistive layer 126 between microtip emitters 134 and conductive plate 128 of one micron, and a typical lateral spacing between each conductive plate 128 and the adjacent stripe conductor 124 of five microns.
  • the arrangement of FIG. 11 provides a relatively small vertical ballast resistance between each microtip emitter 134 and the conductive plate 128 thereunder, and a considerably larger lateral ballast resistance between each conductive plate 128 and the adjacent stripe conductor 124.
  • a method for fabricating emitter plate 118 may comprise the following steps: providing an insulating substrate 120; depositing a layer 122 of SiO2 on substrate 120; depositing a layer of a conductive material, illustratively aluminum, chromium, molybdenum or niobium, on the SiO2 layer 122 and forming therefrom conductive plates 128, column stripes 124, and bus regions and cross-line conductors of the type shown in FIG.
  • a layer 126 of an electrically resistive material illustratively amorphous silicon, over conductive column stripes 124 and conductive plates 128; forming an electrically insulating layer 130 overlaying resistive layer 126; depositing a layer of conductive material, illustratively niobium, on insulating layer 130 and forming row conductors 132 therefrom, typically by photolithographic and etching processes; forming a plurality of apertures 136 in row conductors 132 over conductive plates 128, the apertures extending through insulating layer 130 down to resistive layer 126; and forming microtip emitters 134, illustratively of molybdenum, on resistive layer 126, each emitter 134 formed within one of the apertures 136 in row conductors 132.
EP95117883A 1994-11-18 1995-11-14 Dispositif émitteur d'électrons Withdrawn EP0713236A1 (fr)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US341740 1994-11-18
US08/341,829 US5541466A (en) 1994-11-18 1994-11-18 Cluster arrangement of field emission microtips on ballast layer
US08/341,740 US5557159A (en) 1994-11-18 1994-11-18 Field emission microtip clusters adjacent stripe conductors
US08/378,331 US5536993A (en) 1994-11-18 1995-01-26 Clustered field emission microtips adjacent stripe conductors
US378328 1995-01-26
US378331 1995-01-26
US08/378,328 US5569975A (en) 1994-11-18 1995-01-26 Cluster arrangement of field emission microtips
US341829 1995-01-26

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EP0713236A1 true EP0713236A1 (fr) 1996-05-22

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EP0867908A1 (fr) * 1997-03-28 1998-09-30 Pixtech S.A. Uniformisation de l'émission électronique potentielle d'une cathode d'écran plat à micropointes
US6097139A (en) * 1995-08-04 2000-08-01 Printable Field Emitters Limited Field electron emission materials and devices

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