EP0708982A1 - A method of treating a semi-conductor wafer - Google Patents

A method of treating a semi-conductor wafer

Info

Publication number
EP0708982A1
EP0708982A1 EP95918082A EP95918082A EP0708982A1 EP 0708982 A1 EP0708982 A1 EP 0708982A1 EP 95918082 A EP95918082 A EP 95918082A EP 95918082 A EP95918082 A EP 95918082A EP 0708982 A1 EP0708982 A1 EP 0708982A1
Authority
EP
European Patent Office
Prior art keywords
layer
deposited
polymer
wafer
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95918082A
Other languages
German (de)
French (fr)
Inventor
Christopher David Dobson
Adrian Kiermasz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Electrotech Equipments Ltd
Original Assignee
Electrotech Equipments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Electrotech Equipments Ltd filed Critical Electrotech Equipments Ltd
Publication of EP0708982A1 publication Critical patent/EP0708982A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

  • This invention relates to a method for treating a semi ⁇ conductor wafer and in particular, but not exclusively, to what is known as planarisation.
  • Our Copending International Application No. PCT/GB93/- 01368 (published as O94/01885) describes two methods of depositing a short-chain polymer on a wafer to form a generally planar layer:
  • a method of treating a semi-conductor wafer comprising, depositing a liquid short-chain polymer having the general formula Si ⁇ (OH) y or Si ⁇ H (OH) z on the wafer to form a generally planar layer.
  • a method of treating a semi-conductor wafer including positioning the wafer in a chamber, introducing into the chamber silicon-containing gas or vapour and a compound, containing peroxide bonding, in vapour form, reacting the silicon-containing gas or vapour with the compound to form a short-chain polymer and condensing the polymer on the wafer to form a generally planar layer.
  • silicon-containing gas or vapour introducing into the chamber silicon-containing gas or vapour and a compound, containing peroxide bonding, in vapour form, reacting the silicon-containing gas or vapour with the compound to form a short-chain polymer and condensing the polymer on the wafer to form a generally planar layer.
  • the polymer With the method of the type described the polymer will be in liquid form, at least to the extent that it is capable of a degree of self-levelling and, as is noted in Applica- tion No. PCT/GB93/01368, the water in the layer has to be removed at least partially, by heating.
  • a relatively thick capping layer was deposited prior to heating with the intention of providing physical stability for the polymer layer. Whilst this is advantage ⁇ ous it has not proved entirely successful as careful control of the process is required.
  • the invention consists in a method of the type described, further comprising depositing a diffu ⁇ sion layer on the surface of the polymer layer to allow moisture to be released from the polymer at a controlled rate.
  • the diffusion layer acts as a permeable membrane.
  • the diffusion layer is deposited at between -20 and 60°C and preferably at around 0°C.
  • the diffusion layer can be deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD) and may be of the order of 500°A.
  • PECVD Plasma Enhanced Chemical Vapour Deposition
  • the wafer may be subjected to a preliminary heating stage prior to having a capping layer deposited. A final bake may then take place between 400-475°C.
  • the polymer layer may be preceded by the deposition of an underlayer or seed layer.
  • the method can conveniently include two chambers, one being a 'cold' chamber for the deposition of the polymer layer and the diffusion layer and the other being a hot chamber for the deposition of the underlayer and the capping layer.
  • Figure 1 to 4 illustrates schematically the steps of a planarisation process with the exception of the deposition of the diffusion layer.
  • Figures 1 to 4 substantially correspond with Figures 3a to 3d of Application No. PCT/GB93/01368 with the excep ⁇ tion that Figure 3 replaces Figure 3c of the earlier Application.
  • Figures 1, 2 and 4 substantially stand and are hereby incorporated into this specification.
  • the first is a •hot' chamber in which it is proposed that the steps illustrated in Figures 1 and 4 (of this Application) should be performed, whilst the second chamber is a 'cold' chamber in which the steps described in connection with Figures 1 and 2 (of this Application) are performed.
  • the use of two chambers is not essential, but substantially increases the process control and repeatability.
  • a very thin capping layer e.g. of Si0 2
  • the lattice structure of that layer is sufficiently open for it to act as a diffusion membrane, which controls the rate of moisture loss from the polymer or planarising layer when the wafer is heated, for example, by the heating up of the 'hot' chamber, to which the wafer can be transferred, prior to the Figure 4 "hot" capping.
  • this heating may raise the wafer temperature to between 200-450°C (preferably 300°C) .
  • a furnace or other final bake to 400°to 475°C (preferably 450°C) can take place.
  • the 'cold* cap or diffusion layer is preferably around 500°A.
  • the use of this 'cold* cap has produced high quality planarisation layers without cracks.
  • N 2 0, 0 2 or 0 2 containing gas plasma after the underlayer has been deposited. This can in affect be a continuation of the deposition process or a separate step. It appears to enhance the 'flowing' properties of the planarising layer.
  • This feature can be beneficially used in a method of the type described with or without the 'cold' cap.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

A method of treating a semi-conductor wafer is described in which a short-chain polymer is deposited on the wafer to planarise surface features on the wafer and a diffusion layer is deposited on the surface of the polymer layer to allow moisture to be released from the polymer at a controlled rate.

Description

A method of treating a semi-conductor wafer
This invention relates to a method for treating a semi¬ conductor wafer and in particular, but not exclusively, to what is known as planarisation. Our Copending International Application No. PCT/GB93/- 01368 (published as O94/01885) describes two methods of depositing a short-chain polymer on a wafer to form a generally planar layer:
1. A method of treating a semi-conductor wafer comprising, depositing a liquid short-chain polymer having the general formula Siχ (OH)y or Siχ H (OH)z on the wafer to form a generally planar layer.
2. A method of treating a semi-conductor wafer, including positioning the wafer in a chamber, introducing into the chamber silicon-containing gas or vapour and a compound, containing peroxide bonding, in vapour form, reacting the silicon-containing gas or vapour with the compound to form a short-chain polymer and condensing the polymer on the wafer to form a generally planar layer. For the purpose of this specification these methods will be known as a method of the type described.
With the method of the type described the polymer will be in liquid form, at least to the extent that it is capable of a degree of self-levelling and, as is noted in Applica- tion No. PCT/GB93/01368, the water in the layer has to be removed at least partially, by heating. In order to prevent cracking, once a quantity of the water had been removed, a relatively thick capping layer was deposited prior to heating with the intention of providing physical stability for the polymer layer. Whilst this is advantage¬ ous it has not proved entirely successful as careful control of the process is required.
From one aspect the invention consists in a method of the type described, further comprising depositing a diffu¬ sion layer on the surface of the polymer layer to allow moisture to be released from the polymer at a controlled rate.
Preferably the diffusion layer acts as a permeable membrane. In a preferred embodiment the diffusion layer is deposited at between -20 and 60°C and preferably at around 0°C. The diffusion layer can be deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD) and may be of the order of 500°A. Once the diffusion layer is deposited, the wafer may be subjected to a preliminary heating stage prior to having a capping layer deposited. A final bake may then take place between 400-475°C. As has been mentioned in the earlier Application No.
PCT/GB93/01368 the polymer layer may be preceded by the deposition of an underlayer or seed layer.
The method can conveniently include two chambers, one being a 'cold' chamber for the deposition of the polymer layer and the diffusion layer and the other being a hot chamber for the deposition of the underlayer and the capping layer.
The invention may be performed in various ways and a specific embodiment will now be described, by way of example, with reference to the accompanying drawings, in which:-
Figure 1 to 4 illustrates schematically the steps of a planarisation process with the exception of the deposition of the diffusion layer.
Figures 1 to 4 substantially correspond with Figures 3a to 3d of Application No. PCT/GB93/01368 with the excep¬ tion that Figure 3 replaces Figure 3c of the earlier Application. Thus the explanation and variations described in the earlier Application in connection with Figures 1, 2 and 4 (3a, 3b and 3d) substantially stand and are hereby incorporated into this specification.
There is, however, an additional proposal that there should be two chambers in the apparatus. The first is a •hot' chamber in which it is proposed that the steps illustrated in Figures 1 and 4 (of this Application) should be performed, whilst the second chamber is a 'cold' chamber in which the steps described in connection with Figures 1 and 2 (of this Application) are performed. The use of two chambers is not essential, but substantially increases the process control and repeatability.
Turning to Figure 3 it has been discovered that the integrity of the polymer layer is very much dependent on the rate of loss of moisture being carefully controlled. Such control can be achieved by very careful temperature control, but this is awkward, expensive and time consuming.
The Applicants have now appreciated that if they deposit under cold conditions (-20 to 60°C, but preferably at 0°C) a very thin capping layer, e.g. of Si02, then the lattice structure of that layer is sufficiently open for it to act as a diffusion membrane, which controls the rate of moisture loss from the polymer or planarising layer when the wafer is heated, for example, by the heating up of the 'hot' chamber, to which the wafer can be transferred, prior to the Figure 4 "hot" capping. Typically this heating may raise the wafer temperature to between 200-450°C (preferably 300°C) . Once that later cap is deposited a furnace or other final bake to 400°to 475°C (preferably 450°C) can take place.
The 'cold* cap or diffusion layer is preferably around 500°A. The use of this 'cold* cap has produced high quality planarisation layers without cracks.
One further improvement which has been noted can be obtained by the use of N20, 02 or 02 containing gas plasma after the underlayer has been deposited. This can in affect be a continuation of the deposition process or a separate step. It appears to enhance the 'flowing' properties of the planarising layer.
This feature can be beneficially used in a method of the type described with or without the 'cold' cap.

Claims

Claims
1. A method of the type described further comprising depositing a diffusion layer on the surface of the polymer layer to allow moisture to be released from the polymer at a controlled rate.
2. A method as claimed in Claim 1, wherein the diffusion layer acts as a permeable membrane.
3. A method as claimed in Claim 1 or Claim 2, wherein the diffusion layer is deposited at between -20 and 60°C.
4. A method as claimed in Claim 3, wherein the diffusion layer is deposited at around 0°C.
5. A method as claimed in any one of the preceding Claims, wherein the diffusion layer is deposited by Plasma Enhanced
Chemical Vapour Deposition.
6. A method as claimed in any one of the preceding Claims, wherein the layer is of the order of 500A° Nick.
7. A method as claimed in any one of the preceding Claims, further including a preliminary heating stage.
8. A method as claimed in Claim 7, wherein the layer is subsequently capped with a capping layer and the wafer is then baked.
9. A method as claimed in anyone of the preceding Claims, wherein the deposition of the polymer layer is preceded by the deposition of an underlayer or seed layer.
10. A method as claimed in any one of the preceding Claims, where it is performed in two chambers; one being a 'cold' chamber for the deposition of the polymer layer and diffusi- on layer and the other being a 'hot' chamber for the deposi¬ tion of the underlayer and the capping layer.
11. A method as claimed in any one of the preceding Claims, further comprising treating the wafer with an N20, 02 or an 02 containing gas plasma after the underlayer has been deposited.
EP95918082A 1994-05-14 1995-05-10 A method of treating a semi-conductor wafer Withdrawn EP0708982A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9409713A GB9409713D0 (en) 1994-05-14 1994-05-14 A method of treating a semi-conductor wafer
GB9409713 1994-05-14
PCT/GB1995/001057 WO1995031823A1 (en) 1994-05-14 1995-05-10 A method of treating a semi-conductor wafer

Publications (1)

Publication Number Publication Date
EP0708982A1 true EP0708982A1 (en) 1996-05-01

Family

ID=10755170

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95918082A Withdrawn EP0708982A1 (en) 1994-05-14 1995-05-10 A method of treating a semi-conductor wafer

Country Status (8)

Country Link
EP (1) EP0708982A1 (en)
JP (1) JPH09501020A (en)
KR (1) KR100334855B1 (en)
CN (1) CN1128582A (en)
CA (1) CA2167085A1 (en)
GB (1) GB9409713D0 (en)
TW (1) TW307020B (en)
WO (1) WO1995031823A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2734402B1 (en) * 1995-05-15 1997-07-18 Brouquet Pierre PROCESS FOR ELECTRICAL ISOLATION IN MICROELECTRONICS, APPLICABLE TO NARROW CAVITIES, BY DEPOSITION OF OXIDE IN THE VISCOUS STATE AND CORRESPONDING DEVICE
DE19712233C2 (en) * 1996-03-26 2003-12-11 Lg Philips Lcd Co Liquid crystal display and manufacturing method therefor
US7923383B2 (en) 1998-05-21 2011-04-12 Tokyo Electron Limited Method and apparatus for treating a semi-conductor substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2009518C (en) * 1990-02-07 2000-10-17 Luc Ouellet Spin-on glass processing technique for the fabrication of semiconductor device
JP3262334B2 (en) * 1992-07-04 2002-03-04 トリコン ホルディングズ リミテッド Method for processing semiconductor wafers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9531823A1 *

Also Published As

Publication number Publication date
TW307020B (en) 1997-06-01
CA2167085A1 (en) 1995-11-23
JPH09501020A (en) 1997-01-28
GB9409713D0 (en) 1994-07-06
CN1128582A (en) 1996-08-07
KR960704349A (en) 1996-08-31
KR100334855B1 (en) 2002-11-13
WO1995031823A1 (en) 1995-11-23

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