JPH09501020A - Semiconductor wafer processing method - Google Patents

Semiconductor wafer processing method

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JPH09501020A
JPH09501020A JP7529436A JP52943695A JPH09501020A JP H09501020 A JPH09501020 A JP H09501020A JP 7529436 A JP7529436 A JP 7529436A JP 52943695 A JP52943695 A JP 52943695A JP H09501020 A JPH09501020 A JP H09501020A
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layer
diffusion layer
polymer
deposited
wafer
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ドブソン，クリストファー，デビッド
キアーマスズ，エイドリアン
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エレクトロテック イクイップメンツ リミテッド
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

(57)【要約】 ウエハ上に短鎖状ポリマーを被着してウエハの表面特性をプレーナ化し、ポリマー層表面に拡散層を被着してコントロールされた率でポリマーから水分が放出する半導体ウエハ処理方法。 (57) [Summary] A semiconductor wafer in which a short-chain polymer is deposited on the wafer to planarize the surface properties of the wafer, and a diffusion layer is deposited on the polymer layer surface to release water from the polymer at a controlled rate. Processing method.

Description

【発明の詳細な説明】 半導体ウエハ処理方法 本発明は半導体ウエハを処理するための方法に関するものであり、特に、但し 限定的にではなく、プレーナ化として知られるものに関するものである。 本出願人の他の出願ＰＣＴ／ＧＢ９３／０１３６８号（ＷＯ９４／０１８８５ として公告された）は、ウエハ上に短鎖状ポリマーを被着して総じて平らな層を 形成する二種類の方法を説明している。 １．ウエハ上に一般式Six(OH)yまたはSixHy(OH)zを有する液体短鎖状ポリマー を被着して総じて平らな層を形成することから成る、半導体ウエハ処理方法。 ２．ウエハをチャンバに入れ、チャンバにシリコン含有ガスまたは蒸気ならび に過酸化物結合剤を含有する化合物を蒸気の形態で入れ、シリコン含有ガスまた は蒸気と化合物を反応させて短鎖状ポリマーを形成し、ポリマーをウエハ上に凝 縮させて総じて平らな層を形成することを含む、半導体ウエハ処理方法。 以下の説明のため、これらの方法のことを前述タイプの方法と表すことにする 。 前述タイプの方法では、ポリマーは少なくとも所定の度合いの自己水平化が可 能な程度の液体の形態をなし、特許出願第ＰＣＴ／ＧＢ９３／０１３６８号に記 載されているように、加熱によって層の水分の少なくとも一部が除去されなく てはならない。クラック発生を防止するため、所定量の水分が除去されると、ポ リマー層に物理的安定をあたえるために、加熱前に比較的厚いキャップ層が被着 される。これは有益ではあるが、細心のプロセス管理が要求されるので、完全に 成功するという裏付けがない。 一態様において、本発明は前述タイプの方法であり、更に、コントロールされ た率でポリマーから水分が放出されるようにポリマー層の表面に拡散層を被着す ることを含む。 拡散層は、浸透性のある膜として作用することが好ましい。好適実施例では、 拡散層は−２０から６０°Ｃ間、好ましくは０°Ｃ近くで被着される。拡散層は 、プラズマ増速化学蒸着法（ＰＥＣＶＤ）で被着することが可能で、５００°Ａ 程度のものである。拡散層が被着されると、ウエハは、キャップ層が被着される 前に予備加熱段階にかけられる。その後、４００−４７５°Ｃで最終焼成が行わ れる。 冒頭の特許出願第ＰＣＴ／ＧＢ９３／０１３６８号に述べられている通り、ポ リマー層の前に、下層またはシード層が被着されることもある。 当該方法は便宜のために２つのチャンバを具備でき、一方はポリマー層と拡散 層の被着のための「低温」チャンバであり、他方は下層およびキャップ層の被着 のための「高温」チャンバである。 本発明は種々の方法で実施されるが、一例として特定実施例を添付図面を参照 しながら以下に説明する。 図１から４は、拡散層の被着を除くプレーナ化プロセスの複数ステップを図式 的に示したものである。 図１−４は特許出願第ＰＣＴ／ＧＢ９３／０１３６８号の図３ａ−３ｄに実質 的に対応するものであるが、但し図３は先の出願特許の図３ｃとは別のものであ る。従って、図１、２、および４（３ａ、３ｂおよび３ｄ）について先の出願特 許に記述されている説明ならびに変更態様は基本的に有効で、これにより本明細 書に組み込まれる。 しかしながら、装置内に２つのチャンバを備える、という追加提案がある。第 一のものは、（この出願特許の）図１と４に記載の複数ステップを実施すること が提案される「高温」チャンバであり、第二のチャンバは、（この出願特許の） 図１と２に照らして説明されている複数ステップを実施する「低温」チャンバで ある。二つのチャンバを使用することは必要不可欠ではないものの、実質的にプ ロセス制御と再現性を増大するものである。 図３を見ると、ポリマー層の完全性は、注意深くコントロールされた水分損失 率に著しく依存していることが分かった。このようなコントロールは極めて細心 な温度調整によって達成できるが、これは厄介で、高価で、時間がかかる。 例えばSiO2の極めて薄いキャップ層を低温条件下（−２０から６０°Ｃ、但し 好ましくは０°Ｃ）で被着した場合、図４の「高温」キャップ形成前に、例えば ウエハが変態できるようになるまで「高温」チャンバで加熱することによってウ エハを加熱したときに、ポリマーまたはプレーナ化層からの水分損失率をコント ロールする拡散膜としてキャップ層が作用するのに十分なほど、キャップ層の格 子構造が開状態にあることを、出願人等は認知した。一般に、この加熱でウエハ の温度を２００−４５０°Ｃ間（好ましくは３００°Ｃ）に上昇する。後からの キャップが被着されれば、炉等による４００°から４７５°Ｃ（好ましくは４５ ０°Ｃ）の最終焼成が実施できる。 「低温」キャップまたは拡散層は、５００°Ａ程度であることが好ましい。こ の「低温」キャップの利用により、クラックの無い高品質なプレーナ化層が作成 された。 注目された更なる一改善は、下層が被着された後に、N2O、O2、またはO2含有 ガス・プラズマを利用することによって得られる。これは、性質に応じて、被着 プロセスから続けることも、独立ステップにすることもできる。プレーナ化層の 「流動」特性を向上するようである。 この特徴は、「低温」キャップと組合わせても、組合わせなくても、前述タイ プの方法で有益に利用できる。DETAILED DESCRIPTION OF THE INVENTION Semiconductor wafer processing method The present invention relates to a method for processing semiconductor wafers, in particular, although not limiting, to a what is known as a planarized. Our other application, PCT / GB93 / 01368 (published as WO94 / 01885), describes two methods of depositing short chain polymers on a wafer to form a generally flat layer. ing. 1. A method of processing a semiconductor wafer comprising depositing a liquid short chain polymer having the general formula Si x (OH) y or Si x H y (OH) z on a wafer to form a generally flat layer. 2. A wafer is placed in a chamber, a silicon-containing gas or vapor and a compound containing a peroxide binder are placed in the form of vapor, and the silicon-containing gas or vapor is reacted with the compound to form a short-chain polymer. A method of processing a semiconductor wafer, the method comprising: condensing on a wafer to form a generally flat layer. For purposes of the following description, these methods will be referred to as methods of the type described above. In a method of the aforementioned type, the polymer is in the form of a liquid to the extent that it is capable of at least a certain degree of self-leveling, and upon heating, as described in patent application PCT / GB93 / 01368, the moisture content of the layer At least some must be removed. In order to prevent cracking, once a certain amount of water has been removed, a relatively thick cap layer is applied before heating to give the polymer layer physical stability. While this is beneficial, it requires meticulous process control and is not proof of complete success. In one aspect, the invention is a method of the type described above, further comprising depositing a diffusion layer on the surface of the polymer layer so that the polymer releases water at a controlled rate. The diffusion layer preferably acts as a permeable membrane. In the preferred embodiment, the diffusion layer is deposited between -20 and 60 ° C, preferably near 0 ° C. The diffusion layer can be deposited by plasma enhanced chemical vapor deposition (PECVD) and is of the order of 500 ° A. Once the diffusion layer has been applied, the wafer is subjected to a preheating step before the cap layer is applied. Then, final firing is performed at 400-475 ° C. An underlayer or seed layer may be applied before the polymer layer, as described in the initial patent application PCT / GB93 / 01368. The method may comprise two chambers for convenience, one being a "cold" chamber for the deposition of the polymer layer and the diffusion layer and the other a "hot" chamber for the deposition of the bottom and cap layers. Is. The present invention may be implemented in various ways, and by way of example, specific embodiments are described below with reference to the accompanying drawings. 1 to 4 show diagrammatically the steps of the planarization process, excluding the diffusion layer deposition. FIGS. 1-4 substantially correspond to FIGS. 3a-3d of patent application No. PCT / GB93 / 01368, except that FIG. 3 is separate from FIG. 3c of the earlier filed patent. Therefore, the explanations and modifications described in the previous patent applications for FIGS. 1, 2 and 4 (3a, 3b and 3d) are basically valid and are hereby incorporated by reference. However, there is an additional proposal to provide two chambers in the device. The first is a "hot" chamber, proposed to carry out the multiple steps described in FIGS. 1 and 4 (of this patent), and the second chamber (of this patent). And a "cold" chamber that performs the steps described in the context of 1. and 2. Although the use of two chambers is not essential, it substantially increases process control and reproducibility. Looking at FIG. 3, it was found that the integrity of the polymer layer was significantly dependent on a carefully controlled rate of water loss. Such control can be achieved by very careful temperature regulation, but this is cumbersome, expensive and time consuming. For example, if a very thin cap layer of SiO 2 is deposited under low temperature conditions (-20 to 60 ° C, but preferably 0 ° C), for example, the wafer may be transformed before the "hot" cap formation of FIG. The lattice of the cap layer is sufficient to act as a diffusion film that controls the rate of water loss from the polymer or planarization layer when the wafer is heated by heating in a "hot" chamber until Applicants have recognized that the structure is open. Generally, this heating raises the temperature of the wafer to between 200-450 ° C (preferably 300 ° C). If a cap is applied later, final firing at 400 ° to 475 ° C (preferably 450 ° C) in a furnace or the like can be performed. The "cold" cap or diffusion layer is preferably on the order of 500 ° A. The use of this "cold" cap produced a high quality planarization layer that was crack free. A further improvement noted is obtained by utilizing a N 2 O, O 2 or O 2 containing gas plasma after the underlayer has been deposited. This can either follow the deposition process or be an independent step, depending on the nature. It appears to improve the "flow" properties of the planarization layer. This feature can be beneficially utilized in methods of the type described above, with or without a "cold" cap.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 キアーマスズ，エイドリアン イギリス国 ブリストル ビーエス12 ７ ユーダブリュ エイボン クリーヴドン ピル ウェイ ８────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kearmass, Adrian             United Kingdom Bristol BS 12 7             UW Avon Clevedon             Pill Way 8

Claims (1)

【特許請求の範囲】 １．コントロールされた率でポリマーから水分が放出されるようにポリマー層の 表面に拡散層を被着することを更に含む、前述タイプの方法。 ２．拡散層が透過性膜として作用することを特徴とする、請求項１に記載の方法 。 ３．拡散層は−２０と６０°Ｃの間で被着されることを特徴とする、請求項１ま たは請求項２に記載の方法。 ４．拡散層は０°Ｃ近くで被着されることを特徴とする、請求項３に記載の方法 。 ５．拡散層は、プラズマ増速化学蒸着法で被着されることを特徴とする、上記請 求項のいずれか一項に記載の方法。 ６．当該層は５００°Ａニック程度のものであることを特徴とする、上記請求項 のいずれか一項に記載の方法。 ７．予備加熱段階を更に含むことを特徴とする、上記請求項のいずれか一項に記 載の方法。 ８．当該層は、続いてキャップ層でキャップされ、その後にウエハが焼成される ことを特徴とする、請求項７に記載の方法。 ９．ポリマー層の被着の前に、下層またはシード層の被着が行われることを特徴 とする、上記請求項のいずれかに記載の方法。 １０．一方がポリマー層と拡散層の被着のための「低温」チャンバであり、他方 が下層とキャップ層の被着のための「高温」チャンバである、二つのチャンバで 実施されるこ とを特徴とする、上記請求項のいずれか一項に記載の方法。 １１．下層が被着された後に、N2O、O2、またはO2含有ガス・プラズマでウエハ を処理することを更に含む、上記請求項のいずれか一項に記載の方法。[Claims] 1. A method of the foregoing type further comprising depositing a diffusion layer on the surface of the polymer layer so that the polymer releases moisture at a controlled rate. 2. Method according to claim 1, characterized in that the diffusion layer acts as a permeable membrane. 3. Method according to claim 1 or 2, characterized in that the diffusion layer is deposited between -20 and 60 ° C. 4. Method according to claim 3, characterized in that the diffusion layer is deposited near 0 ° C. 5. Method according to any of the preceding claims, characterized in that the diffusion layer is deposited by plasma enhanced chemical vapor deposition. 6. Method according to any of the preceding claims, characterized in that said layer is of the order of 500 ° A nick. 7. Method according to any of the preceding claims, characterized in that it further comprises a preheating step. 8. Method according to claim 7, characterized in that the layer is subsequently capped with a cap layer, after which the wafer is baked. 9. Method according to any of the preceding claims, characterized in that the application of the underlayer or the seed layer is carried out before the application of the polymer layer. 10. It is carried out in two chambers, one being a "cold" chamber for the deposition of the polymer layer and the diffusion layer and the other a "hot" chamber for the deposition of the lower and cap layers. A method according to any one of the preceding claims. 11. The method of any one of the preceding claims, further comprising treating the wafer with a N 2 O, O 2 , or O 2 containing gas plasma after the underlayer has been deposited.
JP7529436A 1994-05-14 1995-05-10 Semiconductor wafer processing method Pending JPH09501020A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9409713.6 1994-05-14
GB9409713A GB9409713D0 (en) 1994-05-14 1994-05-14 A method of treating a semi-conductor wafer
PCT/GB1995/001057 WO1995031823A1 (en) 1994-05-14 1995-05-10 A method of treating a semi-conductor wafer

Publications (1)

Publication Number Publication Date
JPH09501020A true JPH09501020A (en) 1997-01-28

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US7923383B2 (en) 1998-05-21 2011-04-12 Tokyo Electron Limited Method and apparatus for treating a semi-conductor substrate

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FR2734402B1 (en) * 1995-05-15 1997-07-18 Brouquet Pierre PROCESS FOR ELECTRICAL ISOLATION IN MICROELECTRONICS, APPLICABLE TO NARROW CAVITIES, BY DEPOSITION OF OXIDE IN THE VISCOUS STATE AND CORRESPONDING DEVICE
DE19712233C2 (en) * 1996-03-26 2003-12-11 Lg Philips Lcd Co Liquid crystal display and manufacturing method therefor

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CA2009518C (en) * 1990-02-07 2000-10-17 Luc Ouellet Spin-on glass processing technique for the fabrication of semiconductor device
AU4506993A (en) * 1992-07-04 1994-01-31 Christopher David Dobson A method of treating a semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7923383B2 (en) 1998-05-21 2011-04-12 Tokyo Electron Limited Method and apparatus for treating a semi-conductor substrate

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TW307020B (en) 1997-06-01
KR100334855B1 (en) 2002-11-13
EP0708982A1 (en) 1996-05-01
WO1995031823A1 (en) 1995-11-23
CN1128582A (en) 1996-08-07
GB9409713D0 (en) 1994-07-06
CA2167085A1 (en) 1995-11-23

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