EP0700180A1 - Dispositif pour le traitement de signaux de audio numériques - Google Patents

Dispositif pour le traitement de signaux de audio numériques Download PDF

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Publication number
EP0700180A1
EP0700180A1 EP95112658A EP95112658A EP0700180A1 EP 0700180 A1 EP0700180 A1 EP 0700180A1 EP 95112658 A EP95112658 A EP 95112658A EP 95112658 A EP95112658 A EP 95112658A EP 0700180 A1 EP0700180 A1 EP 0700180A1
Authority
EP
European Patent Office
Prior art keywords
processor
bus
main
parts
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95112658A
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German (de)
English (en)
Inventor
Robert Huber
Andreas Von Ow
Philippe Duc
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harman International Industries Inc
Original Assignee
Studer Professional Audio AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Studer Professional Audio AG filed Critical Studer Professional Audio AG
Publication of EP0700180A1 publication Critical patent/EP0700180A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H60/00—Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
    • H04H60/02—Arrangements for generating broadcast information; Arrangements for generating broadcast-related information with a direct linking to broadcast information or to broadcast space-time; Arrangements for simultaneous generation of broadcast information and broadcast-related information
    • H04H60/04—Studio equipment; Interconnection of studios

Definitions

  • the invention relates to a device for processing digital audio signals, having a number n inputs, a number m outputs, at least one processor for processing the signals and a bus for optionally distributing the signals from the inputs to the processor and the outputs.
  • Such devices are already known in audio technology and typically consist of a bus being connected between the inputs and the outputs, which bus is additionally connected to a processor unit in which the digital signals can be processed.
  • processing is to be understood, for example, as filter functions or the merging or adding of signals.
  • the bus used is a so-called parallel bus, which provides a time window for the data from each input channel so that the signals appear in series on the bus. If there are several processors, they always have their own control section, so that each processor must receive instructions for the desired processing.
  • the invention as characterized in the claims, therefore solves the problem of creating a device for processing digital audio signals that allows to work with a larger number of input and output channels and thereby any connections between the channels and any processing of signals in the time available, ie to perform without signs of overload.
  • SIMD single instruction multiple data
  • main processor is connected to the bus, which on the one hand can read and read the data from the individual inputs and outputs and, on the other hand, data directly into the memory of the individual processor parts.
  • the main processor is also connected to external components such as memory etc., regulates the traffic with them and can also exchange data with them.
  • the individual processor parts are preferably also connected to a further bus in the sense of a series connection.
  • FIG. 1 shows inputs 1a to 1n for digital audio signals which open into an input interface 2. For example, this consists of a shift register with a subsequent word memory for each input, but this is not shown here.
  • the input interface 2 is connected to a parallel bus 3, which in turn is connected to an output interface 4, which has a structure similar to that of the input interface 2.
  • Outputs 5a to 5m for digital output signals are connected to the output interface 4.
  • 6 designates a SIMD computer which has a control part 7 and processor parts 8a, 8b, 8c etc., which are each connected to bus 3 via connections 9a, 10a, 9b, 10b etc.
  • Another bus 11 connects a memory 26 of the interface 2 with the processor part 8a, and the individual processor parts 8a, 8b, 8c, etc., and ends in a processor part 16 of a main processor 14, so that a series circuit is created.
  • the main processor 14 is also connected to the bus 3 via connections 12 and 13.
  • the main processor 14 also consists of a control part 15 and a processor part 16. This is connected via further connections 17 and 18 to a communication unit 19, which in turn has connections 20 and 21 designed as a bus for external components such as external main computers and memories etc.
  • the communication unit 19 consists here, for example, of an interface 22 for communication with a Main computer and an interface 23 for communication with a main memory.
  • the elements are also connected via connections 24 and 25 for the transmission of commands.
  • the interfaces 2 and 4 each have a memory 26 and 27 for cascaded input or output of data.
  • a plurality of such devices can also be connected in series via corresponding inputs and outputs 28 and 29. This is necessary, for example, if you want to work with an even larger number of inputs 1.
  • FIG. 2 schematically shows the structure of the control part 7.
  • This consists of an instruction memory (INSTR RAM) 31, a RISC (Reduced Instruction Set Computer) processor 32 and an address computer (ADDRESS ALU) 33, which are connected to each other via a bus 34 and 35 are.
  • instruction memory ISTR RAM
  • RISC Reduced Instruction Set Computer
  • ADDRRESS ALU address computer
  • FIG. 3 shows, for example, the structure of a processor part 8a, 8b or 8h.
  • This consists of a multiplier and accumulator (MAC) 36, a working register set (ACCU) 37, which comprises, for example, 8 working registers, an arithmetic logic unit (ALU) 38 and a data memory (DATA RAM) 39 with address pointers 40.
  • MAC multiplier and accumulator
  • ACCU working register set
  • ALU arithmetic logic unit
  • DATA RAM data memory
  • the control part 15 can have the same structure as the control part 7 shown in FIG. 2. This also applies to the processor part 16, which can have the same structure as a processor part 8a etc., as is known from FIG. 3.
  • the digital audio signals reach the input interface 2 via the inputs 1a, 1b, 1c, ... 1n, where they are read in succession by the main processor 14 via the bus 3 and the connection 12 and then via the connection 13, the bus 3 and the Connections 9a, 9b, 9c ... 9h are written into the processor parts 8a, 8b, 8c ... 8h of the SIMD computer 6.
  • the input weighting and summation which is described in the instruction memory 31 of the control unit 7 of the SIMD computer 6, is now carried out in parallel in all processor parts 8a, 8b, 8c ... 8h and all results are simultaneously summed up in a working register 37 via the further bus 11 of the neighboring processor part.
  • the data from the further bus 11 now go directly to the processor part 16 of the main processor 14, where the total weighting, which is described in the instruction memory 31 of the control unit 15, is carried out and the respective results via the connection 13 and the bus 3 into the outputs 5a, 5b, ... 5m of the output interface 4.
  • the data which represent the size of the total and the respective input weighting, are written by an external unit, for example the external main computer, via the connection 20 into the interface 22 of the communication unit 19, where they are read by the main processor 14 via the connection 17 with the description, which is located in the instruction memory 31 of the control part 15, evaluated and via the connection 13, the bus 3 and the connections 9a, 9b, 9c ... 9h into the corresponding data memory 39 of the respective processor parts 8a, 8b, 8c. .. 8h are written, where they are then used as weighting coefficients.
  • an external unit for example the external main computer

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Complex Calculations (AREA)
  • Microcomputers (AREA)
EP95112658A 1994-08-31 1995-08-11 Dispositif pour le traitement de signaux de audio numériques Withdrawn EP0700180A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH2660/94 1994-08-31
CH266094 1994-08-31

Publications (1)

Publication Number Publication Date
EP0700180A1 true EP0700180A1 (fr) 1996-03-06

Family

ID=4238729

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95112658A Withdrawn EP0700180A1 (fr) 1994-08-31 1995-08-11 Dispositif pour le traitement de signaux de audio numériques

Country Status (1)

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EP (1) EP0700180A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961981A1 (fr) * 1997-12-23 1999-12-08 Kessler Interactive Digital Designs, Inc. Enregistreur numerique portable
WO2006089667A1 (fr) * 2005-02-23 2006-08-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Dispositif et procede pour reguler un dispositif de rendu de synthese de champ electromagnetique
CN100367268C (zh) * 2002-12-16 2008-02-06 索尼计算机娱乐公司 信号处理设备和娱乐设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2552958A1 (fr) * 1983-10-03 1985-04-05 Moulin Andre Console numerique de traitements de signaux
EP0422965A2 (fr) * 1989-10-13 1991-04-17 Texas Instruments Incorporated Circuit pour le traitement continu de signaux vidéo dans un processeur vectoriel synchrone

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2552958A1 (fr) * 1983-10-03 1985-04-05 Moulin Andre Console numerique de traitements de signaux
EP0422965A2 (fr) * 1989-10-13 1991-04-17 Texas Instruments Incorporated Circuit pour le traitement continu de signaux vidéo dans un processeur vectoriel synchrone

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
G.W. MC NALLY.: "Microprocessor mixing and processing of digital audio signals", JOURNAL OF THE AUDIO ENGINEERING SOCIETY, vol. 27, no. 10, NEW YORK US, pages 793 - 803 *
TERUO FUJINO AND YOHEI TAKANE: "Digital mixing console meets professional mixing needs.", JEE JOURNAL OF ELECTRONIC ENGINEERING, vol. 28, TOKYO JP, pages 38 - 42, XP000230856 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961981A1 (fr) * 1997-12-23 1999-12-08 Kessler Interactive Digital Designs, Inc. Enregistreur numerique portable
EP0961981A4 (fr) * 1997-12-23 2002-11-20 Kessler Interactive Digital De Enregistreur numerique portable
CN100367268C (zh) * 2002-12-16 2008-02-06 索尼计算机娱乐公司 信号处理设备和娱乐设备
WO2006089667A1 (fr) * 2005-02-23 2006-08-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Dispositif et procede pour reguler un dispositif de rendu de synthese de champ electromagnetique
US7668611B2 (en) 2005-02-23 2010-02-23 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Apparatus and method for controlling a wave field synthesis rendering means
CN101129086B (zh) * 2005-02-23 2011-08-03 弗劳恩霍夫应用研究促进协会 用于控制波场合成呈现装置的设备和方法

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