EP0683514A1 - Überbrückende Mask/Isolator für lokale Verbindungen und Herstellungsverfahren - Google Patents

Überbrückende Mask/Isolator für lokale Verbindungen und Herstellungsverfahren Download PDF

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Publication number
EP0683514A1
EP0683514A1 EP95480048A EP95480048A EP0683514A1 EP 0683514 A1 EP0683514 A1 EP 0683514A1 EP 95480048 A EP95480048 A EP 95480048A EP 95480048 A EP95480048 A EP 95480048A EP 0683514 A1 EP0683514 A1 EP 0683514A1
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Prior art keywords
layer
forming
gate stack
mask
stack
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EP95480048A
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English (en)
French (fr)
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John Edward Cronin
Darrell Meulemans
Carter Welling Kaanta
Gordon Seth Starkey
Randy William Mann
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Definitions

  • the present invention relates in general to semiconductor devices and to semiconductor device fabrication methods. More specifically, the invention relates to stack structures for semiconductor devices employing local interconnects, and in particular, to a dual functioning overpass mask/insulator for isolating a gate stack from an overpass conductor at the M0 wiring level. The invention also relates to methods for fabricating such stack structures and such a dual functioning overpass mask/insulator.
  • CMOS Complementary Metal Semiconductor
  • FET Field- Effect Transistor
  • Another common, but more complicated interconnection is that between adjacent diffusions of an FET, without a conductive contact to the intervening gate.
  • a recent alternative approach referred to as local interconnect(s) begins with an insulator being blanket-deposited over a substrate and any devices formed thereon. This blanket insulator is then selectively etched to expose desired device contacts. An inlaid metal structure is deposited in the etched region to electrically contact the exposed device contacts. This metal structure is then planarized with the remaining insulator.
  • the local interconnection technique is used to electrically contact devices beneath the first wiring level, which is formed as described above. The technique avoids problems associated with multiple wiring layers. In particular, the inlaid metal has less resistance, supports connections of very short lengths and is generally stronger than conformal wiring.
  • One specific embodiment of the local interconnect technique is described in U.S. Patent No.
  • the inlaid metal structure, or stud will electrically contact all gate stacks of the devices exposed by the insulator etch. Multiple gates or diffusions may be exposed and thus contacted. Using selective etching, an effective interconnect between a gate and an adjacent diffusion is possible. However, a local interconnection between diffusions that remains insulated from the intervening gate has not been accomplished.
  • the techniques should offer a circuit designer flexibility and provide options based on available processing technologies.
  • the resulting structures should have precisely-formed, predictable shapes and electrical characteristics. Further, the fabrication technique should not diminish the electrical response of current circuit designs, and should not involve overly complex fabrication steps.
  • the invention comprises in a first aspect a method for fabricating a semiconductor structure including the steps of: damascening a first mask of electrically insulative material into an electrically conductive material; forming a second mask above the electrically conductive material; using both the first mask and the second mask to define a conductor image for an overpass conductor; and retaining the first mask as an overpass insulator electrically insulating a portion of the electrically conductive material from the overpass conductor.
  • the invention comprises a method for forming a gate stack which includes the steps of: providing a layer of electrically conductive material above an upper surface of a substrate; damascening an electrically insulative layer into the layer of electrically conductive material; and etching the layer of electrically conductive material and the electrically insulative layer to form the gate stack, wherein a portion of the layer of electrically conductive material and a portion of the electrically insulative layer comprise the gate stack and are self-aligned.
  • a fabrication method for forming two gate stacks of equal height but different composition above an upper surface of a substrate.
  • the method includes: forming a first layer of material above the upper surface of the substrate in a first area; forming two layers of material above the upper surface of the substrate in a second area, wherein an interim semiconductor structure is defined having multiple layers above the upper surface of the substrate; and planarizing an upper surface of the interim semiconductor structure such that formation of a first gate stack in the first area and a second gate stack in the second area results in two gate stacks of different composition but equal height above the upper surface of the substrate.
  • a method for fabricating a gate stack and an overpass conductor includes forming the gate stack above a substrate in part by damascening an insulator layer into a conductor layer; using the portion of the insulator layer in the gate stack has an overpass mask to partially define a conductor image for the overpass conductor; and forming the overpass conductor above the gate stack such that the overpass conductor is insulated from the portion of the conductor layer in the gate stack by the insulator layer in the gate stack.
  • the invention comprises in a first aspect a stack structure, disposed above a substrate, which includes a conducting layer and an insulating layer disposed above the conducting layer.
  • An overpass conductor surrounds the stack structure such that the insulating layer electrically insulates the conducting layer from the overpass conductor.
  • the conducting layer and the insulating layer are self-aligned. Further details of this semiconductor structure are described herein.
  • a semiconductor structure including a first gate stack and a second gate stack.
  • the first gate stack has a first composition and an upper surface located a distance 'X' above an upper surface of a substrate.
  • the second gate stack has an upper surface at a distance 'X' above the upper surface of the substrate.
  • the second gate stack has a second composition which includes an upper layer and a lower layer.
  • the present invention comprises novel methods/structures that greatly improve the utility of local interconnects.
  • inlaid local interconnects can selectively contact some exposed devices and remain insulated from others.
  • Alternate processing steps are provided that offer designers options based on available technologies.
  • the resulting structures are precisely shaped for improved device performance and functionality in advanced semiconductor systems.
  • the present invention comprises a semiconductor interconnect structure and fabrication method.
  • semiconductor structures are provided wherein stack components are electrically insulated from a surrounding layer of inlaid, local interconnect material.
  • the insulating function is partially accomplished with self-aligned overpass insulators selectively embedded below the metal interconnect material.
  • local interconnect fabrication involves depositing a blanket layer of an insulator over the stack structures and then etching the layer to form a mask that defines a conductor image.
  • a modification of the etching pattern is possible to leave insulators on gates not requiring contact to the local interconnect.
  • this modified etching technique can create alignment problems between the gate, the inlaid conductor, and other exposed devices.
  • polysilicon gate stacks are formed as a group and exposed by common etching steps. These gate stacks, as a group, may include insulators disposed thereon. The devices are then fully surrounded with additional insulator material which, upon etching, serves as a boundary material which defines a conductor image for the inlaid metal. The elevation of this insulator layer above the substrate exceeds that of any of the devices and/or contacts. Removing previously-applied insulators from gate stacks requiring electrical contact during this etch requires a mask that is perfectly aligned to the now-submerged gate stack. Because accurate mask alignment is impossible, remaining portions of the insulator will adversely affect subsequent formations. In particular, the subsequently deposited conductor will likely be misaligned to the lower devices thereby adversely affecting the overall electrical characteristics of the device.
  • RIE reactive ion etching
  • a first embodiment of the invention comprises a fabrication method for producing a dual functioning, self-aligned overpass mask/insulator.
  • Second, third and fourth fabrication embodiments entail modifications and improvements to the first embodiment and accommodate various processing technologies to produce structures with different physical and electrical characteristics.
  • a semiconductor structure fabricated in accordance with the first embodiment of the present invention is shown to comprise two stack structures 31 and 33, and an inlaid layer of conductive material 57 surrounding the structures.
  • the conductive material is a metal such as tungsten with barriers like titanium nitride, as well as other materials like copper or aluminum-copper.
  • the stack structures, which reside above a substrate 10, include gate oxides 44a and 44b. In this particular structure, the stacks share a diffusion 49 in substrate 10.
  • a gate 36 is shown disposed over gate oxide 44b.
  • Gate 36 e.g., composed of a heavily-doped polycrystalline silicon layer, electrically controls a depletion region in substrate 10, i.e., across gate oxide 44b.
  • An overpass insulator 34 is shown disposed on an upper surface 38 of the gate 36. Oxide spacers 42c and 42d extend from overpass insulator 34 to the substrate 10, along the sidewall(s) of gate 36. Similarly, nitride barriers 59c and 59d are disposed along the outer surfaces of oxide spacers 42c and 42d. Gate 36 is therefore totally electrically insulated from inlaid conductive material 57 that forms the local interconnect. As shown, a significant component of this insulating structure comprises overpass insulator 34. This insulator, having been formed simultaneously with gate 36, is self-aligned with the gate and comprises part of stack structure 33.
  • stack structure 31 and diffusion 49 each electrically contact inlaid conductive material 57.
  • oxide spacers 42a and 42b and residual nitride barriers 59a and 59b extend along the sidewall(s) of gate 40.
  • the upper layer 48 of structure 31 comprises a conducting layer, e.g., composed of a gate silicide. This layer serves as the ohmic contact between inlaid conductive material 57 and gate 40.
  • diffusion 49 electrically contacts conductive material 57 via a diffusion silicide 50.
  • gate 36 is fully insulated from conductive material 57, while other local structures electrically contact material 57, e.g., gate 40 and diffusion 49.
  • the height of stack structures 31 (before silicidation) and 33 are equivalent because of the mask and etch sequences employed (described below). This equivalent height allows spacers of equivalent width to form along the outer surfaces of the stack structures.
  • Stack structure 71 includes a self-aligned gate 40 and a gate silicide 75, which is decoupled in thickness from an optional silicide 79 above diffusion 77. This is accomplished by forming the two silicides independently. In addition, the elevation of both stack structures above the substrate is equivalent. An inlaid conductive layer (not shown) formed around the structures shown, would again electrically contact gate silicide 75 and silicide 79, but not gate 36.
  • Fig. 4g depicts a semiconductor structure fabricated in accordance with a fourth embodiment of the invention.
  • Stack structures 91 and 93 are similar to the structures discussed above in connection with Fig. 2e; however, an improvement in the etching sequence in the fourth embodiment allows both embedded silicide 116 and overpass insulator 102 to be formed without complicated etching sequences.
  • the various fabrication sequences in accordance with the present invention are next described in detail.
  • the first fabrication embodiment is a method by which a dual functioning overpass mask/insulator is formed on a gate stack that insulates the gate stack from an inlaid local interconnect.
  • the mask/insulator is formed contemporaneously with the gate and is self-aligned to the gate.
  • the mask/insulator composed of a non-erodible material, protects the gate from the etch performed defining the conductor image for the local interconnect. Finally, the mask/insulator is retained to function as an overpass insulator during the operation of the circuit.
  • CMOS fabrication process is assumed.
  • the initial topography includes a substrate 10 with a thin oxide layer 25 grown thereon that will eventually function as a gate oxide.
  • a recessed oxide layer 22 which functions as an isolation region, and is selectively grown from thin oxide layer 25.
  • the isolation region could alternatively be formed by shallow trench isolation in which a groove in the substrate is formed and filled with oxide. The oxide is then planarized back, resulting in isolation oxide 24 shown in Fig. 1b.
  • a mask and etch step is next performed.
  • mask 26 is defined and used to create etched region 28 in layer 20 (see Fig. 1c).
  • An insulative layer 30 is then conformally deposited and planarized back using chem-mech polishing ("CMP") or other appropriate means.
  • CMP chem-mech polishing
  • CMP chem-mech polishing
  • Insulative layer 30 is composed of a non-erodible insulative material such as silicon nitride, Si3N4.
  • Overpass insulator 34 is thereby formed, and is coplanar with an upper surface of conductive layer 20 (Fig. 1d).
  • a second mask 32 is then employed to define the gate stack structures (Fig. 1e). These structures result from etching the interim structure of Fig. 1d. Alternative etching techniques are available to produce the stack structures using second mask 32.
  • the exposed areas of overpass insulator 34 could have been etched, followed by an etch of conductive layer 20 with thin oxide layer 25 serving as an etch stop. Given the good etch ratio of polysilicon to the thin oxide etch stop, the differential thickness of the polysilicon layer caused by the first nitride etch should not result in a premature removal of the thin oxide layer.
  • etching conductive layer 20 and thin oxide layer 25 at the same rate could have been employed.
  • Another alternative would be to etch conductive layer 20 to the bottom level of overpass insulator 34, then etch the exposed areas of overpass insulator 34, followed by an etch of the remaining conductive layer 20 to the thin oxide layer 25. This latter etch is complicated but has one advantage in that gate 40, by undergoing a preliminary etch at its upper surface, has an equivalent thickness of polysilicon and no absorption of the subsequent etch is necessary at the etch stop.
  • the semiconductor structure shown in Fig. 1e remains.
  • Mask 32 has been stripped by suitable means. It is important to note that the insulating characteristics of "mask" 34 will prevent electrical contact between gate 36 and a subsequently deposited local interconnect.
  • overpass mask/insulator 34 having been etched simultaneously with gate 36, is self-aligned therewith. Specifically, exposed side edges 29a and 29b of overpass insulator 34 and side surfaces 27a and 27b of gate 36 are aligned. This alignment is significant and results in an overall improvement in the electrical characteristics of the device, as described further below. Note that such alignment is not possible when the mask is formed subsequent to the formation of the gate. Masks formed subsequent to the formation of the gate have a tendency to extend beyond surfaces 27a-27b, thereby affecting the implantation of and connections to diffusions in the substrate.
  • Fig. 1f depicts the semiconductor structure remaining following further processing steps in accordance with the first embodiment. Specifically, spacer material (e.g. silicon oxide) is deposited over the entire structure. The formation of diffusion 49 is initiated using ion implantation. The spacer material and thin oxide layer 25 are etched, thereby forming spacers 42a-42d and gate oxides 44a and 44b. An anneal step is additionally performed to "drive in" the ion implantation, thereby completing the formation of diffusion 49.
  • spacer material e.g. silicon oxide
  • gate silicide 48 and diffusion silicide 50 are preferably formed to facilitate the connection.
  • These silicides can be formed by the deposition of a metal layer (not shown) composed of, for example, titanium, followed by thermal cycling. Silicide forms only where silicon is exposed to the metal layer, i.e., at the upper surface of gate 40 and above diffusion 49.
  • a nitride barrier 46 is then conformally deposited over the entire semiconductor structure to protect the devices from ionic contamination during subsequent processing.
  • the conductive material to comprise the local interconnect (i.e., M0 level wiring) is next deposited and planarized pursuant to the "damascene" techniques described in U.S. Patent No. 4,789,648 to Chow et al., entitled “METHOD FOR PRODUCING COPLANAR MULTI-LEVEL METAL/INSULATOR FILMS ON A SUBSTRATE AND FOR FORMING PATTERNED CONDUCTIVE LINES SIMULTANEOUSLY WITH STUD VIAS,” assigned to the same assignee as the present application, and which is hereby incorporated herein by reference.
  • damascening involves in one example depositing a planarized layer of insulation over a conductive material to which electrical contacts are to be established.
  • etching channels wherein the underlying conductive material is exposed, thereby defining a conductor image.
  • These channels are then overfilled with metallization and planarized with the remaining insulator, thereby forming a local interconnect.
  • gate 36 falls within such a channel, but is nevertheless insulated from the local interconnect.
  • Damascening can be further explained with reference to Figs. 1g and 1h.
  • Insulative layer 52 e.g., composed of sputtered quartz or a composite Si3N4/SiO2 layer (deposited by CVD), is deposited and planarized over the entire semiconductor structure. The elevation of this layer corresponds to the thickness required for the local interconnect.
  • a third mask 54 defined on the planar upper surface of insulative layer 52, facilitates vertical etching of layer 52 and barrier 46. Residual barrier spacers 59a-59d remain on the structures and a cavity is formed surrounding the stacks.
  • the non-erodible characteristics of overpass insulator 34 prevent removal of the overpass insulator and material from gate 36.
  • conductive material 57 which might comprise titanium nitride (TiN), which is followed by CVD tungsten and which functions as an overpass conductor.
  • planarization of conductive material 57 and insulative layer 52 is performed, again using CMP or other suitable techniques.
  • the resultant semiconductor structure shown in Fig. 1h, and fabricated in accordance with this first processing embodiment of the invention, includes local interconnect 57 overpassing gate 36 but electrically contacting other illustrative devices such as gate 40 and diffusion 49.
  • Overpass insulator 34 formed contemporaneously with gate 36, is self-aligned therewith, and the circuit will not suffer from image bias over the gate(s) and diffusion(s).
  • the second embodiment of the invention is a modification of the first processing embodiment and results in stack structures with improved dimensions and functionality.
  • This processing embodiment generally involves the selective formation of conductive and insulative masks within an upper portion of the stack structures, again prior of formation to the stack structures, thereby resulting in self-aligned insulative and conductive masks.
  • Fig. 2a is similar to Fig. 1b described above, except conductive layer 60 has been deposited on conductive layer 20 and a mask 62 has been formed to remove a portion of the layer, resulting in cavity 66 in layer 60 (see Fig. 2b). Insulative layer 64 is then conformally deposited and planarized back using CMP or other appropriate means (Fig. 2c). A combined layer 70 containing at least one section 80 and a remaining portion of layer 60 results.
  • conductive layer 60 could comprise tungsten (W), cobalt (Co) or titanium (Ti).
  • Insulative layer 64 is preferably a non-erodible oxide or nitride. Note that the choice of materials for insulative layer 64 and conductive layer 60 are related. For example, if tungsten is used for layer 60, the remaining portions of the layer serve as an excellent polish stop for an oxide because of its low polish rate.
  • the thickness of combined layer 70 is chosen toaccommodate a thickness of silicide desired on a conducting gate, which is formed in subsequent steps.
  • Fig. 2c depicts the structure following planarization and the definition of a mask 68. An etch is next performed, resulting in the stack structures shown in Fig. 2d. As in the first embodiment, multiple etch sequences are possible, accounting for differing etch rates of the materials involved. In all embodiments, however, the materials of conductive layer 60, insulative layer 64, and conductive layer 20 are etched in the open areas defined by mask 68.Fig. 2d illustrates the resulting stack structures 71 and 73. Conductive mask 74 and overpass insulative mask 72 comprise integral portions of these stack structures.
  • stack structures 71 and 73 have equivalent heights 'X'. As discussed above, precise spacer formation requires devices of equivalent height above an upper surface of the substrate.
  • both conductive mask 74 and insulative mask 72 are formed simultaneously with their respective underlying gates and are therefore aligned to the gates.
  • stack structure 31 in Fig. 1f has a non-aligned gate silicide 48.
  • edges 56a and 56b form irregularly in the area immediately surrounding gate silicide 48, i.e., in contrast to edges 56c and 56d in the area surrounding insulator 34.
  • the pre-formed conductive mask 74 forms gate silicide 75 as shown in Fig. 2e.
  • Silicide 75 is also aligned to the gate, and the formation of silicide 75 is essentially decoupled from the formation of silicide 79, which serves as the ohmic contact for diffusion 77. If contact is only required at gate 40, the formation of silicide 79 can be avoided altogether. Decoupled silicide formations are advantageous in that circuit designers can decrease or even eliminate silicon lost in a silicide reaction near the diffusion. As shown in Fig. 2e, processing of the circuit continues with the addition of spacers and barriers in preparation for the blanket insulation, etch, and formation of inlaid local interconnect as described above in connection with Fig. 1h
  • a third processing embodiment differs from the second embodiment only in how combined layer 70 is formed.
  • the selection of which processing embodiment to use will be based on available etching and planarization technologies.
  • this embodiment changes the "polarity" of the applied masks. Specifically, as shown in Fig. 3a, an insulative layer 78 is formed above conductor 20and mask 76 is defined thereon to preserve a portion of insulative layer 78 roughly in an area above the substrate to encompass a stack structure. Conductive layer 82 in Fig. 3b is then conformally applied and planarized. Identical materials may be used in this embodiment; for example, W, Ti or Co for conductive layer 82 and nitride or oxide for insulative layer 78.
  • mask 84 is defined as shown in Fig. 3c. From this point forward, the fabrication steps would be identical to those of the second embodiment. Note the identity between the resultant structures depicted in Fig. 2c and Fig. 3c. Again, the third embodiment is offered to accommodate different etching and planarization technologies.
  • a fourth processing embodiment of the present invention comprises additional refinements and processing options.
  • overpass masks are still employed and insulative (or conductive) masks remain on selected gates for insulating (or connecting to) the inlaid local interconnect.
  • a substitute material e.g., oxide or nitride
  • this substitute material is selectively wet-etched from the gate and replaced with the desired metal/silicide. Having used a silicon-based material for the substitute material, the planarization, etching and spacer formation can be more easily controlled.
  • insulative layer 88 preferably composed of silicon nitride, is formed on conductive layer 20.
  • a mask 90 is then defined and a cavity 92 is formed in layer 88 after etching (see Fig 4b).
  • Insulative layer 94 conformally applied, is preferably composed of silicon oxide. Planarization is performed, again employing CMP or other appropriate means. The remaining portions of insulative layer 88 serve as an adequate polish stop for insulative layer 94 because of the excellent polish ratio of oxide to nitride.
  • Combined layer 98 results from the planarization, and mask 96 is defined as shown in Fig 4c.
  • stack structures 91 and 93 are defined. Insulative masks 100 and 102 remain.
  • a simpler etch sequence is employed.
  • the sections of combined layer 98 can be etched simultaneously down to conductive layer 20 because the materials are preferably chosen such that the etch can be performed at the same rate, and such that none of layer 20 is etched or an equi-thickness of layer 20 is etched. Therefore, the materials and etches should be chosen to support similar etch ratios to polysilicon and a subsequent, selective wet etch.
  • the nitride and oxide chosen in the preferred embodiment support both requirements.
  • the chosen materials, oxide and nitride can be employed with a CF4 etch in oxygen, combined with an argon ion bombardment. This should result in approximately equivalent etch ratios of the oxide and nitride to polysilicon.
  • a second etch, only of conductive layer 20, is then performed with thin oxide layer 25 serving as the etch stop. No differing thicknesses need be absorbed in the etch.
  • Oxide spacers 106a-106d are formed along the sidewalls of the resultant stack structures 91 and 93 as shown in Fig. 4e.
  • the resultant stack structures are advantageously the same height before spacer formation.
  • mask 100 is now selectively wet-etched, and because the materials are initially chosen for this selective etch, no other materials or structures are affected.
  • Cavity 104 is created and the upper edges of spacers 106a and 106b serve as boundaries for the formation of silicide 116 as shown in Fig. 4f.
  • Silicide 116 because of the spacer boundaries, remains aligned to the underlying gate.
  • Silicide 118 is also formed for diffusion 120.
  • Spacer widths 108a-108d represent the resultant widths of the oxide spacers 106a-106d.
  • Device length 114 is highly dependent on spacer widths 108a-108d. Should a constant device length 114 be required for a certain application, the spacer widths 108a-108d must be equivalent.
  • the presence of gate stacks of equivalent height during formation of oxide spacers 106a-106d guarantees spacer widths that can be tightly controlled. Further, by removing mask 100 and utilizing spacers 106a and 106b, a self-aligned silicide contact, silicide 116, is possible as discussed above.

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EP95480048A 1994-05-19 1995-04-27 Überbrückende Mask/Isolator für lokale Verbindungen und Herstellungsverfahren Withdrawn EP0683514A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/245,997 US5496771A (en) 1994-05-19 1994-05-19 Method of making overpass mask/insulator for local interconnects
US245997 1994-05-19

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EP0683514A1 true EP0683514A1 (de) 1995-11-22

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1008773C2 (nl) * 1998-04-01 1999-10-04 United Microelectronics Corp Werkwijze voor het vervaardigen van zelfuitgerichte lokale verbindingen en contacten.
US7879663B2 (en) 2007-03-08 2011-02-01 Freescale Semiconductor, Inc. Trench formation in a semiconductor material

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06314687A (ja) * 1993-04-30 1994-11-08 Sony Corp 多層配線構造の半導体装置およびその製造方法
US5850096A (en) * 1994-02-25 1998-12-15 Fujitsu Limited Enhanced semiconductor integrated circuit device with a memory array and a peripheral circuit
US5759867A (en) * 1995-04-21 1998-06-02 International Business Machines Corporation Method of making a disposable corner etch stop-spacer for borderless contacts
JPH09129732A (ja) * 1995-10-31 1997-05-16 Nec Corp 半導体装置の製造方法
JP2924763B2 (ja) * 1996-02-28 1999-07-26 日本電気株式会社 半導体装置の製造方法
US5723380A (en) * 1996-03-25 1998-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of approach to improve metal lithography and via-plug integration
JP3607424B2 (ja) * 1996-07-12 2005-01-05 株式会社東芝 半導体装置及びその製造方法
US6309971B1 (en) 1996-08-01 2001-10-30 Cypress Semiconductor Corporation Hot metallization process
US5977638A (en) * 1996-11-21 1999-11-02 Cypress Semiconductor Corp. Edge metal for interconnect layers
US5861676A (en) * 1996-11-27 1999-01-19 Cypress Semiconductor Corp. Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit
US7067406B2 (en) * 1997-03-31 2006-06-27 Intel Corporation Thermal conducting trench in a semiconductor structure and method for forming the same
JP3077630B2 (ja) * 1997-06-05 2000-08-14 日本電気株式会社 半導体装置およびその製造方法
US6057227A (en) * 1997-06-23 2000-05-02 Vlsi Technology, Inc. Oxide etch stop techniques for uniform damascene trench depth
US5953612A (en) * 1997-06-30 1999-09-14 Vlsi Technology, Inc. Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device
US6420273B1 (en) 1997-06-30 2002-07-16 Koninklijke Philips Electronics N.V. Self-aligned etch-stop layer formation for semiconductor devices
US6184083B1 (en) * 1997-06-30 2001-02-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6074921A (en) * 1997-06-30 2000-06-13 Vlsi Technology, Inc. Self-aligned processing of semiconductor device features
US6207543B1 (en) 1997-06-30 2001-03-27 Vlsi Technology, Inc. Metallization technique for gate electrodes and local interconnects
US5807779A (en) * 1997-07-30 1998-09-15 Taiwan Semiconductor Manufacturing Company Ltd. Method of making tungsten local interconnect using a silicon nitride capped self-aligned contact process
US6221704B1 (en) * 1998-06-03 2001-04-24 International Business Machines Corporation Process for fabricating short channel field effect transistor with a highly conductive gate
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6399432B1 (en) 1998-11-24 2002-06-04 Philips Semiconductors Inc. Process to control poly silicon profiles in a dual doped poly silicon process
US6271596B1 (en) 1999-01-12 2001-08-07 Agere Systems Guardian Corp. Damascene capacitors for integrated circuits
TW471116B (en) * 1999-01-22 2002-01-01 United Microelectronics Corp Contact isolation structure and the manufacturing method thereof
US6221708B1 (en) 1999-07-23 2001-04-24 Micron Technology, Inc. Field effect transistor assemblies, integrated circuitry, and methods of forming field effect transistors and integrated circuitry
US6281084B1 (en) * 1999-08-31 2001-08-28 Infineon Technologies Corporation Disposable spacers for improved array gapfill in high density DRAMs
US6614056B1 (en) 1999-12-01 2003-09-02 Cree Lighting Company Scalable led with improved current spreading structures
US6399512B1 (en) 2000-06-15 2002-06-04 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer
US6635566B1 (en) 2000-06-15 2003-10-21 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit
JP2002009149A (ja) * 2000-06-20 2002-01-11 Toshiba Corp 半導体装置およびその製造方法
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6548347B2 (en) * 2001-04-12 2003-04-15 Micron Technology, Inc. Method of forming minimally spaced word lines
US20020155261A1 (en) * 2001-04-24 2002-10-24 Sung-Hsiung Wang Method for forming interconnect structure with low dielectric constant
US7615829B2 (en) * 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
WO2003105206A1 (en) * 2002-06-10 2003-12-18 Amberwave Systems Corporation Growing source and drain elements by selecive epitaxy
US6982474B2 (en) * 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
WO2004081982A2 (en) * 2003-03-07 2004-09-23 Amberwave Systems Corporation Shallow trench isolation process
JP4610205B2 (ja) * 2004-02-18 2011-01-12 株式会社リコー 半導体装置
US7910418B2 (en) * 2008-01-30 2011-03-22 International Business Machines Corporation Complementary metal gate dense interconnect and method of manufacturing
US9817822B2 (en) * 2008-02-07 2017-11-14 International Business Machines Corporation Managing white space in a portal web page
US8791017B2 (en) 2011-10-26 2014-07-29 Globalfoundries Inc. Methods of forming conductive structures using a spacer erosion technique
US9330983B1 (en) 2015-02-16 2016-05-03 International Business Machines Corporation CMOS NFET and PFET comparable spacer width

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4180826A (en) * 1978-05-19 1979-12-25 Intel Corporation MOS double polysilicon read-only memory and cell
EP0224013A2 (de) * 1985-10-28 1987-06-03 International Business Machines Corporation Verfahren zur Herstellung koplanarer Viellagen-Metall-Isolator-Schichten auf einem Substrat
US4808552A (en) * 1985-09-11 1989-02-28 Texas Instruments Incorporated Process for making vertically-oriented interconnections for VLSI devices
EP0416287A2 (de) * 1989-09-05 1991-03-13 Texas Instruments Incorporated Verfahren zur Erzeugung von Ortsverbindungen mit Gebrauch von selektiv Anisotropie

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662353A (en) * 1979-10-29 1981-05-28 Toshiba Corp Semiconductor device and its manufacturing method
FR2525389A1 (fr) * 1982-04-14 1983-10-21 Commissariat Energie Atomique Procede de positionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre
US4944836A (en) * 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
US4922311A (en) * 1987-12-04 1990-05-01 American Telephone And Telegraph Company Folded extended window field effect transistor
US4933743A (en) * 1989-03-11 1990-06-12 Fairchild Semiconductor Corporation High performance interconnect system for an integrated circuit
US5087584A (en) * 1990-04-30 1992-02-11 Intel Corporation Process for fabricating a contactless floating gate memory array utilizing wordline trench vias
US5308783A (en) * 1992-12-16 1994-05-03 Siemens Aktiengesellschaft Process for the manufacture of a high density cell array of gain memory cells
US5541427A (en) * 1993-12-03 1996-07-30 International Business Machines Corporation SRAM cell with capacitor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4180826A (en) * 1978-05-19 1979-12-25 Intel Corporation MOS double polysilicon read-only memory and cell
US4808552A (en) * 1985-09-11 1989-02-28 Texas Instruments Incorporated Process for making vertically-oriented interconnections for VLSI devices
EP0224013A2 (de) * 1985-10-28 1987-06-03 International Business Machines Corporation Verfahren zur Herstellung koplanarer Viellagen-Metall-Isolator-Schichten auf einem Substrat
EP0416287A2 (de) * 1989-09-05 1991-03-13 Texas Instruments Incorporated Verfahren zur Erzeugung von Ortsverbindungen mit Gebrauch von selektiv Anisotropie

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1008773C2 (nl) * 1998-04-01 1999-10-04 United Microelectronics Corp Werkwijze voor het vervaardigen van zelfuitgerichte lokale verbindingen en contacten.
US7879663B2 (en) 2007-03-08 2011-02-01 Freescale Semiconductor, Inc. Trench formation in a semiconductor material

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JP3245004B2 (ja) 2002-01-07
US5677563A (en) 1997-10-14
KR950034612A (ko) 1995-12-28
JPH0864822A (ja) 1996-03-08
US5496771A (en) 1996-03-05
KR100187870B1 (ko) 1999-06-01

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