EP0665560B1 - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device Download PDF

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Publication number
EP0665560B1
EP0665560B1 EP94119166A EP94119166A EP0665560B1 EP 0665560 B1 EP0665560 B1 EP 0665560B1 EP 94119166 A EP94119166 A EP 94119166A EP 94119166 A EP94119166 A EP 94119166A EP 0665560 B1 EP0665560 B1 EP 0665560B1
Authority
EP
European Patent Office
Prior art keywords
circuit carrier
resistive layer
circuit
ceramic
ceramic strip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP94119166A
Other languages
German (de)
French (fr)
Other versions
EP0665560A3 (en
EP0665560A2 (en
Inventor
Karl-Gerd Dipl.-Ing. Drekmeier (Fh)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TE Connectivity Solutions GmbH
Original Assignee
Tyco Electronics Logistics AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tyco Electronics Logistics AG filed Critical Tyco Electronics Logistics AG
Publication of EP0665560A2 publication Critical patent/EP0665560A2/en
Publication of EP0665560A3 publication Critical patent/EP0665560A3/en
Application granted granted Critical
Publication of EP0665560B1 publication Critical patent/EP0665560B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/01—Mounting; Supporting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/08—Cooling, heating or ventilating arrangements
    • H01C1/084—Cooling, heating or ventilating arrangements using self-cooling, e.g. fins, heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a hybrid circuit arrangement according to the preamble of claim 1, as is known for example from US-A-4 719 443.
  • Electrical circuits with integrated resistors which are used, for example, as series resistors in public telephone exchanges, are usually manufactured using thick-film or thin-film technology. In practice, such layer circuits should be able to withstand short-term large electrical outputs, such as occur in connection with network faults.
  • the object of the present invention is to create a hybrid circuit arrangement of the type mentioned at the outset which has a considerably increased short-term load and which additionally prevents fragmentation, even under higher loads.
  • FIG. 7 shows the load capacity of a known circuit carrier in comparison to a circuit carrier provided according to the invention with a ceramic strip as a function of the Time shown. What is important for the application is above all the large difference in the short-term range, that is to say around 0.1 sec. An even higher load then leads to the interruption of the conductor tracks or layer resistances due to cracks in the layers or in the circuit carrier. However, the ceramic strip holding the torn circuit carrier together from at least one side prevents the formation of fragments.
  • circuit carrier 1 shows a circuit carrier 1 with, for example, film resistors 2 applied on both sides and meandering. The two layer sides are connected via plated-through holes 3.
  • the external connection 4 is designed in a single-in-line (SIL) version.
  • a ceramic strip 6 of circuit carrier thickness is fastened on the back with a heat-conducting adhesive 5.
  • the embodiment shown in FIG. 1, which corresponds to the diagram in FIG. 7, is particularly cost-effective.
  • FIG. 2 shows an embodiment with a dual-in-line connection version 7 and an additional changeover via a connection comb 8.
  • the backside ceramic 6 is somewhat smaller than the circuit 1, so that the edge of the circuit carrier 1 extends beyond the surface of the ceramic strip 6 and can be contacted there by means of the connecting combs 8.
  • a thermal fuse 10 is shown, which interrupts the electrical voltage of the circuit arrangement when the long-term load is too great.
  • the thermal fuse 10 is designed in a manner known per se so that the previously treated network faults are too short to cause the fuse to melt or unsolder.
  • the thermal fuse 10 is designed in such a way that it triggers with a long-term load of approximately 600 V and interrupts the circuit arrangement electrically.
  • FIG. 3 shows a SIL design with heat-relief ceramic strips 6 applied on both sides.
  • FIGS. 5 and 6 each show the configuration of the external connections 4 as a known, technically advantageous stand aid, as can be used in all configurations of the invention.
  • FIG. 5 shows a resistance layer 2 applied flat between conductor tracks 11 and 12 extending parallel to the longitudinal direction of the circuit carrier 1, the connection surfaces 13 for the external connections 4 being arranged on a longitudinal side of the circuit carrier 1.
  • the contacting of the sheet resistors 2 shown at the connection 13 and opposite 14 is advantageous since the circuit 15 is deliberately interrupted when the circuit carrier 1 breaks due to a too high short-term load, which causes an immediate shutdown of the thermal or electrical overload for the module.
  • FIG. 6 shows an embodiment in which the resistance layer 2 is meandered and has diversions 16 with considerably lower surface resistance on the curves. This serves to ensure the necessary surge voltage resistance of more than 1 kV.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Developers In Electrophotography (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

Hybrid switching arrangement has a resistance layer applied on one side of plate-like substrate made of glass or ceramic. A ceramic strip (6) is applied on one side of the substrate (1). Pref. the ceramic strip (6) is made of aluminium oxide, beryllium oxide or aluminium nitride, and is secured using heat conducting adhesive. The substrate (1) and strip (6) are both made of aluminium oxide and are both 1mm thick. The ceramic strip is at most 0.5 (pref. 0.1)mm thick.

Description

Die Erfindung betrifft eine Hybridschaltungsanordnung nach dem Oberbegriff des Anspruchs 1, wie sie beispielsweise aus der US-A-4 719 443 bekannt ist.The invention relates to a hybrid circuit arrangement according to the preamble of claim 1, as is known for example from US-A-4 719 443.

Elektrische Schaltkreise mit integrierten Widerstanden, die beispielsweise als Vorwiderstände in öffentlichen Telefonvermittlungs-Anlagen eingesetzt werden, werden üblicherweise in Dickschicht- oder Dünnfilmtechnik hergestellt. Derartige Schichtschaltungen sollen in der Praxis mit kurzzeitigen großen elektrischen Leistungen belastbar sein, wie sie insbesondere im Zusammenhang mit Netzstörungen auftreten.Electrical circuits with integrated resistors, which are used, for example, as series resistors in public telephone exchanges, are usually manufactured using thick-film or thin-film technology. In practice, such layer circuits should be able to withstand short-term large electrical outputs, such as occur in connection with network faults.

Bekannte, bereits auf dem Markt erhältliche Schichtschaltungen mit einem ca. 1 mm dicken Al2O3-Substrat mit beidseitig aufgebrachter Widerstandsschicht können mit ca. 2 kW, 100 ms belastet werden, danach entsteht ein Substratbruch. Dabei ist nicht nur die relativ geringe Kurzzeitbelastbarkeit, sondern auch die bisher beim Bruch auftretende Fragmentbildung problematisch, da sie zu unkontrolliert in der Baugruppe sich verteilenden, ggf. sogar leitenden Splittern führt.Known layer circuits already available on the market with an approximately 1 mm thick Al 2 O 3 substrate with a resistance layer applied on both sides can be loaded with approximately 2 kW, 100 ms, after which a substrate breakage occurs. Not only the relatively low short-term load-bearing capacity is problematic, but also the fragment formation that has previously occurred during breakage, since it leads to splinters which are distributed in the assembly in an uncontrolled manner, and possibly even lead to splinters.

Aufgabe der vorliegenden Erfindung ist es, eine Hybridschaltungsanordnung der eingangs genannten Art zu schaffen, die eine erheblich vergrößerte Kurzzeitlast aufweist, und bei der zusätzlich, bei noch höheren Belastungen, eine Fragmentbildung verhindert ist.The object of the present invention is to create a hybrid circuit arrangement of the type mentioned at the outset which has a considerably increased short-term load and which additionally prevents fragmentation, even under higher loads.

Erfindungsgemäß wird dies durch die kennzeichnenden Merkmale des Anspruchs 1 erreicht.According to the invention this is achieved by the characterizing features of claim 1.

Durch einen beispielsweise rückseitig auf einen Al2O3-Schaltungsträger von 1 mm Dicke aufgeklebten Keramikstreifen aus dem gleichen Material und mit etwa gleicher Dicke gelingt es, die Kurzzeitlast der Schichtschaltung ohne Änderung der eigentlichen Schaltung nahezu zu verdoppeln. Während die primäre Funktion des Keramikstreifens in der Bereitstellung zusätzlicher Warmekapazität liegt, muß bei der Auswahl des Materials weiterhin auf ein ähnliches thermisches Ausdehnungsverhalten wie beim Schaltungsträger geachtet werden. Darüber hinaus kann die Funktion einer Wärmesenke im Kurzzeitbereich nur durch Keramikmaterialien mit hoher Wärmeleitfähigkeit erfüllt werden. Um Durchschläge zu vermeiden, ist ferner auf die Isoliereigenschaften zu achten. Versuche, die Wärmekapazität unmittelbar durch Vergrößerung der Dicke des Schaltungsträgers selbst zu erhöhen, führten nur in engen Grenzen zum Erfolg, da im Rahmen der Standardschichttechnik Bearbeitungsschwierigkeiten, beispielsweise beim Durchkontaktieren, auftraten.A ceramic strip made of the same material and with approximately the same thickness and glued to the back of an Al 2 O 3 circuit carrier of 1 mm thickness, for example, almost doubles the short-term load of the layer circuit without changing the actual circuit. While the primary function of the ceramic strip is to provide additional heat capacity, the thermal expansion behavior similar to that of the circuit carrier must also be taken into account when selecting the material. In addition, the function of a heat sink in the short-term range can only be fulfilled by ceramic materials with high thermal conductivity. In order to avoid breakdowns, the insulation properties must also be observed. Attempts to increase the heat capacity itself directly by increasing the thickness of the circuit carrier only led to success within narrow limits, since processing difficulties, for example through-contacting, occurred in the context of the standard layer technology.

Weitere Ausgestaltungen der Erfindung sind in den Unteransprüchen gekennzeichnet. Die Erfindung wird nachfolgend an Ausführungsbeispielen anhand der Figuren der Zeichnung näher erläutert. Es zeigen

FIG 1 bis 3
drei verschiedene Ausgestaltungen einer erfindungsgemäßen Hybridschaltungsanordnung, jeweils in Seitenansicht,
Figur 4
entfällt
FIG 5 und 6
in seitlicher Draufsicht zwei weitere Ausgestaltungen der Erfindung,
FIG 7
die gegen die Zeit aufgetragenen Belastbarkeitskurven einer bekannten und einer erfindungsgemäßen Schichtschaltung.
Further developments of the invention are characterized in the subclaims. The invention is explained in more detail below using exemplary embodiments with reference to the figures of the drawing. Show it
1 to 3
three different configurations of a hybrid circuit arrangement according to the invention, each in side view,
Figure 4
not applicable
5 and 6
in side plan view two further embodiments of the invention,
FIG 7
the load capacity curves plotted against time of a known and a layer circuit according to the invention.

In FIG 7 ist die Belastbarkeit eines bekannten Schaltungsträgers im Vergleich zu einem erfindungsgemäß mit einem Keramikstreifen versehenen Schaltungsträger in Abhängigkeit von der Zeit dargestellt. Wichtig für die Anwendung ist vor allem der große Unterschied im Kurzzeitbereich, also bei etwa 0,1 sec. Eine noch höhere Belastung fuhrt dann zwar zur Unterbrechung der Leiterbahnen bzw. Schichtwiderstände durch Risse in den Schichten oder im Schaltungsträger. Der den gerissenen Schaltungsträger mindestens von einer Seite her zusammenhaltende Keramikstreifen verhindert jedoch eine Fragmentbildung.FIG. 7 shows the load capacity of a known circuit carrier in comparison to a circuit carrier provided according to the invention with a ceramic strip as a function of the Time shown. What is important for the application is above all the large difference in the short-term range, that is to say around 0.1 sec. An even higher load then leads to the interruption of the conductor tracks or layer resistances due to cracks in the layers or in the circuit carrier. However, the ceramic strip holding the torn circuit carrier together from at least one side prevents the formation of fragments.

In FIG 1 ist ein Schaltungsträger 1 mit beispielsweise beidseitig aufgebrachten Schichtwiderstanden 2, die mäandriert sind, dargestellt. Die Verbindung der beiden Schichtseiten erfolgt über Durchkontaktierungen 3. Der Außenanschluß 4 ist in Single-in-Line(SIL)-Version ausgeführt. Rückseitig ist ein Keramikstreifen 6 in Schaltungsträgerdicke mit einem Wärmeleitkleber 5 befestigt. Die in FIG 1 dargestellte Ausfuhrung, die dem Diagramm gemäß FIG 7 entspricht, ist besonders kostengünstig.1 shows a circuit carrier 1 with, for example, film resistors 2 applied on both sides and meandering. The two layer sides are connected via plated-through holes 3. The external connection 4 is designed in a single-in-line (SIL) version. A ceramic strip 6 of circuit carrier thickness is fastened on the back with a heat-conducting adhesive 5. The embodiment shown in FIG. 1, which corresponds to the diagram in FIG. 7, is particularly cost-effective.

In FIG 2 ist eine Ausfuhrung mit Dual-in-Line-Anschlußversion 7 und einer zusätzlichen Umkontaktierung durch einen Anschlußkamm 8 dargestellt. Die Ruckseitenkeramik 6 ist etwas kleiner als der Schaltkreis 1, so daß der Schaltungstrager 1 mit seinem Randbereich über die Fläche des Keramikstreifens 6 hinaussteht und dort mittels der Anschlußkämme 8 kontaktierbar ist. Ferner ist eine Thermosicherung 10 dargestellt, die bei zu großer Langzeitbelastung die elektrische Spannung der Schaltungsanordnung unterbricht. Die Thermosicherung 10 ist in an sich bekannter Weise so ausgebildet, daß die zuvorbehandelten Netzstörungen zu kurz sind, um zu einem Schmelzen bzw. Auslöten der Sicherung zu führen. Andererseits ist die Thermosicherung 10 so ausgelegt, daß sie bereits bei einer Langzeitbelastung mit etwa 600 V auslöst und die Schaltungsanordnung elektrisch unterbricht.FIG. 2 shows an embodiment with a dual-in-line connection version 7 and an additional changeover via a connection comb 8. The backside ceramic 6 is somewhat smaller than the circuit 1, so that the edge of the circuit carrier 1 extends beyond the surface of the ceramic strip 6 and can be contacted there by means of the connecting combs 8. Furthermore, a thermal fuse 10 is shown, which interrupts the electrical voltage of the circuit arrangement when the long-term load is too great. The thermal fuse 10 is designed in a manner known per se so that the previously treated network faults are too short to cause the fuse to melt or unsolder. On the other hand, the thermal fuse 10 is designed in such a way that it triggers with a long-term load of approximately 600 V and interrupts the circuit arrangement electrically.

In FIG 3 ist eine SIL-Ausführung mit beidseitig aufgebrachten Wärmeentlastungs-Keramikstreifen 6 dargestellt. Mit dieser Ausführung ist eine weitere Erhöhung der Kurzzeit-Belastbarkeit möglich, wobei für eine eventuelle Thermosicherung eine Ausnehmung im jeweiligen Keramikstreifen 6 vorzusehen ist.FIG. 3 shows a SIL design with heat-relief ceramic strips 6 applied on both sides. With this design, a further increase in the short-term load capacity is possible, a recess in the respective ceramic strip 6 being provided for a possible thermal fuse.

FIG 5 und 6 zeigt jeweils die Ausgestaltung der Außenanschlüsse 4 als eine an sich bekannte, fertigungstechnisch günstige Standhilfe, wie sie bei allen Ausgestaltungen der Erfindung Verwendung finden kann. In FIG 5 ist eine flächig zwischen sich parallel zur Längsrichtung des Schaltungsträgers 1 erstreckende Leiterbahnen 11 und 12 aufgebrachte Widerstandsschicht 2 dargestellt, wobei die Anschlußflächen 13 für die Außenanschlüsse 4 an einer Längsseite des Schaltungsträgers 1 angeordnet sind. Die dargestellte Kontaktierung der Schichtwiderstände 2 am Anschluß 13 und gegenüberliegend 14 ist vorteilhaft, da absichtlich beim Bruch des Schaltungsträgers 1 durch eine zu hohe Kurzzeitbelastung die Leiterbahn 15 unterbrochen wird, was eine sofortige Abschaltung der thermischen bzw. elektrischen Überlast für die Baugruppe bewirkt. In FIG 6 ist eine Ausführung dargestellt, in der die Widerstandsschicht 2 mäandriert ist und an den Kurven Umleitungen 16 mit erheblich geringerem Flächenwiderstand aufweist. Dies dient zur Absicherung der notwendigen Stoßspannungsfestigkeit von mehr als 1 kV.FIGS. 5 and 6 each show the configuration of the external connections 4 as a known, technically advantageous stand aid, as can be used in all configurations of the invention. FIG. 5 shows a resistance layer 2 applied flat between conductor tracks 11 and 12 extending parallel to the longitudinal direction of the circuit carrier 1, the connection surfaces 13 for the external connections 4 being arranged on a longitudinal side of the circuit carrier 1. The contacting of the sheet resistors 2 shown at the connection 13 and opposite 14 is advantageous since the circuit 15 is deliberately interrupted when the circuit carrier 1 breaks due to a too high short-term load, which causes an immediate shutdown of the thermal or electrical overload for the module. FIG. 6 shows an embodiment in which the resistance layer 2 is meandered and has diversions 16 with considerably lower surface resistance on the curves. This serves to ensure the necessary surge voltage resistance of more than 1 kV.

Claims (4)

  1. Hybrid circuit arrangement for series resistors in telephone switching installations having a resistive layer which is mounted on at least one side of a board-like circuit carrier made of ceramic, at least one side of the circuit carrier (1) having a ceramic strip (6), with virtually the same surface area, attached to it so that there is good thermal conduction, characterized in that the resistive layer (2) has a meander shape, in that the circuit carrier (1) holds a thermal protection device (10) which is electrically connected to the resistive layer (2), in that the circuit carrier (1) and the ceramic strip (6) are both made of alumina and both have an approximate thickness of 1 mm, and in that the ceramic strip (6) is attached by means of thermally conductive adhesive (5), the ceramic strip (6) forming a heat sink for the heat produced by the resistive layer (2) in the event of the circuit having a short-term load in the kilowatt range, and holding the circuit carrier (1) together and preventing fragment formation in the event of said circuit carrier breaking.
  2. Hybrid circuit arrangement according to Claim 1, characterized in that the bends in the resistive layer (2) have diversions (16) with a significantly lower sheet resistance.
  3. Hybrid circuit arrangement according to one of Claims 1 and 2, characterized in that the resistive layer (2) is applied flat between conductor tracks (11, 12) which extend parallel to the longitudinal direction of the circuit carrier (1), one longitudinal side of the circuit carrier (1) having connection areas (13) arranged on it.
  4. Hybrid circuit arrangement according to one of Claims 1 to 3, characterized in that the resistive layer (2) is connected via conductor tracks (15) to connection areas (13) arranged in the edge region of the circuit carrier (1), and this edge region protrudes beyond the surface area of the ceramic strip (6) and can have contact made with it by means of connection combs.
EP94119166A 1993-12-17 1994-12-05 Hybrid integrated circuit device Expired - Lifetime EP0665560B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE9319473U 1993-12-17
DE9319473U DE9319473U1 (en) 1993-12-17 1993-12-17 Hybrid circuit arrangement

Publications (3)

Publication Number Publication Date
EP0665560A2 EP0665560A2 (en) 1995-08-02
EP0665560A3 EP0665560A3 (en) 1997-05-02
EP0665560B1 true EP0665560B1 (en) 2000-04-05

Family

ID=6902186

Family Applications (1)

Application Number Title Priority Date Filing Date
EP94119166A Expired - Lifetime EP0665560B1 (en) 1993-12-17 1994-12-05 Hybrid integrated circuit device

Country Status (4)

Country Link
US (1) US5581227A (en)
EP (1) EP0665560B1 (en)
AT (1) ATE191581T1 (en)
DE (2) DE9319473U1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5914648A (en) 1995-03-07 1999-06-22 Caddock Electronics, Inc. Fault current fusing resistor and method
JP2002507329A (en) 1997-07-01 2002-03-05 シーメンス アクチエンゲゼルシヤフト Hybrid circuit device with overload protection circuit function
DE19814445C1 (en) * 1998-03-31 1999-06-24 Siemens Ag Hybrid circuit arrangement
US6404324B1 (en) * 1999-09-07 2002-06-11 General Motors Corporation Resistive component for use with short duration, high-magnitude currents

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3792383A (en) * 1971-06-21 1974-02-12 Motorola Inc Hybrid strip transmission line circuitry and method of making same
US3766440A (en) * 1972-08-11 1973-10-16 Gen Motors Corp Ceramic integrated circuit convector assembly
US4297670A (en) * 1977-06-03 1981-10-27 Angstrohm Precision, Inc. Metal foil resistor
LU83439A1 (en) * 1980-09-25 1981-10-29 Siemens Ag HOUSELESS, VERTICAL PLUG-IN SINGLE-IN-LINE SWITCHING MODULE
US4494104A (en) * 1983-07-18 1985-01-15 Northern Telecom Limited Thermal Fuse
DE3444699A1 (en) * 1984-12-07 1986-06-19 Telefunken electronic GmbH, 7100 Heilbronn ELECTRICAL POWER COMPONENT
US4719443A (en) * 1986-04-03 1988-01-12 General Electric Company Low capacitance power resistor using beryllia dielectric heat sink layer and low toxicity method for its manufacture
DE3837974A1 (en) * 1988-11-09 1990-05-10 Telefunken Electronic Gmbh ELECTRONIC CONTROL UNIT
US5003429A (en) * 1990-07-09 1991-03-26 International Business Machines Corporation Electronic assembly with enhanced heat sinking
US5254969A (en) * 1991-04-02 1993-10-19 Caddock Electronics, Inc. Resistor combination and method
ES2103341T3 (en) * 1991-04-10 1997-09-16 Caddock Electronics Inc FILM TYPE RESISTOR.
US5304977A (en) * 1991-09-12 1994-04-19 Caddock Electronics, Inc. Film-type power resistor combination with anchored exposed substrate/heatsink
DE4234022C2 (en) * 1992-10-09 1995-05-24 Telefunken Microelectron Layer circuit with at least one power resistor

Also Published As

Publication number Publication date
DE59409274D1 (en) 2000-05-11
US5581227A (en) 1996-12-03
ATE191581T1 (en) 2000-04-15
DE9319473U1 (en) 1994-06-23
EP0665560A3 (en) 1997-05-02
EP0665560A2 (en) 1995-08-02

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