EP0665560A2 - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device Download PDF

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Publication number
EP0665560A2
EP0665560A2 EP94119166A EP94119166A EP0665560A2 EP 0665560 A2 EP0665560 A2 EP 0665560A2 EP 94119166 A EP94119166 A EP 94119166A EP 94119166 A EP94119166 A EP 94119166A EP 0665560 A2 EP0665560 A2 EP 0665560A2
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EP
European Patent Office
Prior art keywords
arrangement according
circuit carrier
circuit arrangement
ceramic
ceramic strip
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP94119166A
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German (de)
French (fr)
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EP0665560A3 (en
EP0665560B1 (en
Inventor
Karl-Gerd Dipl.-Ing. Drekmeier (Fh)
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TE Connectivity Solutions GmbH
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Siemens AG
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Publication of EP0665560A2 publication Critical patent/EP0665560A2/en
Publication of EP0665560A3 publication Critical patent/EP0665560A3/en
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Publication of EP0665560B1 publication Critical patent/EP0665560B1/en
Anticipated expiration legal-status Critical
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C1/00Details
    • H01C1/01Mounting; Supporting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C1/00Details
    • H01C1/08Cooling, heating or ventilating arrangements
    • H01C1/084Cooling, heating or ventilating arrangements using self-cooling, e.g. fins, heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a hybrid circuit arrangement with a resistance layer applied at least on one side to a plate-shaped circuit carrier made of glass or ceramic.
  • Electrical circuits with integrated resistors which are used, for example, as series resistors in public telephone exchanges, are usually manufactured using thick-film or thin-film technology. In practice, such layer circuits should be able to withstand short-term large electrical outputs, such as occur in connection with network faults.
  • the object of the present invention is to create a hybrid circuit arrangement of the type mentioned at the outset which has a considerably increased short-term load and which additionally prevents fragmentation, even under higher loads.
  • this is achieved in that a ceramic strip of at least almost the same size surface is attached in a good heat-conducting manner on at least one side of the circuit carrier (substrate).
  • a ceramic strip made of the same material and with approximately the same thickness and glued onto the back of an Al2O3 circuit carrier of 1 mm thickness succeeds in almost doubling the short-term load of the layer circuit without changing the actual circuit. While the primary function of the ceramic strip is to provide additional heat capacity, the thermal expansion behavior similar to that of the circuit carrier must also be taken into account when selecting the material. In addition, the function of a heat sink in the short-term range can only be fulfilled by ceramic materials with high thermal conductivity. In order to avoid breakdowns, the insulation properties must also be observed. Attempts to increase the heat capacity directly by increasing the thickness of the circuit carrier itself have only been successful within narrow limits, since processing difficulties, for example through-contacting, occurred as part of the standard layer technology.
  • FIG. 7 shows the load capacity of a known circuit carrier in comparison with a circuit carrier provided according to the invention with a ceramic strip as a function of the Time shown. What is important for the application is above all the large difference in the short-term range, that is to say at about 0.1 sec. An even higher load then leads to the interruption of the conductor tracks or layer resistances due to cracks in the layers or in the circuit carrier. However, the ceramic strip holding the torn circuit carrier together from at least one side prevents the formation of fragments.
  • circuit carrier 1 shows a circuit carrier 1 with, for example, film resistors 2 applied on both sides, which may be full-surface or meandered.
  • the two layer sides are connected via plated-through holes 3.
  • the external connection 4 is designed in a single-in-line (SIL) version.
  • a ceramic strip 6 of circuit carrier thickness is fastened on the back with a heat-conducting adhesive 5.
  • the embodiment shown in FIG. 1, which corresponds to the diagram in FIG. 7, is particularly cost-effective.
  • the short-term load can be further improved by making the ceramic strip 6 thicker and / or consisting of beryllium oxide or aluminum nitride ceramic.
  • FIG. 2 shows an embodiment with a dual-in-line connection version 7 and an additional contact changeover through a connection comb 8.
  • the backside ceramic 6 is considerably thicker than the circuit carrier 1 and also somewhat smaller than this, so that the circuit carrier 1 projects with its edge region beyond the surface of the ceramic strip 6 and can be contacted there by means of the connecting combs 8.
  • a thermal fuse 10 is shown, which interrupts the electrical voltage of the circuit arrangement when the long-term load is too great.
  • the thermal fuse 10 is designed in a manner known per se so that the previously treated network faults are too short to cause the fuse to melt or unsolder.
  • the thermal fuse 10 is designed in such a way that it triggers with a long-term load of approximately 600 V and electrically interrupts the circuit arrangement.
  • FIG. 3 shows a SIL design with heat-relief ceramic strips 6 applied on both sides.
  • SIL design with heat-relief ceramic strips 6 applied on both sides.
  • FIG. 4 shows a further increase in the short-term load capacity is possible, a recess in the respective ceramic strip 6 being provided for a possible thermal fuse.
  • FIG. 4 Another embodiment of the invention is shown in FIG. 4.
  • the ceramic strip 6 is at most 0.5, but preferably only about 0.1 mm thick. However, it is supplemented by a metal profile, for example made of copper or aluminum, which is fastened in a well heat-conducting manner on its side facing away from the circuit carrier 1.
  • FIGS. 5 and 6 each show the configuration of the external connections 4 as a known, technically advantageous stand aid, as can be used in all configurations of the invention.
  • FIG. 5 shows a resistance layer 2 applied flat between conductor tracks 11 and 12 extending parallel to the longitudinal direction of the circuit carrier 1, the connection surfaces 13 for the external connections 4 being arranged on a longitudinal side of the circuit carrier 1.
  • the contacting of the sheet resistors 2 shown at the connection 13 and opposite 14 is advantageous since the circuit 15 is deliberately interrupted when the circuit carrier 1 breaks due to a too high short-term load, which causes an immediate shutdown of the thermal or electrical overload for the module.
  • FIG. 6 shows an embodiment in which the resistance layer 2 is meandered and has diversions 16 with considerably lower surface resistance on the curves. This serves to ensure the necessary surge voltage resistance of more than 1 kV.

Abstract

Hybrid switching arrangement has a resistance layer applied on one side of plate-like substrate made of glass or ceramic. A ceramic strip (6) is applied on one side of the substrate (1). Pref. the ceramic strip (6) is made of aluminium oxide, beryllium oxide or aluminium nitride, and is secured using heat conducting adhesive. The substrate (1) and strip (6) are both made of aluminium oxide and are both 1mm thick. The ceramic strip is at most 0.5 (pref. 0.1)mm thick.

Description

Die Erfindung betrifft eine Hybridschaltungsanordnung mit einer mindestens einseitig auf einem plattenförmigen Schaltungsträger aus Glas oder Keramik aufgebrachten Widerstandsschicht.The invention relates to a hybrid circuit arrangement with a resistance layer applied at least on one side to a plate-shaped circuit carrier made of glass or ceramic.

Elektrische Schaltkreise mit integrierten Widerstanden, die beispielsweise als Vorwiderstände in öffentlichen Telefonvermittlungs-Anlagen eingesetzt werden, werden üblicherweise in Dickschicht- oder Dünnfilmtechnik hergestellt. Derartige Schichtschaltungen sollen in der Praxis mit kurzzeitigen großen elektrischen Leistungen belastbar sein, wie sie insbesondere im Zusammenhang mit Netzstörungen auftreten.Electrical circuits with integrated resistors, which are used, for example, as series resistors in public telephone exchanges, are usually manufactured using thick-film or thin-film technology. In practice, such layer circuits should be able to withstand short-term large electrical outputs, such as occur in connection with network faults.

Bekannte, bereits auf dem Markt erhältliche Schichtschaltungen mit einem ca. 1 mm dicken Al₂O₃-Substrat mit beidseitig aufgebrachter Widerstandsschicht können mit ca. 2 kW, 100 ms belastet werden, danach entsteht ein Substratbruch. Dabei ist nicht nur die relativ geringe Kurzzeitbelastbarkeit, sondern auch die bisher beim Bruch auftretende Fragmentbildung problematisch, da sie zu unkontrolliert in der Baugruppe sich verteilenden, ggf. sogar leitenden Splittern führt.Known layer circuits already available on the market with an approximately 1 mm thick Al₂O₃ substrate with a resistance layer applied on both sides can be loaded with approximately 2 kW, 100 ms, after which a substrate breakage occurs. Not only the relatively low short-term load-bearing capacity is problematic, but also the fragment formation that has previously occurred in the event of breakage, since it leads to splinters which are distributed in the assembly in an uncontrolled manner, and possibly even conductively.

Aufgabe der vorliegenden Erfindung ist es, eine Hybridschaltungsanordnung der eingangs genannten Art zu schaffen, die eine erheblich vergrößerte Kurzzeitlast aufweist, und bei der zusätzlich, bei noch höheren Belastungen, eine Fragmentbildung verhindert ist.The object of the present invention is to create a hybrid circuit arrangement of the type mentioned at the outset which has a considerably increased short-term load and which additionally prevents fragmentation, even under higher loads.

Erfindungsgemäß wird dies dadurch erreicht, daß auf mindestens einer Seite des Schaltungsträgers (Substrat) ein Keramikstreifen von mindestens nahezu gleichgroßer Fläche in gut wärmeleitender Weise befestigt ist.According to the invention, this is achieved in that a ceramic strip of at least almost the same size surface is attached in a good heat-conducting manner on at least one side of the circuit carrier (substrate).

Durch einen beispielsweise rückseitig auf einen Al₂O₃-Schaltungsträger von 1 mm Dicke aufgeklebten Keramikstreifen aus dem gleichen Material und mit etwa gleicher Dicke gelingt es, die Kurzzeitlast der Schichtschaltung ohne Änderung der eigentlichen Schaltung nahezu zu verdoppeln. Während die primäre Funktion des Keramikstreifens in der Bereitstellung zusätzlicher Warmekapazität liegt, muß bei der Auswahl des Materials weiterhin auf ein ähnliches thermisches Ausdehnungsverhalten wie beim Schaltungsträger geachtet werden. Darüber hinaus kann die Funktion einer Wärmesenke im Kurzzeitbereich nur durch Keramikmaterialien mit hoher Wärmeleitfähigkeit erfüllt werden. Um Durchschläge zu vermeiden, ist ferner auf die Isoliereigenschaften zu achten. Versuche, die Wärmekapazität unmittelbar durch Vergrößerung der Dicke des Schaltungsträgers selbst zu erhöhen, führten nur in engen Grenzen zum Erfolg, da im Rahmen der Standardschichttechnik Bearbeitungsschwierigkeiten, beispielsweise beim Durchkontaktieren, auftraten.For example, a ceramic strip made of the same material and with approximately the same thickness and glued onto the back of an Al₂O₃ circuit carrier of 1 mm thickness succeeds in almost doubling the short-term load of the layer circuit without changing the actual circuit. While the primary function of the ceramic strip is to provide additional heat capacity, the thermal expansion behavior similar to that of the circuit carrier must also be taken into account when selecting the material. In addition, the function of a heat sink in the short-term range can only be fulfilled by ceramic materials with high thermal conductivity. In order to avoid breakdowns, the insulation properties must also be observed. Attempts to increase the heat capacity directly by increasing the thickness of the circuit carrier itself have only been successful within narrow limits, since processing difficulties, for example through-contacting, occurred as part of the standard layer technology.

Weitere Ausgestaltungen der Erfindung sind in den Unteransprüchen gekennzeichnet. Die Erfindung wird nachfolgend an Ausführungsbeispielen anhand der Figuren der Zeichnung näher erläutert. Es zeigen

FIG 1 bis 4
vier verschiedene Ausgestaltungen einer erfindungsgemäßen Hybridschaltungsanordnung, jeweils in Seitenansicht,
FIG 5 und 6
in seitlicher Draufsicht zwei weitere Ausgestaltungen der Erfindung,
FIG 7
die gegen die Zeit aufgetragenen Belastbarkeitskurven einer bekannten und einer erfindungsgemäßen Schichtschaltung.
Further refinements of the invention are characterized in the subclaims. The invention is explained in more detail below using exemplary embodiments with reference to the figures of the drawing. Show it
1 to 4
four different configurations of a hybrid circuit arrangement according to the invention, each in side view,
5 and 6
a side view of two further embodiments of the invention,
FIG 7
the load capacity curves plotted against time of a known and a layer circuit according to the invention.

In FIG 7 ist die Belastbarkeit eines bekannten Schaltungsträgers im Vergleich zu einem erfindungsgemäß mit einem Keramikstreifen versehenen Schaltungsträger in Abhängigkeit von der Zeit dargestellt. Wichtig für die Anwendung ist vor allem der große Unterschied im Kurzzeitbereich, also bei etwa 0,1 sec. Eine noch höhere Belastung fuhrt dann zwar zur Unterbrechung der Leiterbahnen bzw. Schichtwiderstände durch Risse in den Schichten oder im Schaltungsträger. Der den gerissenen Schaltungsträger mindestens von einer Seite her zusammenhaltende Keramikstreifen verhindert jedoch eine Fragmentbildung.FIG. 7 shows the load capacity of a known circuit carrier in comparison with a circuit carrier provided according to the invention with a ceramic strip as a function of the Time shown. What is important for the application is above all the large difference in the short-term range, that is to say at about 0.1 sec. An even higher load then leads to the interruption of the conductor tracks or layer resistances due to cracks in the layers or in the circuit carrier. However, the ceramic strip holding the torn circuit carrier together from at least one side prevents the formation of fragments.

In FIG 1 ist ein Schaltungsträger 1 mit beispielsweise beidseitig aufgebrachten Schichtwiderstanden 2, die vollflächig oder mäandriert sein können, dargestellt. Die Verbindung der beiden Schichtseiten erfolgt über Durchkontaktierungen 3. Der Außenanschluß 4 ist in Single-in-Line(SIL)-Version ausgeführt. Rückseitig ist ein Keramikstreifen 6 in Schaltungsträgerdicke mit einem Wärmeleitkleber 5 befestigt. Die in FIG 1 dargestellte Ausfuhrung, die dem Diagramm gemäß FIG 7 entspricht, ist besonders kostengünstig. Die Kurzzeitlast kann weiter verbessert werden, indem der Keramikstreifen 6 dicker ausgeführt ist und/oder aus Berylliumoxid oder Aluminiumnitridkeramik besteht.1 shows a circuit carrier 1 with, for example, film resistors 2 applied on both sides, which may be full-surface or meandered. The two layer sides are connected via plated-through holes 3. The external connection 4 is designed in a single-in-line (SIL) version. A ceramic strip 6 of circuit carrier thickness is fastened on the back with a heat-conducting adhesive 5. The embodiment shown in FIG. 1, which corresponds to the diagram in FIG. 7, is particularly cost-effective. The short-term load can be further improved by making the ceramic strip 6 thicker and / or consisting of beryllium oxide or aluminum nitride ceramic.

In FIG 2 ist eine Ausfuhrung mit Dual-in-Line-Anschlußversion 7 und einer zusätzlichen Umkontaktierung durch einen Anschlußkamm 8 dargestellt. Die Ruckseitenkeramik 6 ist erheblich dicker als der Schaltungsträger 1 und außerdem etwas kleiner als dieser, so daß der Schaltungstrager 1 mit seinem Randbereich über die Fläche des Keramikstreifens 6 hinaussteht und dort mittels der Anschlußkämme 8 kontaktierbar ist. Ferner ist eine Thermosicherung 10 dargestellt, die bei zu großer Langzeitbelastung die elektrische Spannung der Schaltungsanordnung unterbricht. Die Thermosicherung 10 ist in an sich bekannter Weise so ausgebildet, daß die zuvorbehandelten Netzstörungen zu kurz sind, um zu einem Schmelzen bzw. Auslöten der Sicherung zu führen. Andererseits ist die Thermosicherung 10 so ausgelegt, daß sie bereits bei einer Langzeitbelastung mit etwa 600 V auslöst und die Schaltungsanordnung elektrisch unterbricht.FIG. 2 shows an embodiment with a dual-in-line connection version 7 and an additional contact changeover through a connection comb 8. The backside ceramic 6 is considerably thicker than the circuit carrier 1 and also somewhat smaller than this, so that the circuit carrier 1 projects with its edge region beyond the surface of the ceramic strip 6 and can be contacted there by means of the connecting combs 8. Furthermore, a thermal fuse 10 is shown, which interrupts the electrical voltage of the circuit arrangement when the long-term load is too great. The thermal fuse 10 is designed in a manner known per se so that the previously treated network faults are too short to cause the fuse to melt or unsolder. On the other hand, the thermal fuse 10 is designed in such a way that it triggers with a long-term load of approximately 600 V and electrically interrupts the circuit arrangement.

In FIG 3 ist eine SIL-Ausführung mit beidseitig aufgebrachten Wärmeentlastungs-Keramikstreifen 6 dargestellt. Mit dieser Ausführung ist eine weitere Erhöhung der Kurzzeit-Belastbarkeit möglich, wobei für eine eventuelle Thermosicherung eine Ausnehmung im jeweiligen Keramikstreifen 6 vorzusehen ist. Eine andere Ausgestaltung der Erfindung ist in FIG 4 dargestellt. Dabei ist der Keramikstreifen 6 höchstens 0,5, vorzugsweise jedoch nur etwa 0,1 mm dick. Er wird jedoch durch ein an seiner vom Schaltungstrager 1 abgewandten Seite in gut in wärmeleitender Weise befestigtes Metallprofil, beispielsweise aus Kupfer oder Aluminium, ergänzt.FIG. 3 shows a SIL design with heat-relief ceramic strips 6 applied on both sides. With this design, a further increase in the short-term load capacity is possible, a recess in the respective ceramic strip 6 being provided for a possible thermal fuse. Another embodiment of the invention is shown in FIG. 4. The ceramic strip 6 is at most 0.5, but preferably only about 0.1 mm thick. However, it is supplemented by a metal profile, for example made of copper or aluminum, which is fastened in a well heat-conducting manner on its side facing away from the circuit carrier 1.

FIG 5 und 6 zeigt jeweils die Ausgestaltung der Außenanschlüsse 4 als eine an sich bekannte, fertigungstechnisch günstige Standhilfe, wie sie bei allen Ausgestaltungen der Erfindung Verwendung finden kann. In FIG 5 ist eine flächig zwischen sich parallel zur Längsrichtung des Schaltungsträgers 1 erstreckende Leiterbahnen 11 und 12 aufgebrachte Widerstandsschicht 2 dargestellt, wobei die Anschlußflächen 13 für die Außenanschlüsse 4 an einer Längsseite des Schaltungsträgers 1 angeordnet sind. Die dargestellte Kontaktierung der Schichtwiderstände 2 am Anschluß 13 und gegenüberliegend 14 ist vorteilhaft, da absichtlich beim Bruch des Schaltungsträgers 1 durch eine zu hohe Kurzzeitbelastung die Leiterbahn 15 unterbrochen wird, was eine sofortige Abschaltung der thermischen bzw. elektrischen Überlast für die Baugruppe bewirkt. In FIG 6 ist eine Ausführung dargestellt, in der die Widerstandsschicht 2 mäandriert ist und an den Kurven Umleitungen 16 mit erheblich geringerem Flächenwiderstand aufweist. Dies dient zur Absicherung der notwendigen Stoßspannungsfestigkeit von mehr als 1 kV.FIGS. 5 and 6 each show the configuration of the external connections 4 as a known, technically advantageous stand aid, as can be used in all configurations of the invention. FIG. 5 shows a resistance layer 2 applied flat between conductor tracks 11 and 12 extending parallel to the longitudinal direction of the circuit carrier 1, the connection surfaces 13 for the external connections 4 being arranged on a longitudinal side of the circuit carrier 1. The contacting of the sheet resistors 2 shown at the connection 13 and opposite 14 is advantageous since the circuit 15 is deliberately interrupted when the circuit carrier 1 breaks due to a too high short-term load, which causes an immediate shutdown of the thermal or electrical overload for the module. FIG. 6 shows an embodiment in which the resistance layer 2 is meandered and has diversions 16 with considerably lower surface resistance on the curves. This serves to ensure the necessary surge voltage resistance of more than 1 kV.

Claims (9)

Hybridschaltungsanordnung mit einer mindestens einseitig auf einem plattenförmigen Schaltungsträger aus Glas oder Keramik aufgebrachten Widerstandsschicht,
dadurch gekennzeichnet, daß
auf mindestens einer Seite des Schaltungsträgers (1) ein Keramikstreifen (6) von mindestens nahezu gleichgroßer Fläche in gut wärmeleitender Weise befestigt ist.
Hybrid circuit arrangement with a resistance layer applied at least on one side to a plate-shaped circuit carrier made of glass or ceramic,
characterized in that
On at least one side of the circuit carrier (1), a ceramic strip (6) of at least almost the same size is attached in a heat-conducting manner.
Hybridschaltungsanordnung nach Anspruch 1,
dadurch gekennzeichnet, daß
das Material des Keramikstreifens (6) aus der Gruppe Aluminiumoxid, Berylliumoxid und Aluminiumnitrid ausgewählt ist.
Hybrid circuit arrangement according to Claim 1,
characterized in that
the material of the ceramic strip (6) is selected from the group aluminum oxide, beryllium oxide and aluminum nitride.
Hybridschaltungsanordnung nach Anspruch 1 oder 2,
dadurch gekennzeichnet, daß
der Keramikstreifen (6) mittels Wärmeleitkleber (5) befestigt ist.
Hybrid circuit arrangement according to Claim 1 or 2,
characterized in that
the ceramic strip (6) is attached by means of thermal adhesive (5).
Hybridschaltungsanordnung nach einem der Ansprüche 1 bis 3,
dadurch gekennzeichnet, daß
der Schaltungsträger (1) und der Keramikstreifen (6) beide aus Aluminiumoxid bestehen und beide etwa 1 mm dick sind.
Hybrid circuit arrangement according to one of Claims 1 to 3,
characterized in that
the circuit carrier (1) and the ceramic strip (6) both consist of aluminum oxide and are both about 1 mm thick.
Hybridschaltundsanordnung nach einem der Ansprüche 1 bis 3,
dadurch gekennzeichnet, daß
der Keramikstreifen (6) höchstens 0,5, vorzugsweise etwa 0,1 mm dick ist und daß an seiner vom Schaltungsträger (1) abgewandten Seite ein Metallprofil in gut wärmeleitender Weise befestigt ist.
Hybrid switching and switching arrangement according to one of Claims 1 to 3,
characterized in that
the ceramic strip (6) is at most 0.5, preferably about 0.1 mm thick and that on its side facing away from the circuit carrier (1) a metal profile is fastened in a heat-conducting manner.
Hybridschaltungsanordnung nach einem der Ansprüche 1 bis 5,
dadurch gekennzeichnet, daß
die Widerstandsschicht (2) mäandriert ist und an den Kurven Umleitungen (16) mit erheblich geringerem Flächenwiderstand aufweist.
Hybrid circuit arrangement according to one of Claims 1 to 5,
characterized in that
the resistance layer (2) is meandered and has diversions (16) on the curves with considerably lower surface resistance.
Hybridschaltungsanordnung nach einem der Ansprüche 1 bis 5,
dadurch gekennzeichnet, daß
die Widerstandsschicht (2) flächig zwischen sich parallel zur Längsrichtung des Schaltungsträgers(1) erstreckenden Leiterbahnen (11, 12) aufgebracht ist, wobei Anschlußflächen (13) an einer Längsseite des Schaltungsträgers (1) angeordnet sind.
Hybrid circuit arrangement according to one of Claims 1 to 5,
characterized in that
the resistance layer (2) is applied areally between conductor tracks (11, 12) extending parallel to the longitudinal direction of the circuit carrier (1), connection surfaces (13) being arranged on a longitudinal side of the circuit carrier (1).
Hybridschaltungsanordnung nach einem der Ansprüche 1 bis 7,
dadurch gekennzeichnet, daß
die Widerstandsschicht(2) über Leiterbahnen (15) mit im Randbereich des Schaltungsträgers (1) angeordneten Anschlußflächen (13) verbunden ist, wobei dieser Randbereich über die Fläche des Keramikstreifens (6) heraussteht und mittels Anschlußkämmen kontaktierbar ist.
Hybrid circuit arrangement according to one of Claims 1 to 7,
characterized in that
the resistance layer (2) is connected via conductor tracks (15) to connection surfaces (13) arranged in the edge region of the circuit carrier (1), this edge region protruding over the surface of the ceramic strip (6) and being contactable by means of connection combs.
Hybridschaltungsanordnung nach einem der Ansprüche 1 bis 8,
dadurch gekennzeichnet, daß
auf dem Schaltungstrager (1) eine mit der Widerstandsschicht (2) elektrisch verbundene Thermosicherung (10) angeordnet ist.
Hybrid circuit arrangement according to one of Claims 1 to 8,
characterized in that
a thermal fuse (10) which is electrically connected to the resistance layer (2) is arranged on the circuit carrier (1).
EP94119166A 1993-12-17 1994-12-05 Hybrid integrated circuit device Expired - Lifetime EP0665560B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE9319473U DE9319473U1 (en) 1993-12-17 1993-12-17 Hybrid circuit arrangement
DE9319473U 1993-12-17

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EP0665560A2 true EP0665560A2 (en) 1995-08-02
EP0665560A3 EP0665560A3 (en) 1997-05-02
EP0665560B1 EP0665560B1 (en) 2000-04-05

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EP (1) EP0665560B1 (en)
AT (1) ATE191581T1 (en)
DE (2) DE9319473U1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5914648A (en) * 1995-03-07 1999-06-22 Caddock Electronics, Inc. Fault current fusing resistor and method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002507329A (en) 1997-07-01 2002-03-05 シーメンス アクチエンゲゼルシヤフト Hybrid circuit device with overload protection circuit function
DE19814445C1 (en) * 1998-03-31 1999-06-24 Siemens Ag Hybrid circuit arrangement
US6404324B1 (en) * 1999-09-07 2002-06-11 General Motors Corporation Resistive component for use with short duration, high-magnitude currents

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4297670A (en) * 1977-06-03 1981-10-27 Angstrohm Precision, Inc. Metal foil resistor
EP0048938A1 (en) * 1980-09-25 1982-04-07 Siemens Aktiengesellschaft Vertically pluggable "single-in-line" circuit module without case
US4494104A (en) * 1983-07-18 1985-01-15 Northern Telecom Limited Thermal Fuse
EP0185244A1 (en) * 1984-12-07 1986-06-25 TELEFUNKEN electronic GmbH Electrical power component
US4719443A (en) * 1986-04-03 1988-01-12 General Electric Company Low capacitance power resistor using beryllia dielectric heat sink layer and low toxicity method for its manufacture
EP0465812A1 (en) * 1990-07-09 1992-01-15 International Business Machines Corporation Electronic assembly with enhanced heat sinking
EP0508615A1 (en) * 1991-04-10 1992-10-14 Caddock Electronics, Inc. Film-type resistor assembly
DE4234022A1 (en) * 1992-10-09 1994-04-14 Telefunken Microelectron Layered circuit with power resistor(s) - has extra ceramic carrier layer in heat conductive contact with power resistor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3792383A (en) * 1971-06-21 1974-02-12 Motorola Inc Hybrid strip transmission line circuitry and method of making same
US3766440A (en) * 1972-08-11 1973-10-16 Gen Motors Corp Ceramic integrated circuit convector assembly
DE3837974A1 (en) * 1988-11-09 1990-05-10 Telefunken Electronic Gmbh ELECTRONIC CONTROL UNIT
US5254969A (en) * 1991-04-02 1993-10-19 Caddock Electronics, Inc. Resistor combination and method
US5304977A (en) * 1991-09-12 1994-04-19 Caddock Electronics, Inc. Film-type power resistor combination with anchored exposed substrate/heatsink

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4297670A (en) * 1977-06-03 1981-10-27 Angstrohm Precision, Inc. Metal foil resistor
EP0048938A1 (en) * 1980-09-25 1982-04-07 Siemens Aktiengesellschaft Vertically pluggable "single-in-line" circuit module without case
US4494104A (en) * 1983-07-18 1985-01-15 Northern Telecom Limited Thermal Fuse
EP0185244A1 (en) * 1984-12-07 1986-06-25 TELEFUNKEN electronic GmbH Electrical power component
US4719443A (en) * 1986-04-03 1988-01-12 General Electric Company Low capacitance power resistor using beryllia dielectric heat sink layer and low toxicity method for its manufacture
EP0465812A1 (en) * 1990-07-09 1992-01-15 International Business Machines Corporation Electronic assembly with enhanced heat sinking
EP0508615A1 (en) * 1991-04-10 1992-10-14 Caddock Electronics, Inc. Film-type resistor assembly
DE4234022A1 (en) * 1992-10-09 1994-04-14 Telefunken Microelectron Layered circuit with power resistor(s) - has extra ceramic carrier layer in heat conductive contact with power resistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5914648A (en) * 1995-03-07 1999-06-22 Caddock Electronics, Inc. Fault current fusing resistor and method
US6253446B1 (en) 1995-03-07 2001-07-03 Richard E. Caddock, Jr. Fault current fusing resistor and method

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US5581227A (en) 1996-12-03
DE59409274D1 (en) 2000-05-11
ATE191581T1 (en) 2000-04-15
EP0665560A3 (en) 1997-05-02
DE9319473U1 (en) 1994-06-23
EP0665560B1 (en) 2000-04-05

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