EP0655177A1

EP0655177A1 - Bicmos ecl-to-cmos level translator and buffer

Info

Publication number: EP0655177A1
Application number: EP93914239A
Authority: EP
Inventors: Ban Pak Wong
Original assignee: Microunity Systems Engineering Inc
Current assignee: Microunity Systems Engineering Inc
Priority date: 1992-08-13
Filing date: 1993-05-28
Publication date: 1995-05-31
Also published as: JPH08500225A; AU4397293A; CA2141058A1; WO1994005085A1; EP0655177A4

Abstract

An ECL-to-CMOS level translator and BiCMOS buffer are described. The current supplied from the first input PMOS transistor (P1) is the input current to a current mirror comprising the first and second NMOS transistors (N1 and N2). The current mirror controls the current sourcing and sinking capability of the translator. Third and fourth NMOS transistors (N3 and N4) are coupled to the first and second NMOS transistors in the current mirror and function to vary the source-to-body voltage of the first and second NMOS transistors and consequently their gain which results in increased current drive and sinking capability. The BiCMOS differential buffer of the present invention provides a differential output signal on first and second output nodes (115 and 215). It is comprised of first and second cross-coupled buffers (100B and 200B). Cross-coupling the buffers results in improved high-to-low transition times.

Description

BICMOS ECL-TO-CMOS LEVEL TRANSLATOR AND BUFFER

FIELD OF THE INVENTION

The present invention relates to the field of bipolar complementary metal oxide silicon (BiCMOS) circuits, and particularly to level translator circuits and associated buffer circuitry.

BACKGROUND OF THE INVENTION

Bipolar/complementary metal oxide semiconductor (BiCMOS) processing and design techniques have been developed to create circuits which comprise both bipolar and complementary metal oxide silicon (CMOS) discrete devices. BiCMOS circuit designs take advantage of the speed of bipolar devices while and the relatively low power/space characteristics of CMOS devices. Commonly, bipolar emitter- coupled logic (ECL) circuits and CMOS devices are utilized in many BiCMOS memory designs.

One problem that exists in this merged technology is that ECL and CMOS devices often have different input/output (I/O) characteristics. As a result, ECL I/O characteristics are not usually compatible with most CMOS circuits. This means, for example, that an ECL output signal cannot be directly coupled into a CMOS input stage without first undergoing some sort of logic level adjustment. That is, an interface circuit is needed to adjust the output characteristics of one device type to the input characteristics of the other device type. Such an interface circuit between ECL and CMOS logic stages is frequently referred to as an ECL to CMOS level translator.

By way of example, a common prior art BiCMOS translator design utilizes two p-channel metal-oxide-silicon (PMOS) current switching transistors, and two n- channel metal-oxide-silicon (NMOS) transistors, as input devices. The NMOS transistors are configured as a current mirror. The ECL input signal to be converted and its inverse are coupled to the two input current switches. As a result, one of the input PMOS transistors is on and the other is off. The state of one of the PMOS transistors determines the input current to the first NMOS transistor of the current mirror. The current in the first NMOS transistor of the current mirror is reflected to the output of the second NMOS transistor of the current mirror, thus setting the output CMOS voltage level.

Another type of level translator that is typically utilized comprises a comparator and a reference voltage generator. The reference voltage generator supplies a reference voltage to the comparator. The reference voltage is equal to the midpoint between high and low voltage levels corresponding to an input logic signal. The output of the comparator is coupled to an CMOS output buffer. If the input logic signal coupled to the comparator is above the reference voltage level, the comparator drives the output buffer to a first CMOS logic level. Similariy, if the input logic signal is below the reference voltage, the comparator drives the output buffer to a second CMOS logic level. A comparator/voltage reference type level translator is disclosed in United States Patent No. 4,937,476 entitled "Self-Biased, High Gain Differential Amplifier with Feedback". The differential amplifier of U.S. Patent No. 4,937,476 functions as the comparator portion of the level translator described above. The main drawback of this type of level translator is that the reference voltage must be relatively stable over temperature variations so as to ensure consistent voltage level translation.

Another limitation of prior art translators is that they are generally incapable of providing sufficient current to drive subsequent stages of an integrated circuit. Therefore, it is frequently desirable to increase the current gain of the basic level translator circuit described above. The current driving capability of a translator is important because it affects the fan out of the translator (i.e., the number of gates that can be driven for a given current level). Also, current drive is related to the speed of level translation due to the translators ability to charge the input capacitance of the next stage.

One method which is commonly utilized to compensate for a translator's low current drive is to cascade several CMOS inverters to the output of the translator. This approach, however, adds a gate delay for each stage added and also results in increased transient power. Therefore, in an attempt to reduce the number of gate delays, circuit designers have replaced cascaded CMOS inverter designs with a single BiCMOS buffer design which includes a CMOS inverter and a bipolar transistor. This design, however, still introduces one inverter gate delay plus the turn on time of the bipolar buffer.

The prior art BiCMOS buffer described above is capable of generating only a single-ended output (i.e., only one non-inverted output signal). Frequently, it is necessary that a differential output (i.e., a non-inverted output signal and an inverted output signal) be supplied. In cases where a differential output is required, two BiCMOS buffer stages must be utilized. Each of the BiCMOS buffer stages are coupled to a single translator circuit. The non-inverted and inverted ECL input signals are coupled to each translator in such a way that one of the translators outputs a non- inverted CMOS signal and the other translator outputs an inverted CMOS signal. In this manner, two phases of the output CMOS signal are made available.

In overcoming the drawbacks of the prior art, the ECL-to-CMOS translator of the present invention provides increased current drive capabilities by means of two additional voltage-controlled NMOS resistors coupled to the current mirror of the input devices. The voltage-controlled NMOS resistors control the source-to-body bias voltage (Vsb) of the NMOS transistors in the current mirror. The effect of simultaneously varying the Vsb of the NMOS transistors in the current mirror and the input ECL signals, aids in the conductivity modulation of the current mirror transistors. Consequently, the gain of the current mirror is increased and the current gain capabilities of the translator of the present invention is improved. In addition, the differential BiCMOS buffer circuit of the present invention also obviates the CMOS inverter stage (and its associated gate delay) which is characteristic of prior art BiCMOS buffer circuit designs.

SUMMARY OF THE INVENTION

An ECL-to-CMOS level translator and a differential BiCMOS buffer circuit is described. In one embodiment, ECL input levels which are to be converted and their inverse are coupled to first and second input PMOS current switching transistors of the translator. The current flowing through the first PMOS transistor is supplied to the input of a current mirror circuit which is comprised of first and second NMOS transistors. The current mirror operates such that the current flowing through the first NMOS transistor is reflected to the output of the second NMOS transistor in the current mirrpr.

In addition to the two NMOS transistors, a third NMOS transistor is utilized to increase the current gain of the translator. The third NMOS transistor is coupled to the source of the first NMOS transistor in the current mirror. Also, the gate of the third NMOS transistor is controlled by one of the ECL input level signals. The third NMOS transistor functions to provide a variable voltage at the source of the first NMOS current mirror transistor. As a result, the voltage gain of the first NMOS transistor is increased. The increased voltage gain of the first NMOS transistor results in an increased voltage to the gate of the second NMOS transistor (the output device of the translator). Since the voltage at the gate of the second NMOS transistor is much larger for the same drive current on the first NMOS transistor, the overall current available at the output of the translator is increased without increasing its drive current.

A fourth voltage controlled NMOS transistor is coupled to the output NMOS transistor. The same relationship between the third and first NMOS transistors as described above exists between the the fourth NMOS transistor and second NMOS transistor. The voltage drop across the fourth NMOS transistor is controlled by one of the ECL input level signals. As a result, the fourth voltage controlled NMOS transistor functions to provide a variable resistance at the source of the second NMOS output transistor effecting the overall current behavior of the translator. When the translator is sourcing current, the fourth NMOS transistor provides a higher resistance at the source of the second NMOS transistor which aids in biasing the second NMOS transistor off. When the translator is sinking current, the fourth NMOS transistor provides a lower resistance at the source of the second NMOS transistor which reduces any debiasing effects of the second NMOS transistor.

The differential BiCMOS buffer circuit of the present invention may be utilized in conjunction with either the translator of the present invention or other prior art translators when configured to provide a differential output. The buffer functions to provide current drive to subsequent logic stages while eliminating the CMOS inverter stage which is commonly used in prior art translator buffering designs. In addition, translation times are improved by cross-coupling input signals between buffers. This cross-coupling design establishes a voltage equal to a Vtø (base-to-emitter voltage) at the input of each buffers pull-down circuitry. Consequently, the pull-down stage of the buffer is activated sooner and the buffers overall delay is decreased.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a circuit schematic diagram of the ECL-to-CMOS level translator of the present invention.

Figure 2 is a block diagram of two translators and two buffers configured to provide a differential CMOS output. The buffers are shown being cross-coupled.

Figure 3 shows a circuit schematic diagram of the differential BiCMOS buffer of the present invention.

Figure 4A-4C shows the timing diagrams of the output signal and other related internal signals of the buffer of the present invention.

Figure 5 illustrates a prior art CMOS level driver.

DETAILED DESCRIPTION

An ECL-to-CMOS level translator is described. In the following description, numerous specific details are set forth, such as typical ECL and CMOS logic levels, currents, device types, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well-known ECL and CMOS gates have not been described in detail in order not to avoid unnecessarily obscuring the present invention.

Figure 1 illustrates the ECL-to-CMOS level translator of the present invention, which includes p-channel field-effect devices P1 and P2, and n-channel devices N1- N4. Both of the drains of devices P1 and P2 are coupled to the supply potential, Vcc. on line 114. The ECL level input signals IN and IN/ (where IN/ is the inverse of IN) are shown being coupled to the gates of devices P1 and P2 on lines 111 and 112, respectively. It is appreciated that the input signals IN and IN/ originate from an ECL or BiCMOS logic stage; frequently an ECL or BiCMOS output buffer. Input logic signals from the previous ECL or BiCMOS stage are generally characterized as being equal to Vcc - ^vbβ for a high logic level signal and Vcc - ^vbβ - swing for a low logic level signal (where Vcc is the supply voltage for the ECL or BiCMOS logic stage, V e is a typical forward biased voltage drop across a base/emitter diode junction and Vswing is the voltage separating the high and low levels).

Input PMOS devices P1 and P2 function as input current switches. For example, when IN is low and IN/ is high, P1 is biased on and P2 is biased at its threshold voltage (Vt). Note that when P2 is biased at its threshold, it leaks a small drain-to-source current. The purpose of biasing this device at its threshold is to avoid the additional time it takes to turn on an MOS transistor from a completely off state. Because P1 is biased on, its drain to source current is significantly larger than that of P2.

When P1 is on and P2 is at its threshold, the translator is sinking current. The pull-down portion of the translator, comprising devices N2 and N4, is on and the pull- up portion of the translator, comprising device P2, is biased at its threshold. Therefore a current sinking path is established to the negative supply potential Vss through N2 and N4. Thus the translator sinks current from the next logic stage.

The drain-to-source current of device P1 on line 105 establishes the input current to the current mirror comprised of devices N1 and N2. The current mirror is configured such that the drain of N1 is coupled to its gate by line 116 and and the gates of N1 and N2 are coupled by line 109. The current of N1 is reflected to N2 on line 107 of the current mirror. Therefore, when P1 is biased at its threshold, the current reflected through to device N2 is small. Recognize that in prior art designs, the current flowing through device P1 is the same as the current flowing through N1. This current is reflected to device N2 and determines the output current. The translator of the present invention increases the output current by means of additional devices N3 and N4.

When IN is transitioning high-to-low, two factors are affecting the voltage drop across device N3. First, since IN is coupled to N3's gate on line 110, and Vss is coupled it its source on line 115, its resistance is increasing. Second, more current is made available to N3 due to transistor P1's simultaneous response to IN. As a result of both of these factors, when IN transitions high-to-low, the voltage drop across N3 (voltage on node 106) is increasing. When the voltage at node 106 rises, so does the source-to-body voltage (V_st>) of device N1. This occurs since the body of device N1 is coupled to Vss through line 120 and Vss remains relatively constant. Therefore, if the voltage at node 106 increases, then the V_S of N1 increases too. Increasing the V_Sb of device N1 raises the threshold voltage (Vt) of N1 , making the node voltage at 105 higher for the same drive current (the drive current being defined as the drain-to- source current of P1) as in prior art translator designs. Since node 105 is connected to the gate of N2, N2 is capable of sinking more current due to its increased gate-to- source voltage (V_gs).

Also, since IN/ is coupled to the gate of N4 on line 113 and Vss is coupled to its source on line 115, when IN is transitioning high-to-low, transistor N4's resistance is decreasing. This reduces the debiasing voltage (on node 108) of device N2, also resulting in increased current sinking capability of N2; (debiasing occurs when the voltage at the source of N2 approaches it's gate voltage resulting in reduced bias voltage at it's gate). Hence the combined effects of N3 and N4 results in increased current sinking capability of N2 when ECL input signal, IN, transitions high-to-low.

In the case where IN is transitioning low-to-high, the translator is sourcing current. Device P2 is biased on and P1 is biased at its threshold. In this condition, the pull-up portion of the translator, device P2, is activated. Therefore, a portion of the current flowing from P2 is sourced to the next logic stage. In addition, a small portion of the current flowing from P2 is flowing through N2. The reason for this is that since P1 is biased at its threshold, a small current flows through N1 and is reflected to N2. Therefore, N2 is not completely off. In prior art designs this leakage current has a deleterious effect on the current sourcing capability of the translator. In contrast, devices N3 and N4 of the present invention function to reduce this leakage current, thus increasing the sourcing capability of the translator.

As stated above, when IN is high and IN/ low, device P1 is at its threshold and P2 is on and sourcing current. With P1 biased at its threshold, only a small amount of current is made available to N1 and N3 from P1. As a result, the voltage drop occurring across N3 is less. The voltage drop across N3 (seen at node 106) is further decreased by the increase in its gate voltage (due to IN transitioning low-to-high). Increasing the gate voltage of N3 decreases its resistance thus reducing its associated voltage drop. Consequently, the voltage at node 106 approaches Vss- As described above, the voltage at node 106 affects the Vt of device N1. A lower V_S (voltage at node 106) results in a lower Vt for N1. This translates to a smaller voltage on node 109. Thus, the voltage at the gate of N2 is significantly lower when compared to prior art translator designs. This reduction in voltage reduces leakage current through N2 when device P2 is sourcing current. As a result, more current is made available at the output of the translator. Thus, the present invention provides an increase in pull-up and pull-down drive, without increasing the drive current supplied by P1.

Although the current sourcing ability of the level translator of Figure 1 represents a considerable improvement over prior art translators, in most applications additional buffer stages may still be required for increasing the overall current drive of a translator. Also, in some applications, it is desirable to perform a differential ECL-to- CMOS signal translation. In the past, two separate translator/buffer stages were generally utilized to obtain a differential CMOS output. This typically involves coupling an ECL signal and its inverse to the input of each of two level translators. The ECL differential input signals are coupled such that one translators outputs a CMOS signal corresponding to the non-inverted input ECL signal and the other translator outputs the inverse of this signal. The output CMOS signal from each translator is then coupled to a separate buffering circuit. Each of the output signals from the two buffers comprise the translated differential CMOS signal corresponding to the input ECL differential signal.

In contrast, the BiCMOS differential buffer of the present invention cross- couples the inverted and non-inverted buffer stages. Figure 2 shows a block diagram of the differential translator/buffer of the present invention. The non-inverted translator/buffer stage 100 comprises translator 100A and buffer 100B. Similarly, the inverted translator/buffer stage 200 is comprised of translator 200A and buffer 200B. Differential ECL input signals ECL(IN) and ECL(IN/) are coupled to each of translators 100A and 200A on lines 113 and 114 respectively. The ECL input signals are coupled such that translator 100A outputs a CMOS signal corresponding to ECL(IN), (output on line 116). Similarly, translator 200A outputs a CMOS signal corresponding to ECL(IN/) on line 216. Thus, the signal on line 116 is the inverse of the signal on line 216.

The translator CMOS output signals on lines 116 and 216 are coupled to buffers 100B and 200B respectively. In addition, ECL input signals, ECL(IN) and ECL(IN/) are coupled to buffers 100B and 200B on lines 113 and 114 respectively. The signals coupled to lines 113 and 114 are also the inverse to each other. Buffer 100B outputs a CMOS signal, CMOS(OUT), on line 115 corresponding to ECL(IN). Buffer 200B outputs a CMOS signal, CMOS(OUT/), on line 215 corresponding to ECL(IN/). Each of the output signals on lines 115 and 215 are the same as the signals on 116 and 216 except that the signals on lines 115 and 215 have a greater current drive.

When differential input signals ECL(IN) and ECL(IN/) make a transition from one state to another, the outputs of the translators follow. As an example, when ECL(IN) goes from a high to a low input level, the output of translator 100A (line 116) also transitions from a high to a low CMOS level. As shown in Figure 3, the signal on line 116 is coupled to buffer 100B. Consequently, the input signal to buffer 100B coupled on line 116 makes a high to low transition.

Note that the output of translator 200A follows the input signal ECL(IN/). Since ECL(IN/) is the inverse of signal ECL(IN), when ECL(IN) transitions from high to low, ECL(IN/) transitions from low to high. As a result, when the signal on line 116 is transitioning high to low, the signal on line 216 is transitioning in the opposite direction. As illustrated in Figure 2, buffer 100B and buffer 200B are cross-coupled by lines 117, 217, 118, and 218. The purpose of cross-coupling lines 117 and 217 is to speed up the pull-down portions of buffers 100B and 200B. Lines 118 and 218 provide a feedback technique which functions to drive output signals to Vcc and V_ss.

Note that translators 100A and 200A of Figure 2 may either comprise the level translator of Figure 1 , or a conventional translator. However, if conventional translators are utilized, then an additional CMOS inverter stage may be necessary depending on the current drive requirements of the next logic stage.

Figure 3 shows a schematic diagram of one embodiment of the cross-coupled differential buffers 100B and 200B of the present invention. There are four basic elements in each of buffers 100B and 200B: 1) an emitter follower which increases the pull-up current drive of an input signal; 2) a bipolar transistor configured as a diode for providing a bias potential equal to a Vbe for the pull-down driver; 3) a pull¬ down bipolar driver to improve the pull-down drive; and 4) output level circuitry for driving output levels to Vcc and Vss-

The emitter followers of buffers 100B and 200B include transistors T107 and T207, respectively. Bipolar transistors are utilized to take advantage of theircurrent drive capabilities when compared to MOS devices. Driver transistors T107 and T207 are turned on or off by input signals 116 and 216, respectively. Since signals 116 and 216 are the inverse of each other, only one of transistors T107 or T207 will be turned on at a time; the other will be off. For example, when the voltage on either of lines 116 or 216 is greater than a V e, one of transistors T107 or T207 is turned on and sources current to the next logic stage. As a result, a high output level is seen on the output of the buffer in which the driving transistor is turned on. On the other hand, when the voltage on either of lines 116 or 216 is less than a Vbe, one of transistors T107 or T207 is off; causing either of buffers 100B or 200B to sink current. As a result, a low output voltage level is seen on the output of the buffer in which the driving transistor is turned off.

The V e bias source for each of buffers 100B and 200B is comprised of P105 and T106 which is configured to function as a diode (buffer 100B) and P205 and T206 which is also configured to function as a diode (buffer 200B). PMOS devices, P105 and P205, provide a small trickle current to maintain the Vbe bias voltage when lines 116 or 216 are driven low. P105 and P205 also drive the anode of diodes T106 and T206 to Vcc, respectively, when their gates are driven low. For example, when the gate of P105 is low, the anode of diode T106 approaches Vcc. At the same time, the signal on the cathode of diode T106 is transitioning from a low-to-high voltage level. Diode T106 will be forward biased when the voltage on its cathode is at least equal to a Vbe lower than the voltage on its anode. Therefore, since the anode of diode T106 is coupled to approximately Vcc, and its cathode is transitioning low-to-high, T106 will be on until its cathode voltage transitions to a voltage close to Vcc. As long as T106 is on, the voltage on signal line 117 is equal to a V e above the voltage on line 116. Note, since the signals on line 114 is the inverse of the signal one line 113 only one of the PMOS transistors will be on at a time and thus, only one diode will be functioning as a bias source at one time.

The pull-down portion is another fundamental element in the differential buffer of the present invention. This pull-down circuitry is capable of discharging relatively large capacitive loads while imposing a relatively low load to its driver when compared to conventional CMOS drivers. The pull-down portion of buffer 100B comprises devices N108, N109 and T110. Similarly, the pull-down portion of buffer 200B comprises devices N208, N209, and T210. Since the differential cross-coupled buffers of the present invention operate such that one buffer sources current while the other sinks current, only one pull-down portion will be on at a time. The pull-down portion of buffer 100B operates such that when devices N109 and T110 are active, a current path is established between output line 115 and Vss- Therefore, buffer 100B can sink current through N108 and T110 to Vss thereby causing output line 115 to transition from a high-to-low state. Similarly, when devices N209 and T210 are active; buffer 200B sinks current, and output 215 may transition from a high-to-low state.

As can be seen in Figure 3, to establish the current sinking path in one of the pull-down portions it is necessary to provide enough voltage to overcome the threshold voltage (Vt) of either N 108 or N208 and the base-to-emitter voltage (V e) of either T110 or T210. Thus, one of the pull-down portions of buffers 100B or 200B are on if the voltage on the gates of N108 or N208 is greater than a voltage equal to a Vt plus a Vbe-

To deactivate the current sinking portion of the pull-down circuitry, it is necessary to turn on either N109 or N209. This is accomplished by applying a voltage greater than a Vt on the gates of either N109 or N209. By turning either N109 or N209 on, the base of either T110 or T210 will be discharged; thus ensuring that the current sinking portion of the pull-down circuitry is off.

The high-to-low transition time of the output signals on lines 115 and 215 are dependent on how quickly the pull-down portion can drive lines 115 or 215 to Vss- Therefore, the quicker the pull-down portions are activated, the faster the high-to-low transition times will be. Commonly, in prior art buffer designs, the voltage signal that is coupled to and controls the pull-down circuitry is the inverse of the input signal that is coupled to the driving transistor. Consequently, the inverse of the input signal to the driver transistors, T107 and T207, determines how quickly the pull-down portion of the buffer is activated. But the input signal to the driver transistors are taken from the output of the preceding translator stage. Thus, it follows that the translator output signal determines how quickly the pull-down portion of each buffer is activated.

In the present invention, however, the voltage signal coupled to the pull-down portion of the present invention does not come from the output of the preceding translator stage. Instead, the voltage signal coupled to the pull-down portion of one buffer stage is cross-coupled from another preceding translator output through a diode. Figure 3 shows that for buffer 100B, the gate of pull-down device N108 (the input device for the pull-down circuitry) is coupled to the anode of diode T206 by line 217. The cathode of T206 is coupled to line 216 (the output signal of translator 200 A). The purpose of the bias diode design is to cause one of the pull-down portions of the differential buffer to turn on sooner than if it were simply coupled to the output of the preceding translator stage. For example, when the voltage on line 113 is low, device P205 is on. As a result, the anode of diode T206 is coupled to Vcc and is also on. T206 remains on as long as the voltage on line 216 is low enough to keep T206 forward biased. Consequently, T206 acts as a bias source approximately equal to a V e- Therefore, the voltage applied to the gate of N108 is equal to one Vbe higher than the voltage on line 216. Hence, the voltage necessary to turn on devices N108 and T110 is achieved sooner than if just applied straight from the previous translator stage.

Figures 4A shows the voltage signal seen by the gate of N108 when biased at a Vbe similar to the configuration of the present invention. Line 301 representsihe inverse of the voltage signal supplied by the output of the preceding translator output (line 116 of Figure 3). In prior art designs this signal is coupled to the gate of input pull-down device N108. As can be seen in Figure 4A, voltage signal 301 reaches the turn-on voltage (Vt + V e) of the pull-down circuitry at a time of T1. Therefore at time T1 , the pull-down circuitry is activated and starts sinking current. As a result, the output voltage of buffer 100B (voltage signal on line 115) begins to transition from a high-to-low level. Figure 4C illustrates the output voltage on line 115. Line 306 shows the output signal transitioning high-to-low at a time T1 (the time when the pull¬ down circuitry is activated). This occurs when the inverse of signal 116 reaches a voltage equal to (V_t + Vbe)- Figure 4B illustrates the voltage signal seen by the gate of N108 when biased at a VVbe similar to the configuration of the present invention. Line 302 is the voltage signal on line 216 (Figure 3). As can be seen when comparing Figures 4A and 4B, the inverse of the voltage signal on line 116 is essentially the same as the signal on line 216. As described above, the voltage signal coupled to the gate of N108 (on line 217) is at a potential equal to one diode drop above the signal on line 216 when configured as disclosed by the present invention. The relationship between the voltage signals coupled on 217 and 216 is illustrated in Figure 4B. Line 303 (voltage signal on line 217) is approximately one diode drop above line 302 (voltage signal on line 216). Therefore, the signal on line 217 reaches the turn-on voltage (Vt + V_be) of the pull-down circuitry at a time T2. Therefore at a time T2, the pull-down circuitry is activated and starts sinking current. Figure 4C (line 307) shows the output signal on line 115 transitioning high-to-low at a time T2. As can be seen in Figure 4C, a high-to- low output transition on line 115 Figure 3 (signal 307, Figure 4C) occurs sooner than the output signal 306 (Figure 4C). Therefore, high-to-low output transitions times are improved when utilizing the present invention cross-coupled buffer design. Though the differentaii buffer of the present invention is described in conjunction with the level translator of the present invention, it can be utilized with any BiCMOS logic stage that requires differential buffering.

Another element commonly found in buffering stages is a differential CMOS output level driver. The driver functions to drive the differential outputs to the high and low CMOS output levels. The reason this is needed is because differential buffers 100B and 200B can only drive nodes 115 and 215 to a voltage that is either a Vbe from Vcc or Vss, i-β. a Vbe from the desired CMOS high and low level voltages. For example, when buffer 100B is transitioning high-to-low, the voltage on the collector of T110 (which is the same as the output voltage signal on 115) will be approaching ground. However, when the voltage on the collector reaches Vbe, i becomes biased such that it turns off. Therefore, the pull-down circuitry can only pull the output signal on line 115 to a voltage equal to approximately a V e above Vss- Similariy, if buffer 200B is transitioning from a low-to-high level, T207 is biased on until the output signal on line 215 reaches a voltage of Vcc ~ Vbe- Differential buffer output signals that are not truly at CMOS high or low level voltages may lead to an accumulated amount of leakage current resulting in increased power dissipation in subsequent logic stages. Consequently, an inverter configuration such as shown in Figure 5A is commonly utilized to drive output nodes 115 and 215 to either high or low CMOS output levels. The prior art inverter configuration shown in Figure 5A is comprised of two inverters per output for a differential buffer (a total of four per one differential output buffer). As shown, the CMOS(OUT) output line 115 of differential buffer 100B is coupled to the input of inverter 500 and the output of inverter 501. The output of inverter 500 and the input of inverter 501 are also coupled together. Correspondingly, the CMOS(OUT/) output line 215 of differential buffer 200B is coupled to the input of inverter 502 and the output of inverter 503. The output of inverter 502 and the input of inverter 503 are also coupled together. Since the inverters have an input trip level of Vcc 2, the inverter configurations function such that if an output signal seen on either of lines 115 or 215 are not at CMOS high and low voltage level (Vcc or Vss). the inverters drive the signal to either Vcc or Vss- One main disadvantage of this type of inverter scheme is the number of inverters necessary to accommodate a differential output. When space conservation is an issue, this prior art inverter design may be cumbersome. Another constraint of the prior art inverter design is that it adds the power dissipation of four inverters. Therefore, in memory designs in which space and power consumption are extremely important factors, the prior art inverter design can present some limitations.

The present invention utilizes a cross-coupled inverter design as shown in Figure 3. As illustrated, output line 115 is coupled to the input of inverter 111 the output of inverter 111 being coupled to output line 215. Similarly, output line 215 is coupled to the input of inverter 211 the output of inverter 211 being coupled to output line 115. In comparison to prior art inverter designs, only two inverters are necessary for a differential output. Therefore, the present invention inverter design reduces the number of inverters necessary by 50%. The inverter design of the present invention consumes less power than prior art designs since only two inverters are necessary to drive each of the differential outputs to the CMOS high or low voltage levels.

The level driver shown in figure 3 functions such that if the output signal on line 215 is transitioning from a low-to-high voltage and reaches the Vcc/2 trip point voltage of inverter 211 , it causes the output of inverter 211 to drive output line 115 to a CMOS low level voltage, i.e. Vss- The output of inverter 211 (output signal 115) feeds back to the input of inverter 111. Thus, the output signal on line 215 is driven to a high CMOS level (Vcc).

Although the elements of the present invention has been described in a conjunction with certain embodiments, it is appreciated that the invention may be implemented in a variety of other ways. By way of example, the differential buffering stage may be coupled to any differential logic stage. Or, the translator of the present invention may be coupled with other buffering stages. Consequently, it is to be understood that the particular embodiments shown and described by way of illustration are in no way intended to be considered limiting. Reference to the details of these embodiments is not intended to limit the scope of the claims which themselves recite only those features regarded as essential to the invention.

Thus, the present invention offers an improved BiCMOS ECL-to-CMOS level translator and BiCMOS buffer.

Claims

CLAIMSWe Claim:

1. A voltage level translator for converting an input signal compatible with a first logic level to an output signal compatible with a second logic level comprising: first and second input nodes, said first input node for receiving said input signal and said second input node for receiving the inverse of said input signal; first and second transistors coupled in series to a first operating potential, said first transistor having its gate coupled to said first input node, said second transistor having its gate coupled to its drain and its body coupled to a second operating potential; third and fourth transistors coupled in series to a common output node, said third transistor also being coupled to said first operating potential and having its gate coupled to said second input node, said fourth transistor having its body coupled to said second operating potential; said second and fourth transistors having their gates coupled to a third node; a variable voltage means for varying the source-to-body voltage of said second transistor coupled between the source of said second transistor and said second operating potential. a variable resistance means for varying the resistance coupled to the source of said fourth transistor, said variable resistance means being coupled between the source of said fourth transistor and said second operating potential; wherein when said input signal is at a high potential compatible with said first logic level, said third transistor drives said output node to a high potential compatible with said second logic level, and when said input signal is at a low potential compatible with said first logic level, said fourth transistor and said variable resistance means drive said output node to a low potential compatible with said second logic level.

2. The translator as described in claim 1 wherein the voltage gain of said second transistor varies correspondingly with its source-to-body voltage, said voltage gain determining the voltage potential on the gates of said second and fourth transistors.

3. The translator as described in claim 2 wherein said variable voltage means comprises a fifth transistor having its drain coupled to said source of said second transistor, its gate being coupled to said first input node and its source being coupled to said second operating potential.

4. The translator as described in claim 3 wherein said variable resistance means comprises a sixth transistor having its drain coupled to said source of said fourth transistor, its gate being coupled to said second input node and its source being coupled to said second operating potential.

5. The translator as described in claim 4 wherein said first, second, third, fourth, fifth, and sixth transistors comprise metal oxide semiconductor (MOS) devices and said second logic signal is compatible with complementary MOS logic.

6. The translator as described in claim 5 wherein said first logic signal is compatible with emitter coupled logic.

7. An improved BiCMOS voltage level translator having first and second MOS devices coupled to function as a current mirror, the input of said current mirror being the drain of said first MOS device and the output of said current mirror being the drain of said second MOS device, the gates of said first and second MOS devices being coupled together and said first MOS device having its drain coupled to its gate, said first and second MOS devices having their body coupled to a first operating potential, said improvement comprising: a variable voltage means for varying the source-to-body potential of said first MOS device, said variable voltage means being coupled between the source of said first MOS device and said first operating potential, said first variable voltage means being responsive to a first input signal; a variable resistance means for varying the resistance at the source of said second MOS device, said variable resistance means being coupled between the source of said second MOS device and said first operating potential, said variable resistance means being responsive to the inverse of said first input signal.

8. The translator as described in claim 7 wherein the voltage gain of said first MOS device varies correspondingly with its source-to-body voltage.

9. The translator as described in claim 8 wherein said variable voltage means comprises a third MOS device having its drain coupled to said source of said first MOS device, its gate being coupled to said first input signal and its source being coupled to said first operating potential.

10. The translator as described in claim 9 wherein said variable resistance means comprises a fourth MOS device having its drain coupled to said source of said second MOS device, its gate being coupled to said second input signal and its source being coupled to said first operating potential.

11. A differential bipolar complimentary metal oxide semiconductor (BiCMOS) circuit comprised of first and second identical cross-coupled buffers, for providing buffered first and second output logic signals from first and second input logic signals, each of said first and second buffers comprising: a first input node for receiving said first input logic signal; a second input node for receiving said second input logic signal; an output node; an input device coupled to said first input node, a first operating potential and a cross-coupling node; a pull-down circuit coupled between said output node and a second operating potential, and coupled to said second input node, said pull-down circuit for driving said output node to a low voltage level corresponding to said first and second input logic signal ; an output device coupled to a first operating potential, said second input node and said output node, said output device for driving said output node to a high voltage level corresponding to said first and second input logic signal; a voltage means for providing an activation voltage to said pull-down circuit, said diode means being coupled to said cross-coupling node and said second input node; said cross-coupling node of said first buffering circuit being coupled to said pull-down circuit of said second buffering circuit and said cross-coupling node of said second buffering circuit being coupled to said pull-down circuit of said first buffering circuit; wherein, when said first input logic signal is at a voltage corresponding to a high logic level, said first buffers output node is at a voltage corresponding to a low logic level and said second buffers output node is at a voltage corresponding to a high logic level; and wherein, when said first input logic signal is at a voltage corresponding to a low logic level, said first buffers output node is at a voltage corresponding to a low high level and said second buffers output node is at a voltage corresponding to a low logic level.

12. The differential BiCMOS circuit as described in claim 11 wherein said pull-down circuit comprises first and second metal oxide semiconductor (MOS) devices coupled in series between said output node and said second operating potential and coupled in parallel to a first bipolar transistor, said first MOS device having its drain coupled to said output node, its gate being coupled to said cross- coupling node and its source being coupled to the base of said first bipolar transistor, said second MOS device having its gate coupled to said second input node, wherein said pull-down circuit is driving said output node to a low potential corresponding to said first and second input logic signals when the gate voltage of said first MOS device is greater than the threshold voltage of said first MOS device plus the forward bias base-to-emitter voltage of said first bipolar transistor.

13. The differential BiCMOS circuit as described in claim 12 wherein said voltage means is a second bipolar transistor having its collector and base coupled together and its emitter coupled to said second input node, wherein said activation voltage is approximately equal to the forward biased base-to-emitter voltage of said second bipolar transistor.

14. The differential BiCMOS circuit as described in claim 13 wherein said input device comprises an third MOS device and said output device comprises a third bipolar transistor.

15. The differential BiCMOS circuit as described in claim 14 wherein said first and second input and output logic signals are compatible with CMOS circuitry.