AU4397293A - Bicmos ecl-to-cmos level translator and buffer - Google Patents

Bicmos ecl-to-cmos level translator and buffer

Info

Publication number
AU4397293A
AU4397293A AU43972/93A AU4397293A AU4397293A AU 4397293 A AU4397293 A AU 4397293A AU 43972/93 A AU43972/93 A AU 43972/93A AU 4397293 A AU4397293 A AU 4397293A AU 4397293 A AU4397293 A AU 4397293A
Authority
AU
Australia
Prior art keywords
buffer
level translator
cmos level
bicmos
ecl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU43972/93A
Inventor
Ban Pak Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microunity Systems Engineering Inc
Original Assignee
Microunity Systems Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microunity Systems Engineering Inc filed Critical Microunity Systems Engineering Inc
Publication of AU4397293A publication Critical patent/AU4397293A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
AU43972/93A 1992-08-13 1993-05-28 Bicmos ecl-to-cmos level translator and buffer Abandoned AU4397293A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US92929592A 1992-08-13 1992-08-13
US929295 1992-08-13
PCT/US1993/005106 WO1994005085A1 (en) 1992-08-13 1993-05-28 Bicmos ecl-to-cmos level translator and buffer

Publications (1)

Publication Number Publication Date
AU4397293A true AU4397293A (en) 1994-03-15

Family

ID=25457621

Family Applications (1)

Application Number Title Priority Date Filing Date
AU43972/93A Abandoned AU4397293A (en) 1992-08-13 1993-05-28 Bicmos ecl-to-cmos level translator and buffer

Country Status (5)

Country Link
EP (1) EP0655177A4 (en)
JP (1) JPH08500225A (en)
AU (1) AU4397293A (en)
CA (1) CA2141058A1 (en)
WO (1) WO1994005085A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19633723C1 (en) * 1996-08-21 1997-10-02 Siemens Ag Level conversion circuit for combined CMOS and ECL circuit
GB0413152D0 (en) * 2004-06-14 2004-07-14 Texas Instruments Ltd Duty cycle controlled CML-CMOS converter

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380710A (en) * 1981-02-05 1983-04-19 Harris Corporation TTL to CMOS Interface circuit
EP0218238B1 (en) * 1985-10-09 1991-07-03 Nec Corporation Differential amplifier circuit
KR910002967B1 (en) * 1986-12-12 1991-05-11 가부시끼가이샤 히다찌세이사꾸쇼 Semiconductor integrated circuit combined by bipolar transistor and mos transistor
US5019729A (en) * 1988-07-27 1991-05-28 Kabushiki Kaisha Toshiba TTL to CMOS buffer circuit
US5039886A (en) * 1989-05-26 1991-08-13 Nec Corporation Current mirror type level converters
JP2545146B2 (en) * 1990-01-25 1996-10-16 富士通株式会社 Level conversion circuit
US5113097A (en) * 1990-01-25 1992-05-12 David Sarnoff Research Center, Inc. CMOS level shifter circuit
JPH04335297A (en) * 1991-05-09 1992-11-24 Mitsubishi Electric Corp Input buffer circuit for semiconductor integrated circuit device
US5153465A (en) * 1991-08-06 1992-10-06 National Semiconductor Corporation Differential, high-speed, low power ECL-to-CMOS translator
US5202594A (en) * 1992-02-04 1993-04-13 Motorola, Inc. Low power level converter

Also Published As

Publication number Publication date
EP0655177A4 (en) 1997-03-26
EP0655177A1 (en) 1995-05-31
WO1994005085A1 (en) 1994-03-03
CA2141058A1 (en) 1994-03-03
JPH08500225A (en) 1996-01-09

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