EP0592650A1 - Circuit d'acheminement de signaux pour support d'extension de microprocesseur - Google Patents

Circuit d'acheminement de signaux pour support d'extension de microprocesseur

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Publication number
EP0592650A1
EP0592650A1 EP93910881A EP93910881A EP0592650A1 EP 0592650 A1 EP0592650 A1 EP 0592650A1 EP 93910881 A EP93910881 A EP 93910881A EP 93910881 A EP93910881 A EP 93910881A EP 0592650 A1 EP0592650 A1 EP 0592650A1
Authority
EP
European Patent Office
Prior art keywords
upgrade
microprocessor
signal
socket
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP93910881A
Other languages
German (de)
English (en)
Inventor
Charles J. Stancil
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of EP0592650A1 publication Critical patent/EP0592650A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)

Definitions

  • This invention relates to personal computers and, more particularly, to personal computers which can be upgraded by plugging an upgrade microprocessor into an option socket to improve performance.
  • One line of microprocessors currently in favor are the Intel Corp. processors, which form the basis for personal computers compatible with those originally produced by International Business Machines Corp. such as the IBM PC/AT.
  • the line extends from the 8088 to the 80486.
  • Particularly favored units include the 386SX, the 386DX, the 486SX and the 486DX, in general order of increased performance. Therefore it is common to use these microprocessors on the interchangeable processor cards.
  • the 486DX, 486SX and companion 487SX are the 486SX can be considered as an 486DX without the internal numeric coprocessor. When a numeric coprocessor is necessary, an 487SX is inserted into the system. Therefore, according to recommendations from Intel, two full sockets are necessary on the processor card to allow numeric coprocessor support. This creates major space problems on already crowded interchangeable processor cards.
  • a computer system according to U.S. patent application serial number 07/757,722, filed September 11, 1991, permits the microprocessor to be upgraded from a 486SX microprocessor to a 487SX microprocessor, or from a 486SX or 487SX to a 486DX microprocessor, merely by removing the old processor from the socket and replacing it with the higher performance processor and properly setting several switches.
  • this method is effective, the computer system is limited to the 486 family of processors, which are currently the most expensive and exotic personal computer microprocessors offered by Intel.
  • the microprocessor can be upgraded from a 386 family microprocessor to a 486 family microprocessor without exchanging the processor card.
  • the computer includes a 386DX main CPU permanently lodged in the system along with an Intel 82395 cache system.
  • the computer includes a single empty socket which can be fitted with a 486SX, 487SX, 486DX or 486DX2 microprocessor. Any of these microprocessors can be plugged into the socket, and by setting the proper switches the cache system enters a tri-state test mode and suspends the operation of the main CPU.
  • the 486SX, 487SX and 486DX/DX2 all have different pin arrangements with differing numbers of signals.
  • certain computer system signals must be routed to different pins for the different microprocessors. Control of this routing is accomplished by a set of three switches which are set according to the type of microprocessor used.
  • specific system signals are rerouted among the system components using a set of six switches to provide for proper operation of the computer when the socket is empty and when it is occupied.
  • the correct signals are provided to each pin of the upgrade microprocessor, while the cache system remains in test mode, the main CPU remains fundamentally inactive, and the upgrade processor controls the computer system. This allows the computer system to be upgraded from a 386 microprocessor to a 486 microprocessor by simply placing the upgrade processor in the socket, setting the switches, and resetting the system.
  • Figure 1 is a block diagram of a computer system incorporating the present invention
  • Figures 2A, 2B, and 2C are top view pin diagrams of the 486DX, 487SX, and the 486SX microprocessors, respectively;
  • Figure 3 is a schematic diagram of a circuit for routing various signals to particular upgrade socket pins;
  • Figure 4 is a block diagram of a circuit for routing various system signals among system components.
  • Figure 5 is a block diagram of a circuit for routing the FLUSH* and UPGRADE* signals to the cache system.
  • System C designates generally a computer system incorporating the present invention.
  • System C is comprised of a number of block elements interconnected via four buses.
  • an asterisk following the signal mnemonic indicates that the signal may be active at a logic low level and always is the inverse of a signal mnemonic without the asterisk.
  • Signal mnemonics having numbers or ranges between angle brackets refer to those particular bits or positions in a bus.
  • a main CPU 20 is connected to a numeric coprocessor 22 and to a cache system 24.
  • a bus, generally referred to as the P or processor bus 26 is used to connect the main CPU 20, the numeric coprocessor 22 and the cache system 24.
  • the main CPU 20 is an Intel Corporation 80386 DX-25 microprocessor, while the numeric coprocessor is an 80387 and the cache system 24 is an 82395 cache controller.
  • the 82395 is used as its back end interface is similar to and compatible with the 486 variations.
  • a second or H or host bus 28 is used to connect the cache system 24 to various other elements in the computer system C.
  • an upgrade CPU socket 30 is provided to receive various upgrade sockets of the 486 family developed by Intel.
  • a level 2 or secondary cache 32 is also connected to the host bus 28 for operation. It is understood that the various buses such as the P bus 26 and the host bus 28 are generally comprised of three portions: an address portion, a data portion, and a control portion, such as the PA, PD and PC buses or the HA, HD and HC buses.
  • the main CPU 20 and the upgrade socket 30 are also connected to a CPU utility control (CUC) circuit 36 by the PC bus and the HC bus.
  • the CUC 36 is connected to an X data bus 60, which is a form of an input/output ( /0) bus in the computer C.
  • the CUC 36 performs miscellaneous CPU control and interface functions.
  • a memory controller 34 is connected to the host bus 28 to provide control of the memory utilized in the computer system C.
  • the memory controller 34 provides control signals to a row address strobe (RAS) decode and buffer unit 38 which is connected to the memory controller 34.
  • the memory controller 34 is also connected to base memory 40 by a memory or M bus.
  • the base memory 40 is developed by using a plurality of dynamic random access memories (DRAMs) which are conventionally soldered to the circuit board.
  • Memory sockets 42 are preferably designed to receive single in-line memory modules (SIMMs).
  • SIMMs single in-line memory modules
  • the RAS outputs from the RAS decoder 38 are provided to the memory sockets 42.
  • the memory controller 34 provides the memory control MC and memory address MA signals to the base memory 40 and to buffers 44 which are in turn connected to the memory sockets
  • EBB EISA bus buffer
  • the computer system C utilizes an ISA external bus, designated as the S bus
  • a bus controller 50 referred to as the MBC provides certain of the necessary control functions between the H bus 28 and the S bus 49 and provides the S bus control or SC lines.
  • the MBC 50 Connected to the MBC 50 is the EISA system peripheral (ESP) circuit 48, which is compatible with an ISA bus system and includes various timers, the direct memory access (DMA) controller and the interrupt controller logic of the computer system C.
  • the MBC 50 controls an address EBB 51 connected to the HA bus to develop the LA and SA address lines and a data EBB 53 connected between the HD bus and the SD bus to develop the SD lines.
  • Connected to the S bus 49 is are the ISA connectors 57 to receive option circuit boards.
  • Developed from the S bus 36 is the fourth and remaining bus referred to as the X bus 60.
  • the X bus is developed by means of a system glue chip (SGC) 55 which is connected to the S bus 49 and, performs numerous address decoding operations.
  • the SGC 55 controls a buffer 62 connected to the SA lines to develop the XA address lines and a buffer 64 provided between the SD lines and the XD lines.
  • the SC control lines are used directly to help control the X bus 60.
  • Various internal components in the computer system C are connected to the X bus 60.
  • the read only memory or ROM 66 containing the BIOS of the computer system C is connected to the X bus 60 as are the real time clock (RTC) and CMOS memory 68, a keyboard controller 70, a floppy disk controller 72 and a multiple peripheral controller 74.
  • a video system 52 is connected to the X bus, with a monitor 54 connected to the video system 52 to provide a graphic output for the computer system C. Additionally, an audio system 56 is connected to the X bus 60, with an internal speaker and jacks 58 for external amplifiers and speakers connected to the audio system 56.
  • the keyboard controller 70 is connected to a keyboard and a mouse system 76 to provide user input while the floppy disk controller 72 is connected to a floppy disk drive 78.
  • the multiple peripheral controller 74 contains a parallel port which is connected to a parallel interface 80, a serial port which is connected to a serial interface 82 and a hard disk interface which is connected to a hard disk unit 84.
  • the computer system C shown in Figure 1 is exemplary of a computer system incorporating the present invention and numerous other variations could of course be developed as obvious to one skilled in the art.
  • the computer system C of the preferred embodiment is compatible with four types of upgrade microprocessors manufactured by Intel: the 486SX, the 487SX, the 486DX and 486DX2.
  • any references to 486DX will also include a reference to the 486DX2 as the pin arrangements are identical.
  • Each microprocessor type includes a family of microprocessors having various performance characteristics and qualities, but sharing the same basic design and pin arrangement.
  • each of the three types of upgrade microprocessors shares a common pin arrangement but for 5 pins. The connections of these 5 pins to the various signals of the computer system must be changed according to the particular type of microprocessor used.
  • Pin A13 generates the FERR* (Floating Point Error) signal on the 487SX chip.
  • the asterisk (*) indicates that the signal is asserted LOW and negated HIGH. When asserted LOW, the FERR* signal indicates that a floating point error has occurred.
  • the FERR* signal is supplied to the CUC 36. In the 486SX and 486DX microprocessors, pin A13 is not used, and should be unconnected.
  • the FERR* signal is generated on pin C14.
  • Pin C14 is not used, however, on the 486SX and the 487SX microprocessors, and is thus not connected for those microprocessors.
  • Pin B15 receives the NMI (Non-Maskable Interrupt) signal from the computer system on the 487SX and the 486DX microprocessors.
  • the NMI signal is generated by the ESP 48 and is supplied to the upgrade socket. When asserted HIGH, the NMI signal indicates that a potentially fatal error has occurred in the system. This interrupt cannot be disabled and will always be serviced if active.
  • Pin B15 is not used in the 486SX microprocessor, and therefore remains unconnected.
  • pin A15 receives the NMI signal.
  • pin A15 should receive the IGNNE* (Ignore Numeric Error) signal.
  • the IGNNE* signal is asserted LOW and negated HIGH.
  • the IGNNE* signal when asserted LOW by the CUC 36, instructs the processor to ignore a numeric error and continue executing floating point instructions.
  • the processor freezes a non-control floating point instruction if a previous floating point instruction caused an error.
  • the IGNNE* signal is not used by the 486SX microprocessor.
  • Pin B14 is an extra pin used only on the 487SX microprocessor. Pin B14 generates the UPGRADE* signal, which is asserted LOW and negated HIGH. When asserted LOW, the UPGRADE* signal indicates to the various system components that a processor is present in the upgrade socket. The pin at the B14 location on the 486SX and 486DX microprocessors is not connected.
  • a computer system includes the upgrade socket 30 that can receive any of the upgrade microprocessor types.
  • a set of switches 160, 162, and 164 control the routing of signals to and from pins A13, C14, B14, B15 and A15.
  • Each switch 160, 162 and 164 is a 2 position, preferably surface mount, switch.
  • the switch 160 controls the routing of pin C14.
  • pin C14 should be unconnected for the 486SX and the 487SX microprocessors, but generates the FERR* signal of the 486DX microprocessor.
  • One side of the switch 160 is connected to ground, and the other side is connected to a resistor 166.
  • the other end of the resistor 166 is connected to a 5 volt supply so that when switch 160 is open, a HIGH signal is generated at the node between the resistor 166 and the switch 160.
  • the resistor 166 and the switch 160 are connected to the inverted enable input of a non-inverting tri-state buffer 168. If enabled, the buffer 168 allows a signal to pass through the buffer 168. If the buffer 168 is not enabled, the buffer 168 is in a tri-state mode and acts like an open circuit.
  • the input of the buffer 168 is connected to pin C14 and the output of the buffer
  • a switch 162 controls the routing of pin B14 and the UPGRADE* signal. One end of the switch 162 is connected to ground, and the other end of the switch 162 is connected to a resistor 170. The resistor 170 is connected to the 5 volt supply.
  • the resistor 170 and the switch 162 are connected to the inverted enable input of a non-inverting tri-state buffer 171 identical to the buffer 168 described above.
  • the input of the buffer 171 is connected to pin B14 of the upgrade socket 30, and the output of the buffer 171 is connected to the UPGRADE* signal.
  • Pin B14 is also connected to a pull-up resistor 177 connected to the 5 volt supply to generate a HIGH signal when the buffer 171 is activated but pin B14 of the socket 30 is not connected.
  • the resistor 170 and the switch 162 are also connected to the non-inverted enable input of a second non-inverting tri-state buffer 179, having its input connected to ground and its output connected to the UPGRADE* signal.
  • a LOW signal is asserted at the enable input of each buffer 171, 179, enabling the first buffer 171 and connecting pin B14 to the UPGRADE* signal. If a 487SX - microprocessor is in the socket 30, the UPGRADE* signal is asserted LOW. If another processor is in the socket 30 or the socket 30 is empty when the switch 162 is closed, the UPGRADE* signal is pulled HIGH by the pull- up resistor 177. On the other hand, when the switch 162 is open, a HIGH signal is asserted at the enable input of each buffer 171, 179. Consequently, the second buffer 179 is enabled so that the UPGRADE* signal is connected to ground, asserting a LOW signal.
  • the switch 162 should be opened when a 486SX or a 486DX is inserted. On the other hand, the switch 162 should be closed when the socket 30 is empty. If a 487SX microprocessor is positioned in the socket 30, the switch 162 should be closed because pin B14 of the 487SX processor generates a LOW value on the UPGRADE* signal when the processor is properly placed, and is preferred to remain closed for reasons indicated below. Similarly, the switch 162 and another switch 164 control the routing of pin A13 of the upgrade socket 30.
  • Pin A13 should be connected to the FERR* input of the CUC 36 when used with the 487SX microprocessor, and is not connected for the 486SX and 486DX microprocessors.
  • One end of the switch 164 is connected to ground.
  • the other end of the switch 164 is connected to a resistor 174, which is in turn connected to the 5 volt supply.
  • the resistor 174 and the switch 164 are connected to a first input of a 2- input OR gate 175, and the resistor 170 and the switch 162 are connected to the other input.
  • the output of the OR gate 175 is connected to the inverted enable input of a non-inverting tri-stateable buffer 172.
  • the input of the buffer 172 is connected to pin A13 of the CPU socket 3-0, and the output of the buffer 172 is connected to the FERR* signal.
  • a LOW signal is asserted at the enable input of the buffer 172, connecting pin A13 to the FERR* signal. Because pin A13 should only be connected to the FERR* signal if the 487SX microprocessor is used, both of the switches 162, 164 should be closed only if a 487SX microprocessor is in the socket 30.
  • a pull-up resistor 173 is connected between the 5 volt supply and the FERR* input of the CUC 36 so that no error signal is provided when switches 160 and 162 are both open, as when a 486SX microprocessor is installed or as may accidentally occur. Therefore the FERR* input is at a known level in all cases and does not float.
  • the switch 164 also controls the routing of signals to pin B15 and pin A15 of the CPU socket 30.
  • the switch 164 and the resistor 174 are connected to the inverted enable inputs of 2 non-inverting tri-state buffers 176 and 178 and to the input of an inverter 180.
  • the output of the inverter 180 is connected to the inverted enable input of another non-inverting tri- state buffer 182. According to this arrangement, when the first two buffers 176 and 178 are enabled, the third buffer 182 will be disabled, and conversely, when the third buffer 182 is enabled, the first two buffers 176 and 178 will be disabled.
  • the switch 164 When the switch 164 is closed, the first two buffers 176 and 178 are enabled, and when the switch 164 is opened, the buffer 182 is disabled.
  • the input of the first buffer 176 is connected to the NMI signal, and its output is connected to pin B15.
  • the input of the second buffer 178 is connected to the IGNNE* signal, and its output is connected to pin A15. Therefore, when switch 164 is closed, pin B15 receives the NMI signal and pin A15 is connected to the IGNNE* signal.
  • pin B15 is not connected.
  • Pin A15 is connected to the output of the third buffer 182, which is enabled.
  • the input of the third buffer 182 is connected to the NMI signal.
  • pin B15 should be unconnected and pin A15 should be receiving the NMI signal.
  • pin B15 should receive the NMI signal, and pin A15 should receive the IGNNE* signal. Therefore, for the 486SX microprocessor the switch 164 should be opened, and should be closed for the 487SX or the 486DX microprocessors.
  • switch 160 When no upgrade processor is used, switch 160 should be open or off, switch 162 should be closed or on and switch 164 should be open or off. This setting of switch 160 results in buffer 168 being tri-stated. These settings of switches 162 and 164 result in buffer 172 and buffer 179 being tri-stated and buffer 171 being activated, but the UPGRADE* signal is pulled high by the resistor 177, as an 487SX is not present. Thus these settings effectively disable the switched outputs from the upgrade socket 30. Table 2 below illustrates the proper settings of the switches 160, 162 and 164 for the three microprocessors, and for use when an upgrade microprocessor is not present and the main CPU 20 is controlling the computer system C.
  • any of the three upgrade processors may be used in the socket 30 or none may be used.
  • the UPGRADE* signal is asserted LOW.
  • the UPGRADE* signal is asserted LOW and negated HIGH, and indicates to specific components when the system has been upgraded.
  • the UPGRADE* signal is provided to the input of an inverter 190 and one input of a 2-input AND gate 192.
  • a FLUSH* signal, connected to the upgrade socket 30, is connected to the other input of the AND gate 192.
  • the FLUSH* signal is generated by the CUC 36 when the computer system C wishes to invalidate the contents of the 82395 cache 24 or the cache on the upgrade processor.
  • the FLUSH* input of the cache system 24 using an 82395 is also used in conjunction with the SAHOLD (System Address HOLD) signal to place the cache system 24 in its tri-state test mode as described below. Therefore, the output of the inverter 190 is connected to the SAHOLD input of the 82395 cache system 24, and the output of the AND gate 192 is connected to the FLUSH* input of the 82395 cache system 24.
  • the FLUSH* signal, generated by the CUC 36 in response to processor commands, and the UPGRADE* signal are used to put the 82395 in the cache system 24 in its tri-state test mode, allowing the upgrade microprocessor to control the system, as described below.
  • the UPGRADE* signal may also be provided to other system components to indicate that the upgrade microprocessor has been inserted.
  • the UPGRADE* signal is asserted LOW whenever an upgrade microprocessor is plugged into the socket 30.
  • the 82395 in the cache system 24 must be placed in its tri- state test mode.
  • the cache system's SAHOLD and FLUSH* inputs must both be asserted to cause the cache system 24 to enter test mode, so the inverted UPGRADE* signal is connected directly to the SAHOLD input.
  • the UPGRADE* signal is ANDed with the FLUSH* signal so that the output of the AND gate 192 follows the FLUSH* signal if UPGRADE* is negated, but is held LOW when UPGRADE* is asserted.
  • the AND gate 192 output is provided to the cache system's FLUSH* input, which allows the 82395 in the cache system 24 to be placed in test mode whenever an upgrade processor is present.
  • the AND gate may be replaced by a programmable logic array (PAL) that performs the same function as the AND gate 192 and also allows development of a properly timed FLUSH* signal to allow testing of the memory in the 82395.
  • PAL programmable logic array
  • the SAHOLD and FLUSH* inputs must be asserted during the falling edge of a reset signal. Therefore, when an upgrade microprocessor has been plugged in, the system can be power cycled to reset it.
  • the UPGRADE* signal is automatically generated, which is inverted and connected directly to the SAHOLD input of the cache system 24.
  • the UPGRADE* signal holds the cache system's FLUSH* input LOW through the AND gate 122.
  • the 82395 cache system 24 enters test mode at the falling edge of the RESET signal, floats its outputs, and does not respond to normal system signals.
  • the cache system 24 remains in test mode until the system is reset with SAHOLD and FLUSH* driven inactive. Consequently, the upgrade processor controls the host bus without interference from the 82395 cache system 24 as long as the upgrade processor remains in the socket 30.
  • the main CPU 20 controls the system and the cache system operates normally. Without an upgrade processor, UPGRADE* is negated, and the SAHOLD input remains LOW.
  • the output of the AND gate follows the
  • Upgrading the present system is simple.
  • the upgrade microprocessor is placed in the upgrade socket 30.
  • the switches 160, 162 and 164 are set according to the above disclosure in accordance with the type of upgrade processor used. Then the system is powered up.
  • the main CPU 20 begins its power-on sequence, it addresses the cache system 24, calls for a startup vector, and waits until an answer is received. Until the cache system 24 responds, the main CPU 20 suspends operations and waits. Consequently, the main CPU 20 interacts with no other system components until the cache system 24 provides the startup vector. As described above, however, the cache system 24 is "asleep" and does not respond.
  • the upgrade processor on the other hand, is reset and is connected to the host bus.
  • the upgrade processor does not rely on the cache system 24 for its startup vector, the upgrade processor commences operations and functions as if the main CPU 20 were absent. Thus, the cache system 24 remains "asleep", the main CPU 20 operations are suspended, and the upgrade processor controls the computer system.
  • most of the cache system 24 host bus interface is identical to the host bus interface of the upgrade microprocessor, most of the signals on the cache system 24 may be connected directly to the corresponding signals on the upgrade socket 30.
  • the upgrade host bus and the cache system host bus interface cannot be entirely tied together, because the main CPU 20 uses the processor bus for certain signals that, if tied directly to the corresponding signals of the upgrade socket 30 on the host bus, would cause errors and degrade the performance of the cache system 24.
  • some of the signals must be multiplexed and switched between the upgrade socket 30 and the preferable 80386 main CPU 20 and the preferable 80387 co-processor 22. Because the timing of some of these signals is critical, however, the signals generated by many conventional EISA chip sets cannot be effectively switched to the upgrade socket 30 with active components. Consequently, the signals in the present embodiment are rerouted manually using a set of six switches.
  • the MBC 50 generates the HHOLD (Host bus Hold) signal, which is connected to a first manual switch 200.
  • the other terminal of the switch is connected to the HOLDI input of CUC 36 and a pull-down resistor 202.
  • the HOLDI input on the CUC 36 is used to interface with hold logic inside the CUC 36 for architectures where the processor is located directly on the host bus 28.
  • the HHOLD signal is asserted when another master must have the host bus, and must be provided to the HOLDI input of the CUC 36 when an upgrade microprocessor is being used.
  • the switch 200 is open when the upgrade socket 30 is empty, holding the HOLDI input at a LOW level.
  • the switch 200 is closed, allowing the MBC 50 to provide the HHOLD signal to the HOLDI input of the CUC 36.
  • the PLOCK* signal from the main CPU 20 is provided to a non-inverting buffer 201 whose non- inverted enable input receives the UPGRADE* signal.
  • the output of the buffer 201 is pulled up to 5V by a resistor 203 and is connected to the PLOCK* input of the CUC 36.
  • the PLOCK* signal is provided to the CUC 36, but the PLOCK* input of the CUC 36 is pulled up or inactive when an upgrade processor is present.
  • the PLOCK* signal is used in conjunction with the HHOLD input of the CUC 36 to allow modification of processor lock cycles if desired. In this manner, the CUC 36 receives either the PLOCK* signal at the PLOCK* input or the HHOLD signal at the HOLDI input, allowing the desired control of locked cycles.
  • a buffer 201 can be used with the PLOCK* signal as it is not as timing critical as the HHOLD signal in the preferred embodiment.
  • Both the main CPU 20 and the upgrade socket 30 include HLDA (Hold Acknowledge) outputs.
  • the controlling processor responds by asserting the HLDA signal, indicating that the processor has given the bus to another system bus master.
  • HLDA Hardware Hold Acknowledge
  • a switch 204, 206 is connected between each of the processor's HLDA outputs and the PHLDA (Processor Hold Acknowledge) input of the CUC 36. Consequently, if the upgrade socket 30 is empty, the switch 204 between the upgrade socket 30 and the PHLDA input is open, and the switch 206 between the main CPU 20 and the PHLDA input is closed. Conversely, when an upgrade processor has been plugged into the socket 30, the upgrade socket switch 204 is closed and the main CPU switch 206 is open.
  • both the main CPU 20 and the upgrade socket 30 provide an ADS* (Address Status) output signal to indicate that a valid address is on the address bus.
  • ADS* Address Status
  • the proper ADS* signal must be provided to the PADS* (Processor Address Status) input of the CUC 36.
  • the CUC 36 uses this input to provide a ready indication during certain special cycles and conditions. Therefore, a switch 208 is provided between the main CPU 20 ADS* output and the PADS* input, and another switch 210 controls the connection between the upgrade socket 30 ADS* output and the PADS* input. If an upgrade processor is in the upgrade socket 30, the upgrade switch 210 is closed and the main CPU switch 208 is open, and vice versa if the upgrade socket 30 is empty.
  • the numeric co-processor 22 generates an ERROR* signal to indicate an error condition from the numeric co-processor extension.
  • the ERROR* signal is provided to the CUC 36 through a closed switch 212.
  • the 487SX and 486DX microprocessors generate a FERR* signal when floating pointing errors occur, which signal is routed as described above, relating to buffers 168 and 172, to develop the FERR* signal shown illustratively in Fig. 5. Therefore, the main CPU switch 212 must be open if an upgrade processor is present. Unlike the upgrade socket HLDA and ADS* outputs, no switch controls the connection between the FERR* signal from the upgrade socket switching logic and the CUC 36.
  • the CUC 36 can be redesigned to automatically handle the switching performed by the switches 200, 204, 206, 208, 210 and 212 by using the UPGRADE* signal and to resolve the timing problems, if desired.
  • systems according to the present invention allow the upgrade of an 80386/82395 system to a 486 processor family system without the need for replacing the system board or even a processor board, at the small expense of an extra socket and several switches.
  • the foregoing disclosure and description of the invention are illustrative and explanatory thereof, and various changes in the size, shape, materials, components, circuit elements, wiring connections and contacts as well as in the details of the illustrated circuitry and construction may be made without departing from the spirit of the invention.

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  • Multi Processors (AREA)

Abstract

On peut procéder à l'extension d'un système d'ordinateur en le faisant évoluer d'une unité centrale (CPU) principale de modèle 386 vers un microprocesseur de modèle 486, sans échanger la carte du processeur ni remplacer le microprocesseur 386. L'ordinateur comprend à cet effet un support vide unique dans lequel on peut adapter un microprocesseur 486SX, 487SX ou 486DX. N'importe lequel de ces microprocesseurs peut être enfiché dans le support, ce qui amène le système d'antémémoire contenant un modèle 82395 à passer à un mode test à trois états et à suspendre le fonctionnement de l'unité centrale principale. Pour corriger les variations des agencements des broches de chaque processeur, divers signaux de système sont acheminés au moyen de commutateurs vers différentes broches pour différents microprocesseurs. Des signaux de système spécifiques sont en plus réacheminés parmi les composants du système au moyen d'un groupe de six commutateurs pour obtenir un fonctionnement correct lorsque le support est vide et lorsqu'il est occupé. En réglant de façon appropriée tous les commutateurs, les signaux corrects sont fournis à chaque broche du microprocesseur d'extension. Pendant que le système d'antémémoire reste en mode test, l'unité centrale principale reste essentiellement inactive et le processeur d'extension commande le système d'ordinateur.
EP93910881A 1992-05-04 1993-04-28 Circuit d'acheminement de signaux pour support d'extension de microprocesseur Withdrawn EP0592650A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US87844092A 1992-05-04 1992-05-04
US878440 1992-05-04
PCT/US1993/004005 WO1993022730A1 (fr) 1992-05-04 1993-04-28 Circuit d'acheminement de signaux pour support d'extension de microprocesseur

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EP0592650A1 true EP0592650A1 (fr) 1994-04-20

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EP93910881A Withdrawn EP0592650A1 (fr) 1992-05-04 1993-04-28 Circuit d'acheminement de signaux pour support d'extension de microprocesseur

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EP (1) EP0592650A1 (fr)
JP (1) JPH06504867A (fr)
AU (1) AU4221893A (fr)
CA (1) CA2112752A1 (fr)
WO (1) WO1993022730A1 (fr)

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Publication number Priority date Publication date Assignee Title
US5600802A (en) * 1994-03-14 1997-02-04 Apple Computer, Inc. Methods and apparatus for translating incompatible bus transactions
US6732266B1 (en) * 2000-08-28 2004-05-04 Advanced Micro Devices, Inc. Method and apparatus for reconfiguring circuit board and integrated circuit packet arrangement with one-time programmable elements
CN111221390A (zh) * 2019-12-31 2020-06-02 苏州浪潮智能科技有限公司 一种兼容分时连接CPU和Tri mode卡的背板及实现方法

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JPH02245811A (ja) * 1989-03-18 1990-10-01 Seiko Epson Corp 情報処理装置
US5041962A (en) * 1989-04-14 1991-08-20 Dell Usa Corporation Computer system with means for regulating effective processing rates
GB8911023D0 (en) * 1989-05-13 1989-06-28 Gill Bernard W Computer upgrading
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See references of WO9322730A1 *

Also Published As

Publication number Publication date
CA2112752A1 (fr) 1993-11-11
WO1993022730A1 (fr) 1993-11-11
JPH06504867A (ja) 1994-06-02
AU4221893A (en) 1993-11-29

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