EP0574810B1 - Anzeigevorrichtung - Google Patents

Anzeigevorrichtung Download PDF

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Publication number
EP0574810B1
EP0574810B1 EP93109196A EP93109196A EP0574810B1 EP 0574810 B1 EP0574810 B1 EP 0574810B1 EP 93109196 A EP93109196 A EP 93109196A EP 93109196 A EP93109196 A EP 93109196A EP 0574810 B1 EP0574810 B1 EP 0574810B1
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EP
European Patent Office
Prior art keywords
scanning
scanning lines
blocks
display
lines
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EP93109196A
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English (en)
French (fr)
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EP0574810A1 (de
Inventor
Kazunori C/O Canon Kabushiki Kaisha Katakura
Shinjiro C/O Canon Kabushiki Kaisha Okada
Yutaka C/O Canon Kabushiki Kaisha Inaba
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Canon Inc
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Canon Inc
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/207—Display of intermediate tones by domain size control

Definitions

  • the present invention relates to a display apparatus for use in a television receiver, a computer terminal, an image data processing apparatus, such as a video camera view finder, etc., particularly a planar or flat panel-type display apparatus having scanning lines and data (signal) lines.
  • Planar display apparatus include, for example, a type using electron-discharging elements at respective pixels and a type using a liquid crystal for constituting pixels.
  • a liquid crystal display apparatus using a liquid crystal has been widely used and is calling a further attention.
  • liquid crystal display apparatus wherein a liquid crystal material is disposed between scanning lines (scanning electrodes) and data lines (data electrodes) constituting an electrode matrix so as to form a large number of pixels for displaying image data.
  • the display apparatus is driven in a multiplexed manner such that an address or scanning signal is sequentially applied to the scanning electrodes, and prescribed data signals are applied in parallel to the data electrodes in synchronism with the address signal.
  • the voltage change with time (i.e., voltage waveform) applied between electrodes is different depending on whether the data signal applied thereto is for writing "black” or "white", so that the optical response of the pixel is different. More specifically, when the pixel concerned is on a selected scanning electrode, the pixel is switched to a black or white state. However, when the pixel concerned is on a non-selected scanning electrode, the pixel causes a change in luminance level depending on the data signal waveform while retaining the black or white.
  • the pixels on the data electrode cause a change in luminance level in a cycle of alternation of the black and white signals throughout the period of non-selection of the pixels. If the alternation cycle is below a certain constant determined depending on the difference in luminance corresponding to the application of the black and white signals.
  • DE-C-3 613 446 discloses a liquid crystal light modulation device comprising a matrix of pixels.
  • the matrix of pixels is constituted by a group of scanning electrodes and a group of signal electrodes spaced from each other by a gap. In the gap provided therebetween, a ferroelectric liquid crystal material is filled.
  • a scanning line driver circuit and a common display signal generator are connected to the scanning electrodes and the signal electrodes, respectively, for driving one of plural selectable blocks, e.g. four blocks.
  • the scanning line driver circuit comprises plural separate logic units for selecting one of the plural blocks.
  • a selection signal is sequentially applied to the signal lines for sequentially supplying the signal lines with information signals. Consequently, a block is selected for the purpose of selecting a part of scanning lines among all the scanning lines (i.e., a partial rewrite) and, in the selected block, the scanning lines are subjected to the non-interlaced scanning.
  • EP-A-0 434 042 describes a display apparatus wherein a ferroelectric liquid crystal is disposed between a group of scanning electrodes and a group of data electrodes constituting an electrode matrix.
  • a drive means constituted by a graphic controller applies a scanning signal to the scanning electrodes and data signals to the data electrodes in synchronism with the scanning signal.
  • the scanning electrodes are divided into a plurality of blocks, and the scanning electrodes are selected, while at least one scanning electrode is skipped apart. That is, all the scanning lines in each block are subjected to interlaced scanning, and the blocks are sequentially selected from the top to the bottom without skipping, i.e. in a non-interlaced manner.
  • this object is accomplished by a display apparatus as set out in claim 1, and by a display method as set out in claim 10.
  • a selection signal is not applied to the scanning lines with skipping of a prescribed number of scanning lines from the beginning to the end of one vertical scanning as in the known drive scheme, but the blocks are selected with a spacing of at least one block, i.e., in a manner which may be called a "block-interlaced scanning" scheme.
  • the black data signal and the white data signal continually alternate until the finish of linesequential scanning within one block, so that the lowering in frequency of alternation of the black and white data signal is suppressed, thereby preventing the occurrence of flicker.
  • non-interlaced scanning is performed within each block so that the observability of a motion picture is maintained.
  • Figure 1 is a circuit diagram for illustrating a basic structure of an embodiment of the display apparatus according to the invention.
  • Figure 2 is a time chart showing a set of scanning signals used in the display apparatus of Figure 1.
  • Figure 3 is a block diagram of a display apparatus or system according to the present invention.
  • Figure 4 is a partial schematic plan view of a liquid crystal display unit (picture area) used in the present invention
  • Figure 5 is a schematic sectional view thereof.
  • Figures 6 and 10 are respectively a schematic view of blocks of scanning lines.
  • Figures 7, 9, 11, and 12 are respectively a conceptual view of memories used in the invention.
  • FIG. 8 is a block diagram showing an algorithm used in the invention.
  • Figure 13 shows a set of drive signal waveforms used in the drive system of the present invention.
  • Figure 14 is a time chart showing time correlation between signal transfer and driving.
  • a display apparatus having a plurality of scanning lines wherein a display screen or panel constituted by the scanning lines is divided into at least three regions (blocks) and the blocks are sequentially selected so that neighboring blocks are not consecutively selected, i.e., the blocks are selected with spacing of at least one block, and adjacent scanning lines within each block are consecutively selected in a non-interlaced scanning mode.
  • Figure 1 is a circuit diagram for illustrating a display apparatus. More specifically, Figure 1 shows a display unit DPU comprising a total of 14 scanning lines (C11 ... C14, C21 ... C24 ..., C41 ... C44) divided into four blocks (BK1, BK2 ..., BK4) each including four adjacent scanning lines.
  • a display unit DPU comprising a total of 14 scanning lines (C11 ... C14, C21 ... C24 ..., C41 ... C44) divided into four blocks (BK1, BK2 ..., BK4) each including four adjacent scanning lines.
  • CEL refers to a pixel and CELi,j generally refers to a pixel formed at the intersection of an i-th scanning line and a j-th data signal line.
  • Each pixel provides a certain display data (optical data) based on a combination of two signals applied to the pixel, i.e., a signal supplied to an associated scanning line from a scanning signal application circuit 102 and a signal supplied to an associated one of data signal lines (S1 ... Sm).
  • a block BK1 is selected first, and scanning lines C11 - C14 are sequentially scanned. Then, instead of a block BK2, a block BK3 is selected, and scanning lines C31 - C34 are sequentially scanned. Thereafter, the block BK2 is selected, and scanning lines C21 - C24 are sequentially scanned. Then, a block BK4 is selected, and scanning lines C41 - C44 are sequentially scanned.
  • the blocks are scanned in a regularly or irregularly interlaced manner, and the scanning lines in each block are scanned in a non-interlaced manner.
  • the scanning signal is depicted in a simple rectangular waveform in Figure 2. Actually, however, another appropriate waveform of scanning signal may also be used depending on the structure of the pixel, etc.
  • a scanning signal can of course include a reset signal component (or clear signal component) for once resetting the display state of a pixel.
  • the scanning signal can also include an auxiliary signal component for stabilizing the electrical or physical characteristic of a pixel without changing the display state of the pixel.
  • the timing of scanning signals applied to adjacent scanning lines in a block may be such that the falling of a preceding signal and the rising of a subsequent signal coincide each other or are spaced from each other with a prescribed interval.
  • such successively applied two scanning signals can overlap each other. More specifically, in such a case, while a scanning line receives a signal component for display, a subsequent scanning line may receive a reset signal component so as to effect a high speed display.
  • the number of scanning lines selected at a time in each block need not be one, but a plurality of adjacent scanning lines can be selected simultaneously and such selection may be continued sequentially with respect to other pluralities of adjacent scanning lines.
  • adjacent two scanning lines C11 and C12 are first selected, i.e., supplied with a scanning signal, simultaneously. Then, scanning lines C13 and C14 are selected simultaneously. Then, a subsequent block BK3 is selected with skipping of the block BK2, and C31 and C32 are selected simultaneously, followed by simultaneous selection of C33 and C34. Such operation is continued to effect one frame display.
  • one pixel e.g., CELi,j
  • another pixel CELi+1,j may be used as a compensation pixel for effecting a display compensating for a possible difference in display state at the standard pixel from the time display state due to, e.g., a change in environmental temperature.
  • Such a method is suitably adopted in gradational display performed by forming a transparent region and an opaque region in a pixel unit and by changing the ratio of the regions.
  • the pixels used in the present invention may suitably comprise a liquid crystal cell constituted, e.g., as a simple matrix display panel, an electro-luminescent cell including an electron-discharge device, or a liquid crystal cell having a switching element, such as a thin film transistor or an MIM element, at each pixel.
  • a liquid crystal cell constituted, e.g., as a simple matrix display panel, an electro-luminescent cell including an electron-discharge device, or a liquid crystal cell having a switching element, such as a thin film transistor or an MIM element, at each pixel.
  • a liquid crystal cell is particularly preferred because of its economical production process, and suitable examples of the liquid crystal may include a twisted nematic liquid crystal and a ferroelectric liquid crystal as will be described hereinafter.
  • a light source as an illumination means may be disposed on one side thereof so as to improve the contrast and luminance.
  • recording means for recording a display image may be effected on recording media, such as magnetic media, optical media, semi-conductor memories, paper and plastic sheets, and recording means therefor may include a magnetic head, an optical head, a thermal head, and an ink jet head, for example.
  • recording media such as magnetic media, optical media, semi-conductor memories, paper and plastic sheets
  • recording means therefor may include a magnetic head, an optical head, a thermal head, and an ink jet head, for example.
  • the display apparatus according to the present invention may suitably be applied to a display method using a ferroelectric liquid crystal excellent in responsive characteristic and providing a wide viewing angle, particularly a gradational (gray-scale) display method using a ferroelectric liquid crystal (hereinafter sometimes abbreviated as "FLC").
  • FLC ferroelectric liquid crystal
  • gradational display methods may be representatively classified into (1) a method of dividing a pixel into sub-pixels which are controlled independently (dither method), (2) a method of forming a potential gradient in a pixel to divide the pixel into display regions (potential gradient method), (3) a method of applying a unidirectional electric field to a liquid crystal in a monostable state to control the deviation of the liquid crystal molecular long axis depending on the intensity of the electric field, and (4) a method of changing the liquid crystal layer thickness within a pixel to change the electric field intensity applied to the liquid crystal layer within the pixel, thus effecting a gradational display.
  • a problem in such a gradational display system using an FLC is that it causes a substantial change in threshold value corresponding to a temperature change, so that it is difficult to maintain an identical gradation level in resistance to a temperature change.
  • a driving scheme which may be called a pixel shift method (two pulse method) in U.S. Patent Application Serial No. 984,694, filed December 2, 1992 entitled “Liquid Crystal Display Apparatus”.
  • the driving scheme includes: (1) writing line-sequentially from a first line to an n-th line, while (2) simultaneously selecting consecutive two scanning lines (L-th and L-th+1) at a selection time and, at a subsequent selection time, selecting simultaneously consecutive two scanning lines (L-th+1 and L-th+2) deviated by one line, wherein L is an integer satisfying 1 ⁇ L ⁇ n.
  • the L-th scanning line is a scanning line for temperature compensation for the L-th+1 scanning line. More specifically, if the liquid crystal cell is at a standard temperature, only the L-th+1 scanning line is written and, if the temperature deviates, the L-th line is written.
  • display data to be displayed on the L-th+1 scanning line is shifted onto the L-th scanning line in accordance with a temperature change.
  • an undesirable display state of a pixel on one scanning line of adjacent at least two scanning lines is compensated by a display state of a pixel on the other scanning line. That is, a synthetic display state of adjacent pixels on a data line and at least two scanning lines is used as a unit of gradational display.
  • an undesirable display state of a pixel in the unit can be compensated by a display state of the remaining pixel in the unit, whereby a normal display can be achieved as a whole.
  • the simultaneously selected (at least) two scanning lines are supplied with mutually different scanning signals, which are determined to provide continuous thresholds at two pixels formed at the intersections of a data line and the two scanning lines.
  • the provision of "continuous threshold” is a condition for realizing a smooth data shift between two scanning lines which are sequentially written by a line-sequential scan.
  • a pixel is required to have a distribution of thresholds with respect to transmittance.
  • image data changes its position according to a temperature change, so that it is difficult to completely display a one frame picture. More specifically, the pixels on the first scanning line are not provided with a scanning line to which image data is shifted, and the pixels on the n-th scanning line are not subjected to an operation after the image data shift according to a temperature change.
  • the present invention may be suitably applied to suppressing the flickering liable to be caused in the above-mentioned gradational drive scheme.
  • FIG. 3 is a block diagram showing a liquid crystal display apparatus according to a first embodiment of the present invention.
  • the display apparatus includes a liquid crystal display unit (panel) 101, a scanning signal application circuit 102, a data signal application circuit 103, a scanning signal control circuit 104, a drive control circuit 105, a data signal control circuit 106 and a graphic controller 107.
  • Data supplied from the graphic controller 107 through the drive control circuit 105 enter the scanning signal control circuit 104 and the data signal control circuit 106 where they are converted into address data and display data, respectively.
  • the scanning signal application circuit 102 According to the address data, the scanning signal application circuit 102 generates scanning signals which are supplied to the scanning electrodes in the liquid crystal display unit 101. Further, according to the display data, the data signal application circuit 103 generates data signals, which are supplied to the data electrodes in the liquid crystal display unit 101.
  • Figure 4 is an enlarged partial view of the liquid crystal display unit 101 which includes scanning electrodes C1 - C6 ... and data electrodes S1 - S6 ... disposed so as to form an electrode matrix and form pixels each constituting a display unit, including, e.g., a pixel P22 formed at the intersection of a scanning electrode C2 and a data electrode S2.
  • Figure 5 is a partial sectional view of the display unit taken along the line A - A in Figure 4.
  • the liquid crystal display unit 101 includes glass substrates 302 and 304 and a ferroelectric liquid crystal 303 disposed between the substrates 302 and 304 and in a cell structure forming a cell gap defined by a spacer 306. Further, an analyzer 301 and a polarizer 305 are disposed in cross nicols so as to sandwich the cell structure.
  • the cell structure shown in Figures 4 and 5 comprises a pair of substrates 302 and 304 made of glass plates or plastic plates which are held with a predetermined gap with spacers 306 and sealed with an adhesive to form a cell structure filled with a liquid crystal.
  • an electrode group e.g., an electrode group for applying scanning voltages of a matrix electrode structure
  • a predetermined pattern e.g., of a stripe pattern.
  • another electrode group e.g., an electrode group for applying data voltages of the matrix electrode structure
  • another electrode group e.g., an electrode group for applying data voltages of the matrix electrode structure
  • the alignment control films may be directly disposed over the transparent electrodes C1 - C6 and S1 - S6 formed on the substrates 304 and 302, respectively.
  • insulating films for short circuit prevention (not shown) and alignment control films (not shown) may be disposed, respectively.
  • Examples of the material constituting the alignment control films may include inorganic insulating materials, such as silicon monoxide, silicon dioxide, aluminum oxide, zirconia, magnesium fluoride, cerium oxide, cerium fluoride, silicon nitride, silicon carbide, and boron nitride; and organic insulating materials, such as polyvinyl alcohol, polyimide, polyamide-imide, polyester-imide, polyparaxylylene, polyester, polycarbonate, polyvinyl acetal, polyvinyl chloride, polyamide, polystyrene, cellulose resin, melamine resin, urea resin and acrylic resin.
  • the above-mentioned alignment (control) film of an insulating material can be also used as an insulating film for short circuit prevention.
  • the alignment control films of an inorganic insulating material or an organic insulating material may be provided with an uniaxial alignment axis by rubbing the surface of the film after formation thereof in one direction with velvet, cloth or paper to form the uniaxial alignment axis.
  • the insulating films for short circuit prevention may be formed in a thickness of 20 nm (200 ⁇ ) or larger, preferably 50nm (500 ⁇ ) or larger, with an inorganic insulating material, such as SiO 2 , TiO 2 , Al 2 O 3 , Si 3 N 4 and BaTiO 3 .
  • the film formation may for example be effected by sputtering, ion beam evaporation, or calcination of an organic titanium compound, an organic silane compound, or an organic aluminum compound.
  • the organic titanium compound may for example be an alkyl (methyl, ethyl, propyl, butyl, etc.) titanate compound, and the organic silane compound may be an ordinary silane coupling agent.
  • the thickness of the insulating films for short circuit prevention is below 20nm (200 ⁇ ) a sufficient short circuit prevention effect cannot be accomplished.
  • the thickness is above 500nm (5000 ⁇ )
  • the effective voltage applied to the liquid crystal layer is decreased substantially, so that the thickness may be set to 500nm (5000 ⁇ ) or less, preferably 200nm (2000 ⁇ ) or less.
  • the liquid crystal material suitably used in the present invention is a chiral smectic liquid crystal showing ferroelectricity. More specifically, liquid crystals in chiral smectic C phase (SmC*), chiral smectic G phase (SmG*), chiral smectic F phase (SmF*), chiral smectic I phase (SmI*) or chiral smectic H phase (SmH*) may be used.
  • SmC* chiral smectic C phase
  • SmG* chiral smectic G phase
  • SmF* chiral smectic F phase
  • SmI* chiral smectic I phase
  • SmH* chiral smectic H phase
  • ferroelectric liquid crystals may be disclosed in, e.g., LE JOURNAL DE PHYSIQUE LETTERS, 36 (L-69) 1975, "Ferroelectric Liquid Crystals”; Applied Physics Letters 36 11, 1980, “Submicro Second Bi-stable Electrooptic Switching in Liquid Crystals”; Kotai Butsuri (Solid-State Physics) 16 (141) 1981, “Ekisho (Liquid Crystals)”; U.S. Patents Nos. 4,561,726; 4,589,996; 4,592,858; 4,596,667; 4,613,209; 4,614,609; 4,622,165, etc. Chiral smectic liquid crystals disclosed in these references can be used in the present invention.
  • ferroelectric liquid crystal may include decyloxybenzylidene-p'-amino-2-methylbutylcinnamate (DOBAMBC), hexyloxybenzylidene-p'-amino-2-chloropropylcinnamate (HOBACPC), and 4-O-(2-methyl)butylresorcylidene-4'-octylaniline (MBRA 8).
  • DOBAMBC decyloxybenzylidene-p'-amino-2-methylbutylcinnamate
  • HOBACPC hexyloxybenzylidene-p'-amino-2-chloropropylcinnamate
  • MBRA 8 4-O-(2-methyl)butylresorcylidene-4'-octylaniline
  • the field frequency is 40 Hz or higher, flickering caused by scanning drive is suppressed, so that one picture is designed to be formed by two times of vertical scanning.
  • the whole picture area composed of 512 lines is divided into 16 blocks B1 - B16.
  • blocks B1, B3, B5, B7, B9, B11, B13 and B15 are selected and, in a second field, blocks B2, B4, B6, B8, B10, B12, B14 and B16 are selected.
  • non-interlaced scanning is performed.
  • a memory 500 as shown in Figure 7 is provided in the scanning signal control circuit 104.
  • the memory 500 includes a scanning address memory M1, an address increment memory M2, a line-number counter memory M3, a block-number counter memory, and address table memories MT(1) - MT(16).
  • the number of 1 is set at the address increment memory M2, and the 16 numbers of 1, 65, 129, 193, 257, 321, 385, 449, 33, 97, 161, 225, 289, 353, 417 and 481 are set at the address table memories MT(1) - MT(16), respectively, as the starting scanning address (positional ranks of the starting scanning electrodes) among the entire scanning electrodes for the first vertical scanning and the second vertical scanning in that order.
  • the content of the scanning address memory means the scanning address.
  • the content of the address increment memory M2 means the number of scanning electrodes covered by one-time of scanning (namely "1" means that every line is scanned in a non-interlaced manner).
  • the content of the line-number counter memory means the number of times of scanning effected at that time in each block.
  • the content of the block-number counter memory M4 means the ordinal number of block for which the scanning is performed at that time throughout the first vertical scanning and second vertical scanning.
  • the contents of the address table memories MT(1) - MT(16) mean the scanning addresses from which the scanning is started for the respective blocks.
  • Figure 8 is a flow chart showing an algorithm for determining the scanning addresses.
  • the number of "1" is set in the block-number counter memory M4 for initialization.
  • the number in the block-number counter memory M4 is checked as to whether it exceeds 16 (M4 > 16) in order to judge whether all the blocks have been written.
  • the line-number counter memory is initialized for scanning in each block. First of all, a number of "1" is set in the line-number counter memory M3 for first scanning in the block.
  • the number of the block is checked according to the content of the block-number counter memory, and the starting scanning address in the block is checked according to the content of the corresponding address table memory MT to set the starting scanning address at the scanning address memory M1.
  • a number "1" is added to the block-number counter memory M4.
  • the scanning address is transferred.
  • the content of the address increment memory M2 is added to the content of the scanning address memory M1, and a number of "1" is added to the line-number counter memory M3.
  • the content of the address table memory MT is set to the scanning address memory M1 based on the content of the block-number counter memory M4, and this operation is repeated 16 times, during each of which the steps of sending the scanning address to the scanning signal application circuit and increasing the content of the scanning line address memory by "1" (the content of the address increment memory M2) are repeated 32 times.
  • the scanning address is transferred 16x32 times, the operation is restored to the beginning.
  • a number of "1" is set at each of the scanning address memory M1, the line-number counter memory M3 and the block-number counter memory M4.
  • the 1st, 3rd, 5th ... to 511th lines are sequentially selected to complete the first vertical scanning, and subsequently the 2nd, 4th, ... to 512th lines are sequentially selected to complete the second vertical scanning, whereby one whole picture is written.
  • the 8-interlaced scanning scheme is adopted so as to obviate flickering, while the flickering is removed due to an increased frequency, the observability of a motion picture is remarkably impaired because a picture is constituted by scanning of every 8th line in comparison with the non-interlaced scanning.
  • the apparatus used in the first embodiment may be driven by selecting the blocks in the order of B1, B10, B3, B8, B13, B2, B15, B12, B5, B14, B7, B16, B9, B6, B11 and B4 to achieve a similar effect.
  • 16 numbers of 1, 289, 65, 225, 385, 33, 449, 353, 129, 417, 193, 481, 257, 161, 321 and 97 are set at the address table memories MT(1) - MT(16), respectively, as shown in Figure 9.
  • a liquid crystal display apparatus is constituted by 1024 scanning electrodes and 1280 data electrodes disposed to form an electrode matrix.
  • the 1024 scanning lines constituting a whole display area are divided into 32 blocks B1 - B32 each including 32 lines.
  • blocks B1, B5, B9, B13, B17, B21, B25 and B29 are selected in this order.
  • blocks B3, B7, B11, B15, B19, B23, B27 and B31 are selected in a second field;
  • blocks B2, B6, B10, B14, B18, B22, B26 and B30 are selected in a third field;
  • blocks B4, B8, B12, B16, B20, B24, B28 and B30 are selected in a fourth field.
  • the scanning lines are subjected to non-interlaced scanning.
  • a memory 800 as shown in Figure 11 is provided in the scanning signal control circuit.
  • a number of 1 is set at the address increment memory M2
  • 32 numbers of 1, 129, 257, 385, 513, 641, 769, 897, 65, 193, 321, 449, 577, 705, 833, 961, 33, 161, 289, 417, 545, 673, 801, 929, 97, 225, 353, 481, 609, 737, 865 and 993 are set at the address table memories MT(1) - MT(32), respectively, as the starting scanning addresses among the entire scanning lines for the first, second, third and fourth vertical scanning.
  • the scanning address is performed according to the same algorithm as shown in Figure 8 except that the number of blocks for judging completion of writing in all the blocks is changed to M4 > 32 at step 2 in Figure 8.
  • a pixel P22 receives a black signal and a white signal alternately for each one line.
  • the apparatus in the third embodiment may be driven by selecting the blocks in the order of B1, B18, B27, B12, B5, B22, B31, B8, B17, B2, B23, B20, B29, B14, B11, B32, B13, B26, B3, B16, B9, B30, B19, B4, B25, B10, B7, B28, B21, B6, B15 and B24 to achieve a similar effect.
  • 32 addresses of 1, 545, 833, 353, 129, 673, 961, 225, 513, 33, 705, 609, 897, 417, 321, 993, 385, 801, 65, 481, 257, 929, 577, 97, 769, 289, 193, 865, 641, 161, 449 and 737 are set at the address table memories MT(1) - MT(32), respectively, as shown in Figure 12.
  • Figure 13 shows a set of drive signal waveforms used in evaluation of the above embodiments and Figure 14 is a time chart showing correlation between signal transfer and drive for driving an apparatus shown in Figure 3.
  • each block is designed to have 32 scanning electrodes. This is because patterns, such as a font, an icon and a mouse mark have a height of 32 dots or less and no flicker due to scanning drive is caused by 32 lines. If the number of scanning electrodes in one block is increased, the chance of a block boundary appearing in a display pattern such as a font is lowered, thus providing a good observability, but the liability of flicker due to scanning drive is reversely increased. If the number of scanning electrodes in one block is decreased, the chance of a block boundary appearing in a display pattern such as a font is increased.
  • the number of scanning electrodes in one block is (i) not as large as to cause flicker due to scanning drive, and (ii) sufficiently large as to be equal to or larger than the number of dots in height direction of a display pattern, such as a font, an icon or a mouse mark. As far as the above conditions (i) and (ii) are satisfied, a larger number provides a better observability.
  • the scanning lines are divided into a plurality of blocks each including a plurality of adjacent scanning lines, and the blocks are sequentially selected with a spacing of at least one block between successively selected blocks while consecutively selecting the adjacent scanning liens within each block.

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  • Engineering & Computer Science (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
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Claims (10)

  1. Anzeigevorrichtung, mit:
    einer Matrix aus einer Gruppe von Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44) und einer Gruppe von Datensignalleitungen (S1 ... Sm), die die Abtastleitungen (C11, ... C14, C21 ... C24, C41 ... C44) kreuzen,
    Bildpunkten (CEL), die jeweils an einer Kreuzung der Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44) und den Datensignalleitungen (S1 ... Sm) gebildet sind, und einer Ansteuervorrichtung (104 bis 106) zum Zuführen von Ansteuersignalen zu der Matrix, um eine Anzeige an den Bildpunkten (CEL) zu bewirken, wobei die Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44) in zumindest vier Blöcke (BK1, BK2, ..., BK4) mit jeweils einer Vielzahl von benachbarten Abtastleitungen (C11, ... C14, C21 ... C24 ..., C41 ... C44) aufgeteilt sind,
    dadurch gekennzeichnet, daß
    die Ansteuervorrichtung (104 bis 106) eine Abtastvorrichtung (104) enthält zum sequentiellen Ausiwählen der zumindest vier Blöcke (BK1, BK2, ..., BK4) mit Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44), so daß die Blöcke (BK1, BK2, ..., BK4) sequentiell mit einem Abstand von zumindest einem Block zwischen aufeinanderfolgend ausgewählten Blocken aufgewählt werden und die benachbarten Abtastleitungen (C11, ... C14, C21... C24, ..., C41 ... C44) innerhalb eines jeden gewälhten Blocks aufeinanderfolgend ausgewählt werden.
  2. Vorrichtung nach Anspruch 1, wobei die Bildpunkte (CEL) ein Flüssigkristall aufweisen.
  3. Vorrichtung nach Anspruch 1, wobei die Bildpunkte (CEL) ein ferroelektrisches Flüssigkristall aufweisen.
  4. Vorrichtung nach Anspruch 1, wobei die Bildpunkte (CEL) ein Flüssigkristall aufweisen und jeweils mit einem Schaltelement ausgestattet sind.
  5. Vorrichtung nach Anspruch 1, wobei jeder der zumindest vier Blöcke (BK1, BK2, ..., BK4) die gleiche Zahl von Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44) enthält.
  6. Vorrichtung nach Anspruch 1, wobei die zumindest vier Blöcke (BK1, BK2, ..., BK4) in einer unregelmäßigen Sequenz ausgewählt werden.
  7. Vorrichtung nach Anspruch 1, weiterhin umfassend eine Beleuchtungsvorrichtung zum Beleuchten der Bildpunkte (CEL).
  8. Vorrichtung nach Anspruch 1, weiterhin umfassend eine Grafiksteuerung (107) zum Steuern eines Anzeigebilds.
  9. Vorrichtung nach Anspruch 1, weiterhin umfassend eine Aufzeichnunsvorrichtung zum Aufzeichnen eines Anzeigebilds.
  10. Anzeigeverfahren, mit:
    Bereitstellen einer Anzeigevorrichtung umfassend eine Matrix aus einer Gruppe von Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44) und einer Gruppe von Datensignalleitungen (S1 ... Sm), die die Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44) kreuzen,
    Bildpunkte (CEL), die jeweils an einer Kreuzung der Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44) und der Dattensignalleitung (S1 ...Sm) gebildet sind, und eine Ansteuervorrichtung (104-3-bis 106) zum Zuführen von Ansteuersignalen zu der Matrix, um eine Anzeige an den Bildpunkten (CEL) zu bewirken;
    Aufteilen der Abtastleitungen ((C11, ... C14, C21 ... C24, ..., C41 ... C44) in zumindest vier Blöcke (BK1, BK2, ..., BK4) jeweils mit einer Vielzahl von benachbarten Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44);
    gekennzeichnet durch weiterhin umfassend den Schritt sequentielles Auswählen der zumindest vier Blöcke (BK1, BK2, ..., BK4) von Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44), so daß die Blöcke (BK1, BK2, ..., BK4) sequentiell mit einem Abstand von zumindest einem Block zwischen aufeinanderfolgend ausgewählten Blöcken ausgewählt werden und die benachbarten Abtastleitungen (C11, ... C14, C21 ... C24, ..., C41 ... C44) innerhalb eines jeden ausgewählten Blocks aufeinanderfolgend ausgewählt werden.
EP93109196A 1992-06-11 1993-06-08 Anzeigevorrichtung Expired - Lifetime EP0574810B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP17596392 1992-06-11
JP175963/92 1992-06-11

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EP0574810A1 EP0574810A1 (de) 1993-12-22
EP0574810B1 true EP0574810B1 (de) 1998-09-09

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Publication number Priority date Publication date Assignee Title
US6054230A (en) * 1994-12-07 2000-04-25 Japan Gore-Tex, Inc. Ion exchange and electrode assembly for an electrochemical cell
GB0323622D0 (en) 2003-10-09 2003-11-12 Koninkl Philips Electronics Nv Electroluminescent display-devices
GB0323767D0 (en) 2003-10-10 2003-11-12 Koninkl Philips Electronics Nv Electroluminescent display devices
KR20070052470A (ko) * 2005-11-17 2007-05-22 삼성전자주식회사 액정 표시 장치 및 액정 표시 장치의 구동 방법

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DE3613446A1 (de) * 1985-04-22 1986-11-27 Canon K.K., Tokio/Tokyo Verfahren und vorrichtung zum ansteuern einer lichtmodulationsvorrichtung
GB2218842A (en) * 1988-05-18 1989-11-22 Stc Plc Liquid crystal cell addressing
US5172105A (en) * 1989-12-20 1992-12-15 Canon Kabushiki Kaisha Display apparatus

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DE69320870D1 (de) 1998-10-15
DE69320870T2 (de) 1999-04-01
ATE171003T1 (de) 1998-09-15
EP0574810A1 (de) 1993-12-22

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